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How using the L2RAM of C674x DSP in IPNC

Hi,

I used the IPNC of APPRO Corp.

Now, I want to allocate a memory in L2RAM of DSP.

I find in the file "config_512M.bld" have the following code:

And in the file "BIOS_c6xdsp.cfg" have the following code:

So I write my code in the file "vaLink_alg.c" as follow:

However, when I make the program, have errors as follow:

What should I do if I want to use the L2RAM of DSP?

Thank you.

Tianxing

11 Replies

  • DSP L2 RAM of 128K is fully used by the BIOS internal heap. If you want to place your own array into L2RAM you will have to reduce the size of the BIOS internal heap.

    Modify FC_RMAN_IRES_c6xdsp.cfg

    heapMemParams.size              = 0x00020000;

    to

    heapMemParams.size              = 0x00020000 - 512;/* Reduce size of heap by size of your array */

  • In reply to Badri Narayanan:

    Hi,

    Thank you for your reply.

    What's the mean of "BIOS internal heap"? Could I  allocate a memory from it using the Memory_alloc()?

    And I have another question about the L2Cache.

    What should I do if I want to set the L2 as a 128K RAM and 128K Cache, and set the DDR as cacheable?

    Thank you.

    Tianxing

  • In reply to tianxing hou:

    Could I  allocate a memory from it using the Memory_alloc()?

    - Yes you can allocate memory using Memory_alloc. The heapHandle is called DSP_HEAPINT_MEM.You can allocate memory as shown below:

      extern const ti_sysbios_heaps_HeapMem_Handle DSP_HEAPINT_MEM;

       Memory_alloc(DSP_HEAPINT_MEM,...)

    What should I do if I want to set the L2 as a 128K RAM and 128K Cache

     - This is already the default configuration. L2 cache size can be set in config_512M.bld as l2Mode:  "128k" --> This indicates cache size is 128k and remaining 128K is SRAM.

    To set the DDR as cacheable

      - Set the MAR bits FC_RMAN_IRES_c6xdsp.cfg.(This is already done).Pls refer sysbios/packages/ti/sysbios/family/c64p/Cache.xdc for documentation on MAR bits.

  • In reply to Badri Narayanan:

    Hi,

    Thanks for your reply.

    I have some questions:

    1, Could I modify the configuration of L2 dynamic, or re-configure the L2 by modify the config_512M.bld?

    2, Could I modify the DDR cacheable dynamic, or re-configure it by modify the FC_RMAN_IRES_c6xdsp?

    3, I want to know have any LIB to support the C674x DSP of DM8127, for example, the IMGLIB, VLIB, IQMATH and the Fast RTS for the C64x/C64x+ Device. Since I know the C674x CPU combines support of the C64x+ DSP and C67x+ DSP instruction sets.

    4, I used the fixed point DSP before. The C674x DSP is a fixed/floating point CPU, are there some advantages than the fixed point DSP. What should I care when I use it to accelerate the performance of DSP. I run a simplified alg in the C674x DSP of DM8127, it consume 67ms. When I use the DM648, it consume 19.6ms. And the freq of  C674x DSP is 500MHz, the DM648 is 1.1GHz. 

  • In reply to Badri Narayanan:

    Hi,

    Today, I try run a function of Imglib3.1.1 for the C64x+ DSP on the C674x DSP of DM8127, and run the same function of Imglib2.2 for the C64x+ on the DM648.

    I find the function consume 6ms on the DM8127, however it only consume 0.3ms on the DM648.

    I get the consume time by using the Utils_getCurTimeInMsec() on the DM8127, and get the time by using the CLK_gethtime() on the DM648.

    I can't understand the performance differences between the two dsp platform.

    The resolution of image is 320*240, and I call the function is IMG_thr_le2min_8().

    Could you give me some suggestions?

    Thank you.

  • In reply to tianxing hou:

    1, Could I modify the configuration of L2 dynamic, or re-configure the L2 by modify the config_512M.bld?

      - It is possible to configure L2 dynamically but in RDK it is done at build time. Runtime change should be done carefully as there are a number of things that need to be taken care when changing L2 configuration.Pls refer sysbios docuemntation for Cache_setSize API

    2, Could I modify the DDR cacheable dynamic, or re-configure it by modify the FC_RMAN_IRES_c6xdsp?

     - It is possible to configure DDR caching dynamically. Pls refer sysbios docuemntation for Cache_setMar API.

    For question 3 and 4 you could post in c67 forum where you would get correct response:

    http://e2e.ti.com/support/dsp/tms320c6000_high_performance_dsps/f/115.aspx

  • In reply to Badri Narayanan:

    Thanks a lot for your reply.

    I have a question about the Utils_getCurTimeInMsec(), it get the current time in milliseconds?

  • In reply to Badri Narayanan:

    Hi, 

    I have another question about the using of EDMA.

    I find the interface of EDMA in the IPNC code: DM81XX_EDMA3_setParams and DM81XX_EDMA3_triggerTransfer.

    And I find they are used in the VaLink_algCopyFrames() of vaLink_alg.c.

    However, when I transplant the EDMA interface to the VaLink_algProcessFrames(), it can't execute succeed. It will halted in the code as follow:

    do
    {
           data = *((volatile unsigned int *) DM81XX_EDMA3_IPR);

    } while ((data & (1 << chId)) == 0);

    And I call the interface as follow:

    DM81XX_EDMA3_setParams(VA_LINK_EDMA3_CH_ID,                       // chId
                                                           VA_LINK_EDMA3_QUEUE_ID,               // dmaQueue
                                                          (UInt32)pFullFrame->addr[0][0],              // srcAddr
                                                          (UInt32)pui8YOut,                                       // dstAddr
                                                          inImage.width,                                             // edmaWidth
                                                          inImage.height,                                           // edmaHeight
                                                          inImage.width,                                             // srcLineOffset
                                                          inImage.width);                                            // dstLineOffset


    /* Trigger the edma transfer */
    DM81XX_EDMA3_triggerTransfer(VA_LINK_EDMA3_CH_ID);

    I allocate the pui8YOut using the  pui8YOut     = Utils_memAlloc(320*240, 8);

    I want to know how using the interface of EDMA.

  • In reply to tianxing hou:

    Hi,

    I dont see why the transfer would fail or halt unless a transfer on the same channel is in progress while we triggered another transfer.