I believe I have found a mistake in the MAR register settings for the DSP core of the DM8127 in IPNC RDK Release 2.8.
Here is a partial listing of the file "ipnc_rdk/ipnc_mcfw/mcfw/src_bios6/cfg/ti814x/FC_RMAN_IRES_c6xdsp.cfg". I have added the comments which show the memory address ranges associated with each MAR register.
/* Disable caching for HWspinlock addresses */Cache.MAR0_31 = 0x00000000; /* 0x00000000 - 0x1FFFFFFF --> NOT CACHEABLE */Cache.MAR32_63 = 0x00000000; /* 0x20000000 - 0x3FFFFFFF --> NOT CACHEABLE *//* Config/EDMA registers cache disabled */Cache.MAR64_95 = 0x00000000; /* 0x40000000 - 0x5FFFFFFF --> NOT CACHEABLE */Cache.MAR96_127 = 0x00000000; /* 0x60000000 - 0x7FFFFFFF --> NOT CACHEABLE *//* cache settings for 1st 512MB DDR */Cache.MAR128_159 = 0x0000FF00; /* 0x80000000 - 0x87FFFFFF --> NOT CACHEABLE */ /* 0x88000000 - 0x8FFFFFFF --> CACHEABLE */ /* 0x90000000 - 0x9FFFFFFF --> NOT CACHEABLE *//* cache settings for 2nd 512MB DDR */Cache.MAR160_191 = 0x0FFF0000; /* 0xA0000000 - 0xAFFFFFFF --> NOT CACHEABLE */ /* 0xB0000000 - 0xBBFFFFFF --> CACHEABLE */ /* 0xBC000000 - 0xBFFFFFFF --> NOT CACHEABLE *//* cache settings for 3rd 512MB DDR */Cache.MAR192_223 = 0x00000000; /* 0xC0000000 - 0xDFFFFFFF --> NOT CACHEABLE *//* cache settings for 4th 512MB DDR */Cache.MAR224_255 = 0x00000000; /* 0xE0000000 - 0xFFFFFFFF --> NOT CACHEABLE */
I believe the setting for Cache.MAR160_191 is incorrect. It makes the entire 128 MB of TILER Space cacheable which is OK. But it also makes 64 MB (out of 105 MB total) of the SR2 SysLink Shared Frame Buffer area cacheable. I believe the SR2 memory area should not be cacheable and that the correct setting for Cache.MAR160_191 should look like this:
/* cache settings for 2nd 512MB DDR */Cache.MAR160_191 = 0x00FF0000; /* 0xA0000000 - 0xAFFFFFFF --> NOT CACHEABLE */ /* 0xB0000000 - 0xB7FFFFFF --> CACHEABLE */ /* 0xB8000000 - 0xBFFFFFFF --> NOT CACHEABLE */
I have already made this correction in my own codebase.
This bug is still present (has not been fixed) in DM8127 GA Release 3.0.0. I believe it could cause subtle "difficult to debug" errors for unsuspecting users.
Would someone from TI or Appro please comment?
P.S. - There are also multiple documentation errors in the Memory Map Details section of "The Multi Channel Framework Software User Guide" (Document Revision 1.10, pages 27 and 28). The "Start Address" for 3 of the last 4 memory areas are incorrect.
The MAR160_191 settings needs corrections as you pointed out. Sorry, we missed taking care of it in GA3.0 release. We shall take care of it in our next release.
We shall also update the 'Start address' of memory map section in user guide.
Appreciate you bringing these errors to our notice .
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