ti8148 audio clock

hi Lihou,

Do you want to set the DPLL_AUDIO input clock (audio_dpll_clkin_ck) to be sourced from the AUXOSC clock input (osc1_clkin_ck)? 

Best regards,

Pavel

hi Lihou,

In case this is what you want, one possible solution is to update the ti814x_clk_init(void) function as follows:

int __init ti814x_clk_init(void)

{ 

struct omap_clk *c;
u32 cpu_clkflg = CK_TI814X;

   struct clk *clkp;
   struct clk *new_parent;

............

clk_enable_init_clocks();

    clkp = clk_get(NULL,"audio_dpll_clkin_ck");
    if(!clkp) printk("audio_dpll_clkin_ck clk_get failed\n");
    else printk("audio_dpll_clkin_ck clk_get successed.\n");

    new_parent = clk_get(NULL,"osc1_clkin_ck");
    if(!new_parent) printk("osc1_clkin_ck clk_get failed\n");
    else printk("osc1_clkin_ck clk_get successed.\n");

   clk_set_parent(clkp, new_parent);

  return 0;

}

Thus successfully change the parent clock from osc0_clkin_ck (DEVOSC) to osc1_clkin_ck (AUXOSC). Now reading bit OSC_SRC[24] AUDIO_PLL_SOURCE is 0x1 (AUXOSC), previously 0x0 (DEVOSC).

Best regards,

Pavel

hi pavel,

  thank you very much!

  i add you code on my project, and have get the correct bit value (OSC_SRC[24] is 1) after reading register TI814X_PLL_CMGC_OSC_SRC.

  and i have another issue. audio MCLK is provide from externel crystal source on my dm814x evm. i want to set MCLK is generated  internally, and set MCLK output 24576000 Hz to audio codec chip tlv320aic3x. (my AUXOSC input frequency is 2457600 Hz).

 how to modify the dm814x code?

Hi Lihou,

I have checked the Clock Framework. The audio MCLK that you are interested can be two clock signals:

1. The clock input to the McASP2 module (aux_clk). This clock signal (aux_clk) is coming from the device PRCM.

2. The clock output from the McASP2 module (ACLKX). This clock is input to the TLV320AIC3X audio codec.

Could you please tell in which case your audio MCLK question is? I mean do you ask about the clock input to the McASP2 or to the clock output of the McASP2?

Best regards,

Pavel

hi pavel,

  tks~

  yes, i want ACLKX output to the TLV320AIC3X audio codec. the frequency of the ACLKX signal is 24576000Hz.

Hi Lihou,

Please read section 16.2.2.1 Transmit Clock, from the DM814x TRM. You will find there that ACLKX can be internally generated by programming bit ACLKXCTL[5] CLKXM = 1.

Also all the way from the aux_clk to the ACLKX through the dividers is described also, you can adjust the frequency desired.

Best Regards,

Pavel

hi pavel,

  i try to set ACLKXCTL[5] CLKXM = 1 in code. but found AHCLKX output 20000000 Hz but not 24576000 Hz on board. and then i find AUX_CLK is come form SYSCLK22 but not

 SYSCLK20.

 i try to set AUX_CLK to be SYSCLK20, but has no effect. how i set the AUX_CLK come form SYSCLK20?

  the code as follow:

 // mcasp3_fck from sysclk20_ck
 clkp = clk_get(NULL, "mcasp3_fck");
 if(!clkp)
  printk("mcasp3_fck clk_get failed\n");
 else
  printk("mcasp3_fck clk_get successed.\n");

 new_parent = clk_get(NULL, "sysclk20_ck");
 if(!new_parent)
  printk("sysclk20_ck clk_get failed\n");
 else
  printk("sysclk20_ck clk_get successed.\n");

 clk_set_parent(clkp, new_parent);

Hi Lihou,

I also can not set in linux, the parent clock to be sysclk20. I am still investigating this.

Meanwhile, I found a workaround in u-boot, file ti-ezsdk_xxx/board-support/u-boot-xxx/board/ti/ti8148/evm.c

/*
     * McASP2
     * select mcasp2 clk from sys_clk_22 (OSC 0)
     * so that audio clk (sys_clk_20) can be used for RMII
     * ToDo :
     * This can be removed once kernel exports set_parent()
     */
    //__raw_writel(0x2, CM_AUDIOCLK_MCASP2_CLKSEL);
    //while (__raw_readl(CM_AUDIOCLK_MCASP2_CLKSEL) != 0x2);

When I comment the above two lines of code, the parent clock of mcasp3_fck is sysclk20. I am not sure if this is the most appropriate fix, so I continue with the investigation.

Could you please try if this fix will work for you?

BR

Pavel

Hi Pavel,

I met the same situation.After changing DEVOSC to AUXOSC,OSC_SRC[24] is 0x1,but AHCLKX output is 20MHz.I want to set the output is 24.576MHz.

Would you please give me some suggestions?

BR

Bob

Bob,

Do you need to set the McASP2 AHCLKX (transmit high-frequency master clock) to 24.576MHz?

Regards,
Pavel

Hi Pavel,

Yes,I do.

BR

Bob

Bob,

Do you need to set the input AHCLKX clock of the McASP2 to 24.576MHz? This AHCLKX_IN can be sourced from the AUD_CLKIN0/1/2, AUXOSC_XI, ATCLK0/1/2/3 pins.

Or you need to set the output AHCLKX clock of the McASP2 to 24.576MHz? This AHCLK_OUT is based on the McASP2 functional clock (AUX_CLK).

Regards,
Pavel

Hi Pavel,

I want to set the output AHCLKX clock to 24.576MHz,but don't know how to set?

Would you tell me how to set ?Thank you.

BR

Bob

Bob,

What is the frequency of the McASP2 aux_clk (mcasp3_fck) at your side?

Refer to DM814x TRM, section 16.2.2.1 Transmit Clock. The AHCLKX_OUT is based on the aux_clk and internal divider (AHLKXCTL[11-0] HCLKXDIV)

Regards,
Pavel

Hi Pavel,

Sorry,I don't know how to get the frequency of McASP2 aux_clk ,could you tell me how to do ?

I have set the clock source from OSC1,but don't know how to get auxclk from sysclk20.

Need your help.

BR

Bob

Hi Pavel,

Do you have some good suggestions?

BR

Bob

Bob,

bob lee said:

Sorry,I don't know how to get the frequency of McASP2 aux_clk ,could you tell me how to do ?

You should use the TI81xx clock framework:

http://processors.wiki.ti.com/index.php/TI81XX_PSP_PM_CLOCK_FRAMEWORK_User_Guide

By default, the mcasp3_fck (McASP2 aux_clk) is derived from sysclk22_ck and is 20MHz. See below how I find this:

Arago Project http://arago-project.org dm814x-evm ttyO0

Arago 2011.09 dm814x-evm ttyO0

dm814x-evm login: root
root@dm814x-evm:~# mount -t debugfs debugfs /sys/kernel/debug
root@dm814x-evm:~# cd /sys/kernel/debug/clock
root@dm814x-evm:/sys/kernel/debug/clock# ls -lR | grep mcasp3_fck
drwxr-xr-x    2 root     root            0 Jan  1  1970 mcasp3_fck
./osc0_clkin_ck/sysclk22_ck/mcasp3_fck:
root@dm814x-evm:/sys/kernel/debug/clock# cd osc0_clkin_ck/sysclk22_ck/mcasp3_fck/
root@dm814x-evm:/sys/kernel/debug/clock/osc0_clkin_ck/sysclk22_ck/mcasp3_fck# cat rate
20000000


So, what is your mcasp3_fck clock path, and what is the frequency?

Regards,
Pavel

Hi Pavel,

It's mine.

root@dm814x-evm:/sys/kernel/debug/clock/osc0_clkin_ck/sysclk22_ck/mcasp3_fck# ls
flags     rate      usecount
root@dm814x-evm:/sys/kernel/debug/clock/osc0_clkin_ck/sysclk22_ck/mcasp3_fck# ca
t rate
20000000
root@dm814x-evm:/sys/kernel/debug/clock/osc0_clkin_ck/sysclk22_ck/mcasp3_fck#

That is to say, if I want the clock 24.576MHz, I need to set the sysclk22_ck to 24.576MHz.Is it right?

If so ,how to set ?

BR

Bob

Bob,

bob lee said:

That is to say, if I want the clock 24.576MHz, I need to set the sysclk22_ck to 24.576MHz.Is it right?

You can not set sysclk22_ck to value different from 20MHz, unless you change the main device oscillator (DEVOSC), which is 20MHz on the DM814x EVM. The sysclk22_ck clock tree is:

osc0_clkin_ck -> sysclk22_ck

This clock tree can not be changed. osc0_clkin_ck is 20MHz, this is DEVOSC.

The mcasp3_fck can be also sourced from sysclk21_ck and sysclk20_ck. You can try with these clocks. This is controlled in the CM_AUDIOCLK_MCASP2_CLKSEL register.

Regards,
Pavel

Hi Pavel,

I have found the register CM_AUDIOCLK_MCASP2_CLKSEL in TRM and struct mcasp3_fck.

Would tell me how to set ? Many thanks .

/* Mcasp2 aux_clk out (PRCM out) */
static struct clk mcasp3_fck = {
 .name  = "mcasp3_fck",
 .init  = &omap2_init_clksel_parent,
 .clksel  = audio_prcm_mux_sel,
 .ops  = &clkops_ti81xx_dflt_wait,
 .enable_reg = TI81XX_CM_ALWON_MCASP2_CLKCTRL,
 .enable_bit = TI81XX_MODULEMODE_SWCTRL,
 .clksel_reg = TI81XX_CM_DPLL_AUDIOCLK_MCASP2_CLKSEL,
 .clksel_mask = TI81XX_CLKSEL_0_1_MASK,
 .clkdm_name = "alwon_l3_slow_clkdm",
 .recalc  = &omap2_clksel_recalc,
 .set_rate       = &ti814x_clksel_set_rate,
};

BR

Bob

Bob,

One easy way to change the McASP2 source clock from sysclk22 to sysclk20 or sysclk21 is from u-boot. See the below post:

http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/716/p/197142/711664.aspx#711664

Regards,
Pavel

Hi Pavel,

Could we change it in kernel code ?

BR

Bob

Bob,

You can change the value of CM_AUDIOCLK_MCASP2_CLKSEL[1:0] CLKSEL to 0x0 (sysclk20) in linux kernel code with with direct writing in the  CM_AUDIOCLK_MCASP2_CLKSEL register, but when the kernel boot up, mcasp3_fck is still sourced from sysclk22_ck (not from sysclk20_ck).


Other working solution, beside modifying the u-boot source code (evm.c) is to modify u-boot with the mw command:

TI8148_EVM#mw 0x48180384 0x0

After this command, you can continue with loading the linux kernel and rootfs.

Regards,
Pavel

Bob,

Other thing we can try is to make direct write in the linux kernel. Although the clock framework reports that mcasp3_fck is sourced from sysclk22_ck, I suspect it might be sysclk20_ck instead.

You can modify linux-2.6.37-psp04.04.00.01/arch/arm/mach-omap2/clock814x_data.c

int __init ti814x_clk_init(void)
{
    struct omap_clk *c;
    u32 cpu_clkflg = CK_TI814X;

   static void __iomem *base;

...............

   clk_enable_init_clocks();

   base = ioremap(0x48180384, SZ_4K);    

    __raw_writel(0x0, base);
    
    return 0;
}

Then build and load the new uImage. Then you can measure the McASP2 AHCLKX pin, this time the value should be different than the default 20MHz value.

Regards,
Pavel

Hi Pavel,

I have added the code you gave me to the linux kernel,but the output of MaASP2 ACLKX is about 300MHz which is not I want .

According to the electric schematic diagram,the clock source is from Y2.

Hi Pavel,

I have added the code you gave me to the linux kernel.But the output of ACLKX is 300MHz.

On our board ,the clock source is 24.576 from Y2.

On EVM board , the clock source is 22.579 from Y6/Y7.

The clock sources are not same.Do it matter?

Hi Pavel,

Could we change the input value of AUXOSC?For example,change the value to 24.576MHz by configuring some registers.

BR

Bob

Hi Pavel,

I don't find something is wrong.Need your great help .

Thank you.

BR

Bob

Bob,

bob lee said:

I have added the code you gave me to the linux kernel.But the output of ACLKX is 300MHz.

What about the AHCLKX_OUT clock frequency? You stated that this clock frequency was 20MHz:

http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/716/p/197142/1321247.aspx#1321247

And from what I understand this is the clock you need to adjust, not ACLKX? What is the frequency on the AHCLKX_OUT pin now?

Regards,
Pavel

Hi Pavel,

Sorry, maybe I posted your the wrong message.

I got below infor.

root@dm814x-evm:/sys/kernel/debug/clock/osc1_clkin_ck/audio_dpll_clkin_ck/audio_dpll_ck/sysclk20_ck/mcasp2_fck# ls
flags     rate      usecount
root@dm814x-evm:/sys/kernel/debug/clock/osc1_clkin_ck/audio_dpll_clkin_ck/audio_dpll_ck/sysclk20_ck/mcasp2_fck# cat rate
282237500
root@dm814x-evm:/sys/kernel/debug/clock/osc1_clkin_ck/audio_dpll_clkin_ck/audio_dpll_ck/sysclk20_ck/mcasp2_fck#

Hi Pavel,

I got the frequency(300MHz) of MCA[2]_ACLKX by using oscilloscope.

I don't know how to get the frequency of AHCLKX.

Would you tell me how to operate ?

Thank you .

BR

Bob

Hi Pavel,

The both values of HCLKXDIV and CLKXDIV are 0x0.So I think the frequency of AHCLKX and ACLKX are the same .

Is it right ?

BR

Bob

Bob,

bob lee said:

root@dm814x-evm:/sys/kernel/debug/clock/osc1_clkin_ck/audio_dpll_clkin_ck/audio_dpll_ck/sysclk20_ck/mcasp2_fck

bob lee said:

root@dm814x-evm:/sys/kernel/debug/clock/osc1_clkin_ck/audio_dpll_clkin_ck/audio_dpll_ck/sysclk20_ck/mcasp2_fck

bob lee said:

root@dm814x-evm:/sys/kernel/debug/clock/osc1_clkin_ck/audio_dpll_clkin_ck/audio_dpll_ck/sysclk20_ck/mcasp2_fck

The DM814x TRM and datasheet has the below numbering:

McASP0, McASP1, McASP2, McASP3, McASP4 and McASP5

While in the linux kernel code, the numbering is:

McASP1, McASP2, McASP3, McASP4, McASP5 and McASP6

Could you please tell which McASP you need to set to 24.576MHz, McASP1 (stated as mcasp2 in linux kernel) or McASP2 (stated as mcasp3 in linux kernel)?

Until now, I though you need to set McASP2 (mcasp3 in linux kernel), as McASP2 is connected to the AIC3106 audio codec on the DM814x EVM. But from your last post it seems you need to set McASP1 (mcasp2 in linux kernel)?

The based address of McASP1 (mcasp2 in linux kernel) is 0x46400000 (data port) and 0x4803C000 (config port).

The based address of McASP2 (mcasp3 in linux kernel) is 0x46800000 (data port) and 0x48050000 (config port).

Regards,
Pavel

Hi Pavel,

Sorry for not giving you the detailed message.

I want to set McASP2 to get the clock from CPU.

According to the TRM,I have select AUXSOC as the clock source.Please refer the red line in the below picture.

The input clock (AUXSOC) is 24.576MHz, and I want the output clock(MCASP2 aux_clk) also is 24.575MHz.But the aux_clk is not right.

So I think the problem is DPLL_AUDIO and Would you tell me how to set the DPLL_AUDIO registers to keep the clock all the same without changing.

Thank you .

BR

Bob

Bob,

bob lee said:

AHCLKX output is 20MHz.I want to set the output is 24.576MHz.

Are you measuring the 20MHz output from MCA[2]_AHCLKX signal, on H1 physical pin, with the scope?

PINCNTL16/0x4814083C  [7:0] MUXMODE = 0x4?


Regards,
Pavel

Bob,

bob lee said:

I have added the code you gave me to the linux kernel,but the output of MaASP2 ACLKX is about 300MHz which is not I want .

Do you mean that you have 300MHz on the MCA[2]_ACLKX signal, physical pin U6? What frequency you want to get on this pin?


Do you have PINCNTL39/0x48140898 [7:0] MUXMODE = 0x1?

Regards,
Pavel

Hi Pavel,

I measure the U6 PIN.Before  changing  the McASP2 source clock from sysclk22 to sysclk20,the value is 20MHz.

After changing  the McASP2 source clock from sysclk22 to sysclk20,the value is 300MHz.

root@dm814x-evm:/media/mmcblk0p1# devmem2 0x4814083C
/dev/mem opened.
Memory mapped at address 0x40269000.
Read at address  0x4814083C (0x4026983c): 0x00040001
root@dm814x-evm:/media/mmcblk0p1#

BR

Bob

Hi Pavel,

Yes ,you are right . I want the frequency is 24.576MHz or 2.048MHz.

root@dm814x-evm:/media/mmcblk0p1# devmem2 0x48140898
/dev/mem opened.
Memory mapped at address 0x40332000.
Read at address  0x48140898 (0x40332898): 0x00060001
root@dm814x-evm:/media/mmcblk0p1#

BR

Bob

Bob,

bob lee said:

So I think the problem is DPLL_AUDIO and Would you tell me how to set the DPLL_AUDIO registers to keep the clock all the same without changing.

From what I understand, you need to below clock path:

AUXOSC -> DPLL_AUDIO -> sysclk20 -> McASP2 aux_clk

And AUXOSC in DM814x EVM is 22579000 Hz, while in your custom board is 24576000 Hz.

The first steps is to switch from DEVOSC (20MHz) to AUXOSC (22.579MHz on EVM, 24.576MHz on your custom board). From what I understand you know how to do this.

The second step is to disable the DPLL_AUDIO, thus AUXOSC frequency will not be multiplied and stay the same. This can be done in u-boot:

ti-ezsdk_dm814x-evm_5_05_02_00/board-support/u-boot-2010.06-psp04.04.00.01/board/ti/ti8148/evm.c

void prcm_init(u32 in_ddr)
{
    /* Enable the control module */
    __raw_writel(0x2, CM_ALWON_CONTROL_CLKCTRL);

#ifdef CONFIG_SETUP_PLL
    /* Setup the various plls */
    //audio_pll_config();   -----------> comment the audio pll config
    sata_pll_config();
#if 0
    pcie_pll_config();
#endif

The third step is to switch from sysclk22 to sysclk20. We already discuss how this can be done.

Finally you should end up with AUXOSC frequency provided to McASP2 aux_clk (mcasp3_fck in linux kernel).

Regards,
Pavel

Hi Pavel.

Your understand are right.Sorry for confusing you.

I have programmed the uboot to the nand flash. And we use tftp tool to download the uImage and ramdisk.gz to the DRAM to run the linux.So I think if we can reconfigure or disable the DPLL_AUDIO in linux code ,it will be good.

Is there any way to do this?

BR

Bob

Bob,

bob lee said:

I have programmed the uboot to the nand flash. And we use tftp tool to download the uImage and ramdisk.gz to the DRAM to run the linux.So I think if we can reconfigure or disable the DPLL_AUDIO in linux code ,it will be good.

Is there any way to do this?

One possible solution could be to load the u-boot from the NAND flash, then change the DPLL_AUDIO from the u-boot prompt, then continue with booting the kernel and filesystem.

The DPLL_AUDIO can be put in bypass mode through AUDIOPLL_CLKCTRL/0x481C5234 register, bit [23] IDLE = 1

TI8148_EVM#mw 0x481C5234 0x08910811

Thus the DPLL_AUDIO is put to IDLE bypass mode (from active and locked mode), and the clock in the input is not multiplied, but just bypassed to the output with no change of the frequency.

Does this work for you?

BR
Pavel

Hi Pavel,

Yes,it works.

Can we set the value of AUDIOPLL_CLKCTRL/0x481C5234 in linux kernel directly?

BR

Bob

Bob,

bob lee said:

Can we set the value of AUDIOPLL_CLKCTRL/0x481C5234 in linux kernel directly?

Yes, this should be possible. Please try:

 linux-2.6.37-psp04.04.00.01/arch/arm/mach-omap2/clock814x_data.c

int __init ti814x_clk_init(void)
{
    struct omap_clk *c;
    u32 cpu_clkflg = CK_TI814X;

   static void __iomem *base;

...............

   clk_enable_init_clocks();

   base = ioremap(0x481C5234, SZ_4K);    

    __raw_writel(0x08910811, base);
    
    return 0;
}

BR
Pavel

Hi Pavel,

Thank you very much.It is ok now.

Have a nice weekend.

BR

Bob

Hi Bob,

Glad to know you are making progress. Let me know if you have more questions on this subject.

Regards,
Pavel

Hi Pavel,

As we know the ACLKX & AHCLKX are ok last week,I am working with the frame clock now.

Now the frame clock is 64kHz,but I want to set the frame clock to 8kHz.

Do I need to configure the AFSXCTL register ? And how to do ?

BR

Bob

Bob,

bob lee said:

As we know the ACLKX & AHCLKX are ok last week

Does this mean that McASP2 AHCLKX (MCA[2]_AHCLKX pin set as output) is 24.576MHz?

And what is McASP2 ACLKX (MCA[2]_ACLKX pin set as output) frequency?

And what is McASP2 aux_clk, is it 24.576MHz?

bob lee said:

I am working with the frame clock now.

Do you mean McASP2 AFSX (MCA[2]_AFSX pin set as output) signal?

bob lee said:

Now the frame clock is 64kHz,but I want to set the frame clock to 8kHz.

Do you mean that you have 64KHz on the MCA[2]_AFSX pin (set as output) and you want 8KHz on it?

BR
Pavel

Hi Pavel,

The frequency of  aux_clk and McASP2 AHCLKX  are both 24.576MHz.

And I set the frequency of  ACLKX to 2.048MHz.

Do you mean that you have 64KHz on the MCA[2]_AFSX pin (set as output) and you want 8KHz on it?

Yes ,you are right . I want to set the frequency of McASP2 AFSX to 8kHz.

BR

Bob

Bob,

bob lee said:

The frequency of  aux_clk and McASP2 AHCLKX  are both 24.576MHz.

So you have McASP2 AHCLKXCTL[11:0] HCLKXDIC = 0x0 (divide by 1)?

bob lee said:

And I set the frequency of  ACLKX to 2.048MHz.

So you have McASP2 ACLKXCTL[4:0] CLKXDIV = 0xB (divide by 12)?

bob lee said:

I want to set the frequency of McASP2 AFSX to 8kHz.

Is your AFSX based on the XCLK (McASP2.AHCLKXCTL[15] HCLKXM =1; McASP2.ACLKXCTL[5] CLKXM=1) ?

Regards,
Pavel

Hi Pavel,

So you have McASP2 AHCLKXCTL[11:0] HCLKXDIC = 0x0 (divide by 1)?

Yes,you are right.

So you have McASP2 ACLKXCTL[4:0] CLKXDIV = 0xB (divide by 12)?

Yes.you are right.

Is your AFSX based on the XCLK (McASP2.AHCLKXCTL[15] HCLKXM =1; McASP2.ACLKXCTL[5] CLKXM=1) ?

Yes.AFSX is based on the XCLK.

BR

Bob