Hello,
This thread has been specialized from an other.
To sum up facts, following init could be performed under Image (VPSS) M3 core:
*((unsigned int*)0x48180d00) = 0x2;
*((unsigned int*)0x48180d10) = 0x3;
*((unsigned int*)0x48180700) = 0x2;
*((unsigned int*)0x48180720) = 0x2;
*((unsigned int*)0x48180724) = 0x2;
*((unsigned int*)0x55050010) = 0x23; // ISP5_SYSCONFIG
// ISP5_SYSCONFIG had been readable until write so that following further steps are required:
*((unsigned int*)0x55040080) = 0xFFFF0000; // ISS_CTRL
*((unsigned int*)0x55040084) = 0xF0000002; // ISS_CLKCTRL
// at this point it seems that ISS registers are fully accessible from the M3
Based on Rajat's answer: M3 accesses go via MMU, but for A8 the accesses don't go via the MMU. So I should read/write ISS registers from A8 by directly mapping the physical to virtual address.
From the A8, I kept trying with something like this:
fd = open("/dev/mem", O_RDWR | O_SYNC);
page_addr = (unsigned char *) mmap( 0, getpagesize(), PROT_READ | PROT_WRITE, MAP_SHARED, fd, 0x5505000 );
offset = (unsigned int *)(page_addr + 0x10);
// I get no errors until here.
printf("%x\n",*offset);
// Here a bus error comes.
What could I do wrong?
Linux is configured almost as in IPNC DM8148 RDK except for the vpss notify area. It is missing from bootargs in order to run msgQ sample.
Regards
Krisztián