discrete sync issue in 8148

Chuan-Hsiu Lee

Intellectual 590 points

Hi,

We used discrete sync (DE + VBLK) in our system.

Our SW is DVR RDK3.5.

Our HW is "SDI-->FPGA-->DM8148(PG3.0)".

Sometimes, we will lose video frame(CH000), but vbi frame(CH010) is correct.

No frames are dropped by capture link.

Does any comment for this issue?

Or any limitations for discrete sync?

[m3vpss ] | Total Even Odd Total Even Odd Min / Max Min / Max Dropped Fid Repeat Frame Error Y/C

[m3vpss ] CH | Fields Fields Fields FPS FPS FPS Width Height Fields Count (Desc Error Y/C)

[m3vpss ] ------------------------------------------------------------------------------------------------------------

[m3vpss ] 000 | 243334 243334 0 58 58 0 1280 / 1280 720 / 720 1 0 0/0 (0/0)

[m3vpss ] 010 | 250956 250956 0 59 59 0 1280 / 1280 30 / 30 1 0 0/0 (0/0)

over 10 years ago

0 Brijesh Jadav over 10 years ago

TI__Guru**** 399000 points

Hi,

Do you mean less number of frames captured on ch000?

As such, there is no limitation fro discrete sync capture, the same number of frame could have been captured for the ch000 also. Can you check if you are seeing any overflow during this run? are the input sources for the ch000 and ch010 same?

Regards,

Brijesh

0 Chuan-Hsiu Lee over 10 years ago in reply to Brijesh Jadav

Intellectual 590 points

Hi Brijesh:

CH000 is active video.

CH010 is vertical blanking interval .

1. I think these number of two channels should be the same.

2. No VIP Overflow .

On embedded sync, I cannot see this issue is occurred.

Any IP/component will effect HDVPSS driver?

for example, CPU(A8/M3) usage? DDR bandwidth? L2?

Regards,

CH Lee

0 Troy huang over 10 years ago in reply to Chuan-Hsiu Lee

Prodigy 110 points

Dear Brijesh;

I am working with Chuan-Hsiu.

I want to describe the issue more.

When we found the phenomenon, we check the M3 information like as below.

[m3vpss ] | Total Even Odd Total Even Odd Min / Max Min / Max Dropped Fid Repeat Frame Error Y/C

[m3vpss ] CH | Fields Fields Fields FPS FPS FPS Width Height Fields Count (Desc Error Y/C)

[m3vpss ] ------------------------------------------------------------------------------------------------------------

[m3vpss ] 000 | 243334 243334 0 58 58 0 1280 / 1280 720 / 720 1 0 0/0 (0/0)

[m3vpss ] 010 | 250956 250956 0 59 59 0 1280 / 1280 30 / 30 1 0 0/0 (0/0)

The CH000(video frame, video format is 720p) frame is less than CH010(VBI).

After 10min, the CH000(video frame) total field is 243334(the same) but the CH010(VBI) total field is added(more than 250956).

I also proble FPGA discrete signal(V_sync,de). The signal is also “normal toggle”. I can find de pin signal is high/low toggle when v_sync signal is “low”(it mean video total field should not keep the constant.

B.R.

Troy Huang

0 hb chen over 10 years ago in reply to Troy huang

Expert 2640 points

Dear Brijesh,

I provide more information.

We are testing two case. One is Discrete Sync. The other one is Embedded Sync.

Each case has different problem. But we hope we can use discrete sync mode.

The problems that we met described as below:

---

1) Discrete Sync mode:

CH010 is vertical blanking interval. CH000 is active video. Sometimes, we will lose video frame(CH000), no anymore video frame will be captured by CaptureLink, but VBI frame(CH010) is correct. No VIP Overflow occurs.

---

2) Embedded Sync mode:

"Overflow detected on VIP0" sometimes happens:

[m3vpss ] 52696659: CAPTURE: Overflow detected on VIP0, Total Resets = 33

[m3vpss ] VIP Parser Reset Count : 33
[m3vpss ]
[m3vpss ]      |   Total    Even     Odd Total Even   Odd Min / Max Min / Max Dropped Fid Repeat Frame Error Y/C
[m3vpss ] CH | Fields Fields Fields    FPS   FPS   FPS       Width      Height Fields      Count (Desc Error Y/C)
[m3vpss ] ------------------------------------------------------------------------------------------------------------
[m3vpss ] 000 | 3159901       1 3159900     59     0    59 1280 / 1280 720 / 720      34          0 0/0 (0/0)
[m3vpss ] 010 | 3159935       1 3159934     59     0    59 1280 / 1280   30 /   30      34          0 0/0 (0/0)

---

The code difference between two case is:

dvr_rdk\mcfw\src_bios6\links_m3vpss\capture\captureLink_drv.c::CaptureLink_drvCreateInst

#if FOR_EMBEDDED_SYNC
pVipCreateArgs->videoCaptureMode = VPS_CAPT_VIDEO_CAPTURE_MODE_SINGLE_CH_NON_MUX_EMBEDDED_SYNC;
#else // FOR DISCRETE_SYNC
pVipCreateArgs->videoCaptureMode =
VPS_CAPT_VIDEO_CAPTURE_MODE_SINGLE_CH_NON_MUX_DISCRETE_SYNC_ACTVID_VBLK;
#endif

Two cases are under same environment. Same testing problem. But different problems occurred.

A8 CPU usage is 100%.

[m3vpss ] 51708176: LOAD: CPU: 33.2% HWI: 3.2%, SWI:2.7%

[m3video] 51708689: LOAD: CPU: 17.3% HWI: 1.2%, SWI:1.9%

[c6xdsp ] 51634449: LOAD: CPU: 18.2% HWI: 0.5%, SWI:0.4%

Two cases are both unacceptable.

Plz help clarify it and how to solve it.

thx ~

0 Brijesh Jadav over 10 years ago in reply to hb chen

TI__Guru**** 399000 points

Hi,

You are seeing difference in the embedded sync format because you are seeing overflow. Overflow comes on Active Video data and to recover from the overflow, it takes few frames, so there is difference in number of frames captured between active video and vbi data.

In case of discrete sync capture, since there is no overflow, there should no be any frame capture differences unless there is some issue in the vsync provided. Can you please ensure that the vsync is consistently provided for 30 lines and between two vsync there is always a active video period of 720 lines.

Regards,

Brijesh

Regards,

Brijesh

0 Chuan-Hsiu Lee over 10 years ago in reply to Brijesh Jadav

Intellectual 590 points

Hi Brijesh:

Thanks for your comment.

I have found out the root cause.

In discrete mode(ACTVID+VBLK), capture link will disable VIP overflow detection.

I don't know why Ti's driver disables VIP overflow detection in discrete mode(ACTVID+VBLK).

When I comment out these code, I can see that VIP overflow is occurred in our system.

pObj->enableCheckOverflowDetect = TRUE;
if (pVipCreateArgs->videoCaptureMode ==
VPS_CAPT_VIDEO_CAPTURE_MODE_SINGLE_CH_NON_MUX_DISCRETE_SYNC_ACTVID_VBLK)
{
pObj->enableCheckOverflowDetect = FALSE;
}

Do you have any comment to avoid VIP overflow?

It is very easy to duplicate this issue, when I run iperf to transfer large packet to PC via network.

Regrads,

CH Lee

0 Brijesh Jadav over 10 years ago in reply to Chuan-Hsiu Lee

TI__Guru**** 399000 points

Hi,

Which framework and hdvpss version you are using? i think this was fixed sometimes back and overflow check was enabled for all interfaces.

Are you using any other modules in the vip pipeline? like scalar/csc/chr_ds?

Regards,

Brijesh

0 Chuan-Hsiu Lee over 10 years ago in reply to Brijesh Jadav

Intellectual 590 points

Hi,

We are using DVR RDK 03.50.00.05 and HDVPSS 01.00.01.37.

We did not use scaler/csc/chr_ds.

Input Video is YUV422.

Thanks

CH Lee

0 Brijesh Jadav over 10 years ago in reply to Chuan-Hsiu Lee

TI__Guru**** 399000 points

Hi,

What is the output format from VIP? Are you running full use case or just capture and display? This is to check if there ddr bandwidth is available for the VIP capture?

Regards,

Brijesh

0 hb chen over 10 years ago in reply to Brijesh Jadav

Expert 2640 points

Dear Brijesh,

Our output format from VIP is YUV422. We are running full case (not only capture and display).

In our system, we have 1GB size DDR3. For Linux, we allocate 384MB.
To duplicate this issue quickly, we let A8 run at 100% CPU usage (only perform a while loop count), and malloc 300MB when start application.

1) Can BW_REGULATOR Registers L3_BW_R_BANDWIDTH be used to monitor L3 bandwidth? (page 358 in SPRUGZ8C spec) Or How to monitor system bandiwdth and L3 bandwidth?

2) Currently, we think we don't have much bandwidth utilization in A8. But we let A8 run at 100% CPU usage (only perform a while loop count).
If we set DMM Priority of A8 from 4 to 7, Can this modification help to improve this situation?

3) We apply below settings, is there any other seeting to imporve this situation? (improve L3?)
0x4C000054: 00FFFF10
0x4D000054: 00FFFF10
comment out below line in init.sh >> ./bin/sys_pri.out --dmm-pri-set HDVICP0 2

4) Do you have example to use DMA in M3? Can we use DMA in M3 to improve this situation?

=====

Our system case:

                          |
                       DUP0
                   0   |     1
                   -----------
                   (I)          (P)
                   |          |
                   Dei0        |
                    |          |
                    ------------
                        |
                      Merge0
                        |
                      Select
                        |
                      DUP1
                        |
                    ----------
                    |         |
                  SCL0       SCL1
                    |         |
                  (MP4)    (MP2TS)
                    |         |
                    -----------
                        |
                      Merge1
                        |
                       NSF
                        |
                       ENC

0 Badri Narayanan over 10 years ago in reply to hb chen

TI__Guru 59700 points

hb chen said:
1) Can BW_REGULATOR Registers L3_BW_R_BANDWIDTH be used to monitor L3 bandwidth? (page 358 in SPRUGZ8C spec) Or How to monitor system bandiwdth and L3 bandwidth?

No BW Regulator cannot be used. You can use mem_stats.out which is part of dvrrdk.This will print number of DMM transactions and not actual DDR bandwidth.Another option is to use STM stats collector performance counter to measure exact DDR usage. Check http://processors.wiki.ti.com/index.php/C6A816x,_AM389x,_DM816x,_DM814x_Debug_and_Trace_Tools

Using either of these you cannot determine momentary HDVPSS DDR starvation issue.

hb chen said:
2) Currently, we think we don't have much bandwidth utilization in A8. But we let A8 run at 100% CPU usage (only perform a while loop count).
If we set DMM Priority of A8 from 4 to 7, Can this modification help to improve this situation?

What is A8 doing ? Is it just in a busy loop or is it reading and writing lot of data.Changign A8 priority fom 4 to 7 will not improve the situation.

hb chen said:
3) We apply below settings, is there any other seeting to imporve this situation? (improve L3?)
0x4C000054: 00FFFF10
0x4D000054: 00FFFF10

There isn't anything further.I think you already confirmed you have code

Utils_setL3Pressure in /dvr_rdk/mcfw/src_bios6/links_m3vpss/system/system_m3vpss.c

hb chen said:
4) Do you have example to use DMA in M3? Can we use DMA in M3 to improve this situation?

DMA on M3 is already used in DVRRDK. you can refer swmsLink. It wont help in this situation.

I want to understand the background for this test. Do you want to cause VIP overflow by intentionally maximizing A8 DDR usage ? Is max DDR bandwidth usage on A8 typical usage scenario in your application ?

0 hb chen over 10 years ago in reply to Badri Narayanan

Expert 2640 points

Dear Badri,

My original application is encode one video (1280x720 60p) to mp2ts (640x360) and mp4 (1280x720). mp2ts will use gstreamer to streaming out through network. mp4 file will be saved on SD card. In this situation, sometimes (long time) VIP overflow occurs.

Thus, I try to duplicate VIP overflow quickly to check whether any suggestion can resolve this issue.

To duplicate VIP overflow issue quickly, based on original application, I create another busy loop (do nothing) to let A8 to 100%, and malloc 300MB memory size. In this situation, we can duplicate VIP overflow issue around twice per hour.

In our experience, if A8 CPU is not so busy (keep under 70%), the duration of VIP overflow issue will be long.

I think DDR bandwidth usage and heavy A8 loading will both exist in my application.

Do I reply your question?

0 hb chen over 10 years ago in reply to hb chen

Expert 2640 points

Dear Badri,

How about speed up L3 bus speed?

Currently, out setting is

M3 Freq : 200 MHz
L3 Freq : 200 MHz
        L3_M   : 800
        L3_N   : 19
        L3_M2 : 4

Can we speed up L3 Freq in PG2.1? Will it help improve this issue?

Do you know the how to set L3_M value for speed up L3 bus?

Our setting in uboot:clock_ti814x.h

#define L3_N       19
#define L3_M       (pg_val_ti814x(880, 800))
#define L3_M2       4
#define L3_CLKCTRL   0x801

0 hb chen over 10 years ago in reply to hb chen

Expert 2640 points

Dear Badri,

Here is our bandwidth estimation in M3.

I think bandwidth should be enough for L3 bus.

But we still cannot find the root cause to improve this situation.

Plz help ~

thx ~

0 hb chen over 9 years ago in reply to hb chen

Expert 2640 points

Dear Badri,

Furthermore experiment, we only enable capture link (to null link).

But "CAPTURE: Overflow detected on VIP0" still happens.

In A8/Linux, we execute iperf.exe and simple while loop let A8/CPU to 100%.

Below is the loading of m3vpss/m3video/c6xdsp.

==============================

[m3vpss ]

[m3vpss ] 108126: LOAD: CPU: 4.2% HWI: 0.7%, SWI:1.0%

[m3vpss ]

[m3vpss ] 108126: LOAD: TSK: SYSTEM_MSGQ : 0.1%

[m3vpss ] 108126: LOAD: TSK: CAPTURE : 0.5%

[m3vpss ] 108126: LOAD: TSK: NULL0 : 0.3%

[m3vpss ] 108127: LOAD: TSK: MISC : 1.6%

[m3vpss ]

[m3video]

[m3video] 108628: LOAD: CPU: 1.8% HWI: 0.3%, SWI:0.6%

[m3video]

[m3video] 108628: LOAD: TSK: IPC_IN_M30 : 0.2%

[m3video] 108628: LOAD: TSK: ENC0 : 0.4%

[m3video] 108628: LOAD: TSK: MISC : 0.3%

[m3video]

[c6xdsp ]

[c6xdsp ] 108604: LOAD: CPU: 0.2% HWI: 0.0%, SWI:0.0%

[c6xdsp ]

[c6xdsp ] 108604: LOAD: TSK: MISC : 0.2%

[c6xdsp ]

[m3vpss ] VIP(PortA) detect overflow VIP_Parser_FIQ_Status:10

[m3vpss ] 183697: CAPTURE: Overflow detected on VIP0, Total Resets = 1

==============================

Plz reply ~

thx ~

0 Badri Narayanan over 9 years ago in reply to hb chen

TI__Guru 59700 points

1. Pls share your uboot and kernel boot logs

2. Pls clarify on what experiment you are trying to recreate VIP overflow.

1. Are you running iperf

2. Are you running some busy loop on A8 which does nothing but only causes CPU load to be 100%.

Running iperf has potential to cause DDR starvation on VIP but just making CPU load 100% on A8 will not affect HDVPSS. If you are seeing VIP overflow by just adding a busy loop on A8 this issue is not related to DDR.

3. Share the mem_stats log before and after you make A8 100% load. We need to check if number of DDR transactions from A8 is increasing.

4. Collect the DDR bandwidth using CCS + XDS560v2 using the link I shared previously . COllect the data before and after you make A8 CPU 100%

.5 Modify /dvr_rdk_hdvpss/packages/ti/psp/vps/hal/src/vpshal_vpdmaDebug.c

Int32 VpsHal_vpdmaPrintPerfMonRegs(void)
{
CSL_VpsVpdmaRegsOvly regOvly;

regOvly = VpdmaBaseAddress;

    GT_4trace(VpsHalVpdmaDebugTrace, GT_INFO,
        " VPDMA: PERF_MON34 = 0x%08x, PERF_MON35 = 0x%08x, "
        "PERF_MON38 = 0x%08x, PERF_MON39 = 0x%08x \r\n",
        regOvly->PERF_MON34,
        regOvly->PERF_MON35,
        regOvly->PERF_MON38,
        regOvly->PERF_MON39);

return 0;
}

Modify GT_4trace to Vps_rprintf in above function. After this change collect Vsys_printDetailedStatistics log after starting capture but before any VIP overflow and after VIP overflow

0 hb chen over 9 years ago in reply to Badri Narayanan

Expert 2640 points

Dear Badri,

According to your suggestions, we did item 1)/2)/3)/5).

About 1)/3)/5) item. Plz check attached log file.

1805.vip_overflow.txt

U-boot & Linux Kernel Log
U-Boot 2010.06-svn451 (Mar 11 2013 - 10:02:14)

TI8148-GP rev 2.1

ARM clk: 720MHz
DDR clk: 400MHz

DRAM:  2 GiB
Using default environment

The 2nd stage U-Boot will now be auto-loaded
Please do not interrupt the countdown till TI8148_EVM prompt if 2nd stage is already flashed
Hit any key to stop autoboot:  0
512 KiB SST25VF040B at 0:0 is now current device
## Starting application at 0x81000000 ...


U-Boot 2010.06-svn451 (Mar 11 2013 - 10:02:45)

TI8148-GP rev 2.1

ARM clk: 720MHz
DDR clk: 400MHz

I2C:   ready
DRAM:  2 GiB
NAND:  HW ECC BCH8 Selected
No NAND device found!!!
0 MiB
MMC:   OMAP SD/MMC: 0, OMAP SD/MMC: 1
                          .:;rrr;;.
                    ,5#@@@@#####@@@@@@#2,
                 ,A@@@hi;;;r5;;;;r;rrSG@@@A,
               r@@#i;:;s222hG;rrsrrrrrr;ri#@@r
             :@@hr:r;SG3ssrr2r;rrsrsrsrsrr;rh@@:
            B@H;;rr;3Hs;rrr;sr;;rrsrsrsrsrsr;;H@B
           @@s:rrs;5#;;rrrr;r#@H:;;rrsrsrsrsrr:s@@
          @@;;srs&X#9;r;r;;,2@@@rrr:;;rrsrsrsrr;;@@
         @@;;rrsrrs@MB#@@@@@###@@@@@@#rsrsrsrsrr;;@@
        G@r;rrsrsr;#X;SX25Ss#@@#M@#9H9rrsrsrsrsrs;r@G
        @9:srsrsrs;2@;:;;:.X@@@@@H::;rrsrsrsrsrsrr:3@
       X@;rrsrsrsrr;XAi;;:&@@#@Bs:rrsrsrsrsrsrsrsrr;@X
       @#;rsrsrsrsrr;r2ir@@@###::rrsrsrsrsrsrsrsrsr:@@
       @A:rrsrsrsrr;:2@29@@M@@@;:;rrrrsrsrsrsrsrsrs;H@
       @&;rsrsrsrr;A@@@@@@###@@@s::;:;;rrsrsrsrsrsr;G@
       @#:rrsrsrsr;G@5Hr25@@@#@@@#9XG9s:rrrrsrsrsrs:#@
       M@;rsrsrsrs;r@&#;::S@@@@@@@M@@@@Grr:;rsrsrsr;@#
       :@s;rsrsrsrr:M#Msrr;;&#@@@@@@@@@@H@@5;rsrsr;s@,
        @@:rrsrsrsr;S@rrrsr;:;r3MH@@#@M5,S@@irrsrr:@@
         @A:rrsrsrsrrrrrsrsrrr;::;@##@r:;rH@h;srr:H@
         ;@9:rrsrsrsrrrsrsrsrsr;,S@Hi@i:;s;MX;rr:h@;
          r@B:rrrrsrsrsrsrsrr;;sA@#i,i@h;r;S5;r:H@r
           ,@@r;rrrsrsrsrsrr;2BM3r:;r:G@:rrr;;r@@,
             B@Mr;rrrrsrsrsr@@S;;;rrr:5M;rr;rM@H
              .@@@i;;rrrrsrs2i;rrrrr;r@M:;i@@@.
                .A@@#5r;;;r;;;rrr;r:r#AsM@@H.
                   ;&@@@@MhXS5i5SX9B@@@@G;
                       :ihM#@@@@@##hs,

Net:   Detected MACID:50:56:63:b8:77:aa
cpsw
Hit any key to stop autoboot:  0
Device: OMAP SD/MMC
Manufacturer ID: 11
OEM: 100
Name: 008G9
Tran Speed: 25000000
Rd Block Len: 512
MMC version 4.0
High Capacity: Yes
Capacity: 7818182656
Bus Width: 4-bit
reading uImage_20140305

2717128 bytes read
## Booting kernel from Legacy Image at 81000000 ...
   Image Name:   Linux-2.6.37+
   Image Type:   ARM Linux Kernel Image (uncompressed)
   Data Size:    2717064 Bytes = 2.6 MiB
   Load Address: 80008000
   Entry Point:  80008000
   Verifying Checksum ... OK
   Loading Kernel Image ... OK
OK

Starting kernel ...

Uncompressing Linux... done, booting the kernel.
Linux version 2.6.37+ (chlee@linux-computer) (gcc version 4.3.3 (Sourcery G++ Lite 2009q1-203) ) #6 PREEMPT Wed Mar 5 16:56:34 CST 2014
CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c53c7f
CPU: VIPT nonaliasing data cache, VIPT aliasing instruction cache
Machine: ti8148evm
ti81xx_reserve: ### Reserved DDR region @97f00000
reserved size = 0 at 0x0
Memory policy: ECC disabled, Data cache writeback
OMAP chip is TI8148 2.1
SRAM: Mapped pa 0x402f1000 to va 0xfe400000 size: 0xf000
Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 97280
Kernel command line: mem=384M ddr_mem=1024M console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=172.17.15.202:/home1/chlee/Sony_Project/Corsica_1v1/target/rfs_814x ip=dhcp notifyk.vpssm3_sva=0xBFD00000
PID hash table entries: 2048 (order: 1, 8192 bytes)
Dentry cache hash table entries: 65536 (order: 6, 262144 bytes)
Inode-cache hash table entries: 32768 (order: 5, 131072 bytes)
Memory: 383MB = 383MB total
Memory: 382820k/382820k available, 10396k reserved, 0K highmem
Virtual kernel memory layout:
    vector  : 0xffff0000 - 0xffff1000   (   4 kB)
    fixmap  : 0xfff00000 - 0xfffe0000   ( 896 kB)
    DMA     : 0xffc00000 - 0xffe00000   (   2 MB)
    vmalloc : 0xd8800000 - 0xf8000000   ( 504 MB)
    lowmem  : 0xc0000000 - 0xd8000000   ( 384 MB)
    pkmap   : 0xbfe00000 - 0xc0000000   (   2 MB)
    modules : 0xbf000000 - 0xbfe00000   (  14 MB)
      .init : 0xc0008000 - 0xc0040000   ( 224 kB)
      .text : 0xc0040000 - 0xc0532000   (5064 kB)
      .data : 0xc0532000 - 0xc057b5c0   ( 294 kB)
SLUB: Genslabs=11, HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
NR_IRQS:375
IRQ: Found an INTC at 0xfa200000 (revision 5.0) with 128 interrupts
Total of 128 interrupts on 1 active controller
GPMC revision 6.0
Trying to install interrupt handler for IRQ368
Trying to install interrupt handler for IRQ369
Trying to install interrupt handler for IRQ370
Trying to install interrupt handler for IRQ371
Trying to install interrupt handler for IRQ372
Trying to install interrupt handler for IRQ373
Trying to install interrupt handler for IRQ374
Trying to install type control for IRQ375
Trying to set irq flags for IRQ375
OMAP clockevent source: GPTIMER1 at 20000000 Hz
Console: colour dummy device 80x30
Calibrating delay loop... 719.25 BogoMIPS (lpj=3596288)
pid_max: default: 32768 minimum: 301
Security Framework initialized
Mount-cache hash table entries: 512
CPU: Testing write buffer coherency: ok
devtmpfs: initialized
TI81XX: Map 0x97f00000 to 0xfe500000 for dram barrier
TI81XX: Map 0x40300000 to 0xfe600000 for sram barrier
omap_voltage_early_init: voltage driver support not added
regulator: core version 0.5
regulator: dummy:
NET: Registered protocol family 16
omap_voltage_domain_lookup: Voltage driver init not yet happened.Faulting!
omap_voltage_add_dev: VDD specified does not exist!
OMAP GPIO hardware version 0.1
OMAP GPIO hardware version 0.1
OMAP GPIO hardware version 0.1
OMAP GPIO hardware version 0.1
omap_mux_init: Add partition: #1: core, flags: 4
_omap_mux_init_gpio: Could not set gpio38
_omap_mux_init_gpio: Could not set gpio35
clk get on i2c3 fck failed
Cannot clk_get ck_32
Debugfs: Only enabling/disabling deep sleep and wakeup timer is supported now
registered ti81xx_vpss device
registered ti81xx_vidout device
registered ti81xx_vin device
bio: create slab <bio-0> at 0
SCSI subsystem initialized
usbcore: registered new interface driver usbfs
usbcore: registered new interface driver hub
usbcore: registered new device driver usb
USBSS revision 4ea2080b
registerd cppi-dma Intr @ IRQ 17
Cppi41 Init Done
omap_i2c omap_i2c.1: bus 1 rev4.0 at 100 kHz
omap_i2c omap_i2c.2: bus 2 rev4.0 at 100 kHz
Advanced Linux Sound Architecture Driver Version 1.0.23.
Switching to clocksource gp timer
musb-hdrc: version 6.0, host, debug=0
musb-hdrc musb-hdrc.0: dma type: dma-cppi41
MUSB controller-0 revision 4ea20800
usb2phy_config: musb(0) rxcalib done, rxcalib read value 6f6e5b8e
musb-hdrc musb-hdrc.0: MUSB HDRC host driver
musb-hdrc musb-hdrc.0: new USB bus registered, assigned bus number 1
usb usb1: New USB device found, idVendor=1d6b, idProduct=0002
usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1
usb usb1: Product: MUSB HDRC host driver
usb usb1: Manufacturer: Linux 2.6.37+ musb-hcd
usb usb1: SerialNumber: musb-hdrc.0
usb usb1: DeviceClass=0x09
usb usb1: InterfaceClass=0x09
hub 1-0:1.0: USB hub found
busnum(1)
idVendor(0x1d6b) idProduct(2)
hub 1-0:1.0: 1 port detected
hub_configure bbb ed
hub_testmode_init_1
hub_testmode_init_1 4271
musb-hdrc musb-hdrc.0: USB Host mode controller at d881e000 using DMA, IRQ 18
musb-hdrc musb-hdrc.1: dma type: dma-cppi41
MUSB controller-1 revision 4ea20800
usb2phy_config: musb(1) rxcalib done, rxcalib read value 6f726176
musb-hdrc musb-hdrc.1: MUSB HDRC host driver
musb-hdrc musb-hdrc.1: new USB bus registered, assigned bus number 2
usb usb2: New USB device found, idVendor=1d6b, idProduct=0002
usb usb2: New USB device strings: Mfr=3, Product=2, SerialNumber=1
usb usb2: Product: MUSB HDRC host driver
usb usb2: Manufacturer: Linux 2.6.37+ musb-hcd
usb usb2: SerialNumber: musb-hdrc.1
usb usb2: DeviceClass=0x09
usb usb2: InterfaceClass=0x09
hub 2-0:1.0: USB hub found
busnum(2)
idVendor(0x1d6b) idProduct(2)
hub 2-0:1.0: 1 port detected
hub_configure bbb ed
hub_testmode_init_2
hub_testmode_init_2 4287
musb-hdrc musb-hdrc.1: USB Host mode controller at d8828800 using DMA, IRQ 19
NET: Registered protocol family 2
IP route cache hash table entries: 4096 (order: 2, 16384 bytes)
TCP established hash table entries: 16384 (order: 5, 131072 bytes)
TCP bind hash table entries: 16384 (order: 4, 65536 bytes)
TCP: Hash tables configured (established 16384 bind 16384)
TCP reno registered
UDP hash table entries: 256 (order: 0, 4096 bytes)
UDP-Lite hash table entries: 256 (order: 0, 4096 bytes)
NET: Registered protocol family 1
RPC: Registered udp transport module.
RPC: Registered tcp transport module.
RPC: Registered tcp NFSv4.1 backchannel transport module.
NetWinder Floating Point Emulator V0.97 (double precision)
PMU: registered new PMU device of type 0
omap-iommu omap-iommu.0: ducati registered
omap-iommu omap-iommu.1: sys registered
JFFS2 version 2.2. (NAND) ? 2001-2006 Red Hat, Inc.
msgmni has been set to 747
io scheduler noop registered
io scheduler deadline registered
io scheduler cfq registered (default)
Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
omap_uart.0: ttyO0 at MMIO 0x48020000 (irq = 72) is a OMAP UART0
console [ttyO0] enabled
omap_uart.1: ttyO1 at MMIO 0x48022000 (irq = 73) is a OMAP UART1
omap_uart.2: ttyO2 at MMIO 0x48024000 (irq = 74) is a OMAP UART2
omap_uart.3: ttyO3 at MMIO 0x481a6000 (irq = 44) is a OMAP UART3
omap_uart.4: ttyO4 at MMIO 0x481a8000 (irq = 45) is a OMAP UART4
omap_uart.5: ttyO5 at MMIO 0x481aa000 (irq = 46) is a OMAP UART5
brd: module loaded
loop: module loaded
omap2-nand driver initializing
davinci_mdio davinci_mdio.0: davinci mdio revision 1.6
davinci_mdio davinci_mdio.0: detected phy mask ffeffffb
davinci_mdio.0: probed
davinci_mdio davinci_mdio.0: phy[2]: device 0:02, driver unknown
davinci_mdio davinci_mdio.0: phy[20]: device 0:14, driver unknown
usbcore: registered new interface driver cdc_ether
usbcore: registered new interface driver dm9601
usbcore: registered new interface driver cdc_acm
cdc_acm: v0.26:USB Abstract Control Model driver for USB modems and ISDN adapters
Initializing USB Mass Storage driver...
usbcore: registered new interface driver usb-storage
USB Mass Storage support registered.
mice: PS/2 mouse device common for all mice
rtc-s35390a 2-0030: rtc core: registered rtc-s35390a as rtc0
i2c /dev entries driver
Linux video capture interface: v2.00
usbcore: registered new interface driver uvcvideo
USB Video Class driver (v1.0.0)
OMAP Watchdog Timer Rev 0x00: initial timeout 60 sec
usbcore: registered new interface driver usbhid
usbhid: USB HID core driver
notify_init : notify drivercreated  for  remote proc id 2 at physical Address 0xbfd00000
usbcore: registered new interface driver snd-usb-audio
Registered tvp5158 audio codec
asoc: HDMI-DAI-CODEC <-> hdmi-dai mapping ok
asoc: ACLVFE-DAI-CODEC <-> davinci-mcasp.0 mapping ok
asoc: ACLVFE-DAI-CODEC <-> davinci-mcasp.1 mapping ok
asoc: HDMI-DAI-CODEC <-> hdmi-dai mapping ok
ALSA device list:
  #0: TI8168 ACLVFE
  #1: TI81XX SOUND1
Netfilter messages via NETLINK v0.30.
nf_conntrack version 0.5.0 (5981 buckets, 23924 max)
ctnetlink v0.93: registering with nfnetlink.
ip_tables: (C) 2000-2006 Netfilter Core Team
TCP cubic registered
NET: Registered protocol family 17
Registering the dns_resolver key type
VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
omap_voltage_late_init: Voltage driver support not added
Power Management for TI81XX.
mmc0: new high speed MMC card at address 0001
mmcblk0: mmc0:0001 008G92 7.28 GiB
 mmcblk0: p1 p2
Detected MACID=50:56:63:b8:77:aa
Detected MACID=50:56:63:b8:77:ab
rtc-s35390a 2-0030: setting system clock to 2014-04-29 00:55:34 UTC (1398732934)

CPSW phy found : id is : 0x3625d12
IP-Config: Failed to open eth1
Sending DHCP requests .
PHY: 0:02 - Link is Up - 100/Full
., OK
IP-Config: Got DHCP answer from 0.0.0.0, my address is 172.17.14.42
IP-Config: Complete:
     device=eth0, addr=172.17.14.42, mask=255.255.254.0, gw=172.17.15.254,
     host=172.17.14.42, domain=advantech.corp, nis-domain=(none),
     bootserver=0.0.0.0, rootserver=172.17.15.202, rootpath=
VFS: Mounted root (nfs filesystem) on device 0:15.
devtmpfs: mounted
Freeing init memory: 224K
Starting logging: OK
Initializing random number generator... done.
Starting network...
ip: RTNETLINK answers: File exists
Starting sshd: OK

=================================================================================================================================
Before runnng A8 cpu busy 
 # MEM STATS Started !!! (1000 msecs sampling time)
 #
 # [ ALL      ]    2.380 M req/sec
 # [ IVA_0    ]    0.000 M req/sec
 # [ IVA_1    ]    0.000 M req/sec
 # [ IVA_2    ]    0.000 M req/sec
 # [ HDVPSS_0 ]    0.000 M req/sec
 # [ HDVPSS_1 ]    0.441 M req/sec
 # [ A8       ]    0.009 M req/sec
 # [ M3       ]    1.930 M req/sec
 # [ EDMA_0_RD]    0.000 M req/sec
 # [ EDMA_0_WR]    0.000 M req/sec
 # [ EDMA_1_RD]    0.000 M req/sec
 # [ EDMA_1_WR]    0.000 M req/sec
 # [ EDMA_2_RD]    0.000 M req/sec
 # [ EDMA_2_WR]    0.000 M req/sec
 # [ EDMA_3_RD]    0.000 M req/sec
 # [ EDMA_3_WR]    0.000 M req/sec
 # [ EMAC_0   ]    0.000 M req/sec
 # [ EMAC_1   ]    0.000 M req/sec
 # [ USB_DMA  ]    0.000 M req/sec
 # [ USB_QMGR ]    0.000 M req/sec
 # [ SATA     ]    0.000 M req/sec
 # [ PCIE     ]    0.000 M req/sec
 # [ DSP_MDMA ]    0.000 M req/sec
 # [ DSP_CFG  ]    0.000 M req/sec
 # [ SYS_MMU  ]    0.000 M req/sec
 # [ ALL      ]    2.377 M req/sec
 #
=====================================================================================================================
After running A8 cpu busy
 # MEM STATS Started !!! (1000 msecs sampling time)
 #
 # [ ALL      ]    2.377 M req/sec
 # [ IVA_0    ]    0.000 M req/sec
 # [ IVA_1    ]    0.000 M req/sec
 # [ IVA_2    ]    0.000 M req/sec
 # [ HDVPSS_0 ]    0.000 M req/sec
 # [ HDVPSS_1 ]    0.441 M req/sec
 # [ A8       ]    0.008 M req/sec
 # [ M3       ]    1.926 M req/sec
 # [ EDMA_0_RD]    0.000 M req/sec
 # [ EDMA_0_WR]    0.000 M req/sec
 # [ EDMA_1_RD]    0.000 M req/sec
 # [ EDMA_1_WR]    0.000 M req/sec
 # [ EDMA_2_RD]    0.000 M req/sec
 # [ EDMA_2_WR]    0.000 M req/sec
 # [ EDMA_3_RD]    0.000 M req/sec
 # [ EDMA_3_WR]    0.000 M req/sec
 # [ EMAC_0   ]    0.000 M req/sec
 # [ EMAC_1   ]    0.000 M req/sec
 # [ USB_DMA  ]    0.000 M req/sec
 # [ USB_QMGR ]    0.000 M req/sec
 # [ SATA     ]    0.000 M req/sec
 # [ PCIE     ]    0.000 M req/sec
 # [ DSP_MDMA ]    0.000 M req/sec
 # [ DSP_CFG  ]    0.000 M req/sec
 # [ SYS_MMU  ]    0.000 M req/sec
 # [ ALL      ]    2.378 M req/sec
 #
===========================================================================================================================================
[m3vpss ] VIP(PortA) detect overflow VIP_Parser_FIQ_Status:10
 [m3vpss ]  8277530: CAPTURE: Overflow detected on VIP0, Total Resets = 1
[host] Unknown MP4 State
[host] SYSLINK is Living
[host] Unknown MP4 State
[host] SYSLINK is Living
[host] Unknown MP4 State
[host] SYSLINK is Living
[host] Unknown MP4 State
[host] SYSLINK is Living
[host] Unknown MP4 State
[host] SYSLINK is Living
p
 [m3vpss ]
 [m3vpss ]  *** CAPTURE Statistics ***
 [m3vpss ] 8416159: CAPTURE: Queued to driver = 1008210, Dequeued from driver = 1008178
 [m3vpss ] CAPTURE [0] Buf Q Status
 [m3vpss ] Empty Q -> count 0, wrPtr 0, rdPtr 0
 [m3vpss ] Full Q -> count 0, wrPtr 280, rdPtr 280
 [m3vpss ]
 [m3vpss ]  *** [DEI3    ] DEI Statistics ***
 [m3vpss ] 8416160: DEI: Rcvd from prev = 0, Returned to prev = 0
 [m3vpss ] DEI Out [0] Buf Q Status
 [m3vpss ] Empty Q -> count 0, wrPtr 0, rdPtr 0
 [m3vpss ] Full Q -> count 0, wrPtr 0, rdPtr 0
 [m3vpss ] DEI Out [1] Buf Q Status
 [m3vpss ] Empty Q -> count 0, wrPtr 0, rdPtr 0
 [m3vpss ] Full Q -> count 0, wrPtr 0, rdPtr 0
 [m3vpss ] DEI Out [2] Buf Q Status
 [m3vpss ] Empty Q -> count 0, wrPtr 0, rdPtr 0
 [m3vpss ] Full Q -> count 0, wrPtr 0, rdPtr 0
 [m3vpss ] DEI Out [3] Buf Q Status
 [m3vpss ] Empty Q -> count 0, wrPtr 0, rdPtr 0
 [m3vpss ] Full Q -> count 0, wrPtr 0, rdPtr 0
 [m3vpss ] DEI Out [4] Buf Q Status
 [m3vpss ] Empty Q -> count 0, wrPtr 0, rdPtr 0
 [m3vpss ] Full Q -> count 0, wrPtr 0, rdPtr 0
 [m3vpss ]
 [m3vpss ]  *** [BUFCTRL0 ] BufCtrl Buffer Statistics ***
 [m3vpss ] BufCtrl[Metadata][0] Buf Q Status
 [m3vpss ] Empty Q -> count 600, wrPtr 0, rdPtr 0
 [m3vpss ] Ring Buf:614400,0,614400
 [m3vpss ] Full Q -> count 0, wrPtr 0, rdPtr 0
 [m3vpss ] BufCtrl[Metadata][1] Buf Q Status
 [m3vpss ] Empty Q -> count 600, wrPtr 0, rdPtr 0
 [m3vpss ] Ring Buf:614400,0,614400
 [m3vpss ] Full Q -> count 0, wrPtr 0, rdPtr 0
 [m3video]
 [m3video]  *** [BUFCTRL0 ] BufCtrl Buffer Statistics ***
 [m3video] BufCtrl[Video][0] Buf Q Status
 [m3video] Empty Q -> count 600, wrPtr 0, rdPtr 0
 [m3video] Ring Buf:15728640,0,15728640
 [m3video] Full Q -> count 0, wrPtr 0, rdPtr 0
 [m3video] BufCtrl[Video][1] Buf Q Status
 [m3video] Empty Q -> count 600, wrPtr 0, rdPtr 0
 [m3video] Ring Buf:8388608,0,8388608
 [m3video] Full Q -> count 0, wrPtr 0, rdPtr 0
 [m3video] BufCtrl[Video][2] Buf Q Status
 [m3video] Empty Q -> count 600, wrPtr 0, rdPtr 0
 [m3video] Ring Buf:8388608,0,8388608
 [m3video] Full Q -> count 0, wrPtr 0, rdPtr 0
 [m3video] BufCtrl[Video][3] Buf Q Status
 [m3video] Empty Q -> count 600, wrPtr 0, rdPtr 0
 [m3video] Ring Buf:204800,0,204800
 [m3video] Full Q -> count 0, wrPtr 0, rdPtr 0
 [c6xdsp ]
 [c6xdsp ]  *** [BUFCTRL0 ] BufCtrl Buffer Statistics ***
 [c6xdsp ] BufCtrl[Audio][0] Buf Q Status
 [c6xdsp ] Empty Q -> count 600, wrPtr 0, rdPtr 0
 [c6xdsp ] Ring Buf:307200,0,307200
 [c6xdsp ] Full Q -> count 0, wrPtr 0, rdPtr 0
 [c6xdsp ] BufCtrl[Audio][1] Buf Q Status
 [c6xdsp ] Empty Q -> count 600, wrPtr 0, rdPtr 0
 [c6xdsp ] Ring Buf:307200,0,307200
 [c6xdsp ] Full Q -> count 0, wrPtr 0, rdPtr 0
 [c6xdsp ] BufCtrl[Audio][2] Buf Q Status
 [c6xdsp ] Empty Q -> count 600, wrPtr 0, rdPtr 0
 [c6xdsp ] Ring Buf:307200,0,307200
 [c6xdsp ] Full Q -> count 0, wrPtr 0, rdPtr 0
 [c6xdsp ]
 [c6xdsp ]  *** [AAC_Encoder0] AAC Encoder Buffer Statistics ***
 [c6xdsp ] AAC Encoder Buf Q Status
 [c6xdsp ] Empty Q -> count 48, wrPtr 48, rdPtr 0
 [c6xdsp ] Full Q -> count 0, wrPtr 0, rdPtr 0
 [c6xdsp ] Channel[0]:Audio Samples(Raw):0
 [c6xdsp ] Channel[0]:Audio Samples(Encode):0
 [c6xdsp ] Channel[1]:Audio Samples(Raw):0
 [c6xdsp ] Channel[1]:Audio Samples(Encode):0
 [c6xdsp ] Channel[2]:Audio Samples(Raw):0
 [c6xdsp ] Channel[2]:Audio Samples(Encode):0
 [m3vpss ]  ===
 [m3vpss ] VBIHandlLink Buffer Statistics
 [m3vpss ] VBIHandlLink Buf Q Status
 [m3vpss ] A Empty Q -> count 384, wrPtr 0, rdPtr 0
 [m3vpss ] A Full Q -> count 0, wrPtr 0, rdPtr 0
 [m3vpss ] M Empty Q -> count 384, wrPtr 0, rdPtr 0
 [m3vpss ] M Full Q -> count 0, wrPtr 0, rdPtr 0
 [m3vpss ] vbinin(0) Length: Ch0(0) Ch1(0) Ch2(0)
 [m3vpss ]
 [m3vpss ]  *** [VIDEOHANDL0] VideoHandlLink Encoder Buffer Statistics ***
 [m3vpss ] VideoHandlLink Buf Q Status
 [m3vpss ] metacmdcnt(0) videocmdcnt(0)
 [m3vpss ] OutFrame Empty Q -> count 256, wrPtr 256, rdPtr 0
 [m3vpss ] OutFrame Full Q -> count 0, wrPtr 0, rdPtr 0
 [m3vpss ] M Empty Q -> count 384, wrPtr 0, rdPtr 0
 [m3vpss ] M Full Q -> count 0, wrPtr 0, rdPtr 0
 [m3vpss ]
 [m3vpss ]  *** [VIDEOHANDL1] VideoHandlLink Encoder Buffer Statistics ***
 [m3vpss ] VideoHandlLink Buf Q Status
 [m3vpss ] metacmdcnt(0) videocmdcnt(0)
 [m3vpss ] OutFrame Empty Q -> count 256, wrPtr 256, rdPtr 0
 [m3vpss ] OutFrame Full Q -> count 0, wrPtr 0, rdPtr 0
 [m3vpss ] M Empty Q -> count 384, wrPtr 0, rdPtr 0
 [m3vpss ] M Full Q -> count 0, wrPtr 0, rdPtr 0
 [m3video]
 [m3video]  *** Encode Statistics ***
 [m3video]   8419168: ENC: Rcvd from prev = 0, Returned to prev = 0
 [m3video]  ENC Out  BitBuf Q Status
 [m3video] Empty Q 0 -> count 16, wrPtr 16, rdPtr 0
 [m3video] Full Q -> count 0, wrPtr 0, rdPtr 0
 [m3vpss ]
 [m3vpss ]  *** Capture Driver Advanced Statistics ***
 [m3vpss ]
 [m3vpss ]  VIP Parser Reset Count : 1
 [m3vpss ]
 [m3vpss ]      |   Total    Even     Odd  Total  Even   Odd  Min /  Max  Min /  Max Dropped Fid Repeat Frame Error Y/C
 [m3vpss ]  CH  |  Fields  Fields  Fields    FPS   FPS   FPS       Width      Height  Fields      Count (Desc Error Y/C)
 [m3vpss ]  ------------------------------------------------------------------------------------------------------------
 [m3vpss ]  000 |  504301  504301       0     59    59     0 1280 / 1280  720 /  720       2          0 0/0 (0/0)
 [m3vpss ]  010 |  504303  504303       0     59    59     0 1280 / 1280   30 /   30       2          0 0/0 (0/0)
 [m3vpss ]
 [m3vpss ]  VIP Capture Port 0 | DescMissMatch1 = 0, DescMissMatch2 = 0 , DescMissMatch3 = 0
 [m3vpss ]
 [m3vpss ]  *** Capture List Manager Advanced Statistics ***
 [m3vpss ]
 [m3vpss ]  List Post Count        : 1051704
 [m3vpss ]  List Stall Count       : 0
 [m3vpss ]  List Post Time (ms)    : Max = 1, Min = 0, Avg = 0, Total = 6
 [m3vpss ]  INTC Timeout Count     : (0, 0) (Min timeout value = 991, 1000)
 [m3vpss ]  Descriptor miss found count : 0
 [m3vpss ]
 [m3vpss ]
 [m3vpss ]  VIP and VPDMA registers,
 [m3vpss ]  VIP0 : FIQ_STATUS  : 0x4810551c = 0x00000000
 [m3vpss ]  VIP1 : FIQ_STATUS  : 0x48105a1c = 0x00000000
 [m3vpss ]  VPDMA: LIST_BUSY   : 0x4810d00c = 0x00000000
 [m3vpss ]  VPDMA: PERF_MON34 = 0x4305ffff, PERF_MON35 = 0x4305ffff, PERF_MON38 = 0x4305ffff, PERF_MON39 = 0x4305ffff
 [m3vpss ]
 [m3vpss ]
 [m3vpss ]  8419670: CAPTURE: Fields = 1008598 (fps = 119, CPU Load = 0)
 [m3vpss ]  8419671: CAPTURE: Num Resets = 1 (Avg 14 ms per reset)
 [m3vpss ]  8419671: SYSTEM  : FREE SPACE : System Heap      = 241272 B, Mbx = 10239 msgs)
 [m3vpss ]  8419671: SYSTEM  : FREE SPACE : SR0 Heap         = 8275328 B (7 MB)
 [m3vpss ]  8419671: SYSTEM  : FREE SPACE : Frame Buffer     = 236861312 B (225 MB)
 [m3vpss ]  8419671: SYSTEM  : FREE SPACE : Bitstream Buffer = 5533568 B (5 MB)
 [m3vpss ]
 [m3vpss ]  *** [Scalar0   ] SCLR Statistics ***
 [m3vpss ]
 [m3vpss ]  Elasped Time           : 8377 secs
 [m3vpss ]  Total Fields Processed : 0
 [m3vpss ]  Total Fields FPS       : 0 FPS
 [m3vpss ]
 [m3vpss ]
 [m3vpss ]  CH  | In Recv In Reject In Process Out Skip Out User Out Latency
 [m3vpss ]  Num | FPS     FPS       FPS        FPS    FPS   Skip FPS Min / Max
 [m3vpss ]  ---------------------------------------------------------------------
 [m3vpss ]    0 |       0         0          0   0        0        0 255   0
 [m3vpss ]
 [m3vpss ]  8419672: SYSTEM  : FREE SPACE : Tiler Buffer     = 127 B (0 MB)  - TILER OFF
 [m3vpss ]
 [m3vpss ]  *** [Scalar1   ] SCLR Statistics ***
 [m3vpss ]
 [m3vpss ]  Elasped Time           : 8377 secs
 [m3vpss ]  Total Fields Processed : 0
 [m3vpss ]  Total Fields FPS       : 0 FPS
 [m3vpss ]
 [m3vpss ]
 [m3vpss ]  CH  | In Recv In Reject In Process Out Skip Out User Out Latency
 [m3vpss ]  Num | FPS     FPS       FPS        FPS    FPS   Skip FPS Min / Max
 [m3vpss ]  ---------------------------------------------------------------------
 [m3vpss ]    0 |       0         0          0   0        0        0 255   0
 [m3vpss ]
 [m3vpss ]
 [m3vpss ]  *** [DEI3    ] DEI Statistics ***
 [m3vpss ]
 [m3vpss ]  Elasped Time           : 8377 secs
 [m3vpss ]  Total Fields Processed : 0
 [m3vpss ]  Total Fields FPS       : 0 FPS
 [m3vpss ]
 [m3vpss ]
 [m3vpss ]  CH  | In Recv In Reject In Process Out[0] Out[1] Out[2] Out[3] Out[4] Skip Out[0] Skip Out[1] Skip Out[2] Skip Out[3] Skip Out[4] User Out[0] User Out[1] User Out[2] User Out[3] User Out[4] Latency
 [m3vpss ]  Num | FPS     FPS       FPS        FPS    FPS    FPS    FPS    FPS       FPS         FPS         FPS         FPS         FPS       Skip FPS    Skip FPS    Skip FPS    Skip FPS    Skip FPS   Min / Max
 [m3vpss ]  -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
 [m3vpss ]    0 |       0         0          0      0      0      0      0      0           0           0           0           0           0           0           0           0           0           0 255 /   0
 [m3vpss ]
 [m3vpss ]
 [m3vpss ]  *** [BUFCTRL0 ] BufCtrl Statistics ***
 [m3vpss ] BufCtrl[Metadata][0]:in data:0,out data: 0
 [m3vpss ]
 [m3vpss ] BufCtrl[Metadata][1]:in data:0,out data: 0
 [m3vpss ]
 [m3video]      8425677: HDVICP-ID:0
 [m3video] All percentage figures are based off totalElapsedTime
 [m3video]               totalAcquire2wait :0 %
 [m3video]               totalWait2Isr :0 %
 [m3video]               totalIsr2Done :0 %
 [m3video]               totalWait2Done :0 %
 [m3video]               totalDone2Release :0 %
 [m3video]               totalAcquire2Release :0 %
 [m3video]               totalAcq2acqDelay :0 %
 [m3video]               totalElapsedTime in msec :       0
 [m3video]               numAccessCnt:       0
 [m3video]              IVA-FPS :       0
 [m3video]              Average time spent per frame in microsec:       0
 [m3video]      8425678: HDVICP-ID:1
 [m3video] All percentage figures are based off totalElapsedTime
 [m3video]               totalAcquire2wait :0 %
 [m3video]               totalWait2Isr :0 %
 [m3video]               totalIsr2Done :0 %
 [m3video]               totalWait2Done :0 %
 [m3video]               totalDone2Release :0 %
 [m3video]               totalAcquire2Release :0 %
 [m3video]               totalAcq2acqDelay :0 %
 [m3video]               totalElapsedTime in msec :       0
 [m3video]               numAccessCnt:       0
 [m3video]              IVA-FPS :       0
 [m3video]              Average time spent per frame in microsec:       0
 [m3video]      8425678: HDVICP-ID:2
 [m3video] All percentage figures are based off totalElapsedTime
 [m3video]               totalAcquire2wait :0 %
 [m3video]               totalWait2Isr :0 %
 [m3video]               totalIsr2Done :0 %
 [m3video]               totalWait2Done :0 %
 [m3video]               totalDone2Release :0 %
 [m3video]               totalAcquire2Release :0 %
 [m3video]               totalAcq2acqDelay :0 %
 [m3video]               totalElapsedTime in msec :       0
 [m3video]               numAccessCnt:       0
 [m3video]              IVA-FPS :       0
 [m3video]              Average time spent per frame in microsec:       0
 [m3video]
 [m3video]  *** [BUFCTRL0 ] BufCtrl Statistics ***
 [m3video] BufCtrl[Video][0]:in data:0,out data: 0
 [m3video]
 [m3video] BufCtrl[Video][1]:in data:0,out data: 0
 [m3video]
 [m3video] BufCtrl[Video][2]:in data:0,out data: 0
 [m3video]
 [m3video] BufCtrl[Video][3]:in data:0,out data: 0
 [m3video]
 [m3video]
 [m3video]  *** ENCODE Statistics ***
 [m3video]
 [m3video]  Elasped Time           : 8377 secs
 [m3video]
 [m3video]
 [m3video]  CH  | In Recv In Skip In User  Out Latency
 [m3video]  Num | FPS     FPS     Skip FPS FPS Min / Max
 [m3video]  --------------------------------------------
 [m3video]    0 |       0       0        0   0 255 /   0
 [m3video]    1 |       0       0        0   0 255 /   0
 [m3video]
 [m3video] Multi Channel Encode Average Submit Batch Size
 [m3video] Max Submit Batch Size : 24
 [m3video] IVAHD_0 Average Batch Size : 0
 [m3video] IVAHD_0 Max achieved Batch Size : 0
 [m3video]
 [m3video] Multi Channel Encode Batch break Stats
 [m3video] Total Number of Batches created: 0
 [m3video] All numbers are based off total number of Batches created
 [m3video]       Batch breaks due to batch sizeexceeding limit: 0 %
 [m3video]       Batch breaks due to ReqObj Que being empty: 0 %
 [m3video]       Batch breaks due to changed resolution class: 0 %
 [m3video]       Batch breaks due to interlace and progressivecontent mix: 0 %
 [m3video]       Batch breaks due to channel repeat: 0 %
 [m3video]       Batch breaks due to different codec: 0 %
 [m3vpss ]
 [m3vpss ]  8427682: LOAD: CPU: 4.3% HWI: 0.7%, SWI:1.0%
 [m3vpss ]
 [m3vpss ]  8427682: LOAD: TSK: SYSTEM_MSGQ         : 0.1%
 [m3vpss ]  8427682: LOAD: TSK: CAPTURE             : 0.5%
 [m3vpss ]  8427682: LOAD: TSK: NULL0               : 0.2%
 [m3vpss ]  8427682: LOAD: TSK: MISC                : 1.8%
 [m3vpss ]
 [m3video]
 [m3video]  8428183: LOAD: CPU: 1.7% HWI: 0.3%, SWI:0.5%
 [m3video]
 [m3video]  8428183: LOAD: TSK: IPC_IN_M30          : 0.2%
 [m3video]  8428183: LOAD: TSK: ENC0                : 0.4%
 [m3video]  8428184: LOAD: TSK: MISC                : 0.3%
 [m3video]
 [c6xdsp ]
 [c6xdsp ]  8428158: LOAD: CPU: 0.2% HWI: 0.0%, SWI:0.0%
 [c6xdsp ]
 [c6xdsp ]  8428158: LOAD: TSK: MISC                : 0.2%
 [c6xdsp ]


 *** Encode Bitstream Received Statistics ***

 Elased time = 8377.1 secs

 CH | Bitrate (Kbps) | FPS | Key-frame FPS | Width (max/min) | Height (max/min) | Latency (max/min)
 --------------------------------------------------------------------------------------------------

About 2), we only use some busy loop on A8 which does nothing but only causes CPU load to be 100%.

About 4), sorry, we cannot use CCS.

Plz check and reply ~ thx ~

0 Badri Narayanan over 9 years ago in reply to hb chen

TI__Guru 59700 points

You are using PG2.1 not PG3.0 as initially claimed.

Anyhow pls get the VIP capture statistics before and after the first VIp overflow. Collect stats 3 times with 1 second interval and then make A8 load 100% and cause VIP overflow and recollect the logs.

Pls share logs of top/htop after you run your busy loop

Pls share the exact code you are executing to cause 100% CPU load.

As you mentioned the number of DDR transactions from A8 doesn't increase .As you have not collect actual DDR bw data using CCS it is not possible to confirm A8 DDR bw is not increasing but it seems unlikely that A8 DDR bw is increasing.

Have you been able to recreate the issue on 814x EVM. The only thing I can think of that changes by making A8 load 100% is power consumption.If you start seeing VIP overflow after this it is very strange. If you are able to recreate on EVM then it will give additional info. I have tried out on 816x UDDVR board and I don't see any VIP overflow by making CPU load 100% on A8.

0 hb chen over 9 years ago in reply to Badri Narayanan

Expert 2640 points

Dear Badri,

Sometime we use PG2.1, sometimes we use PG3.0.

PG3.0 also has VIP Overflow issue, thus we focus on our product which used PG2.1.

Plz check attached file: 6404.VIP_overflow_Log.7z

mem_stats.log: mem_stats.out log.

test_ap.log: test_ap is used to enable capture link to null link. You can see Statistics in this file.

... Statistics ...

[Tue Apr 29 16:54:18.429 2014] [m3vpss ] VIP(PortA) detect overflow VIP_Parser_FIQ_Status:10
[Tue Apr 29 16:54:18.435 2014] [m3vpss ] 2628840: CAPTURE: Overflow detected on VIP0, Total Resets = 1

... Statistics ...

top.log: top every ten seconds.

0 Badri Narayanan over 9 years ago in reply to hb chen

TI__Guru 59700 points

Pls share the a.out source code that makes CPU load 100%. Also pls confirm yu are seeing overflow on disabling the ancillary data channel and only doing VIP0 Port A capture.

0 hb chen over 9 years ago in reply to Badri Narayanan

Expert 2640 points

Dear Badri,

a.out source code:

cat cpu_busy.c
#include<stdio.h>
int main(void)
{
      int a=0,b=0;
        while(1)
        {
              a++;
              b++;
        }
        return 0;
}

disabling the ancillary data channel>> what do you mean?

for example, what is ancillary data channel??

0 Badri Narayanan over 9 years ago in reply to hb chen

TI__Guru 59700 points

I meant disable below in VIP:

010 | 165917 165917 0 59 59 0 1280 / 1280 30 / 30 2 0 0/0 (0/0)

Are you sure running above simple loop actually causes overflow and you don't get overflow if you don't run the above for long time ? I think it may just be coincidence and have nothing to do with running the app.

If you have DVRRDK with memcpy_neon function (http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/717/p/271221/1100084.aspx#1100084).

pls run an app that does memcpy neon of say 1024 bytes from same src to dest address repeatedly. Using neon should increase A8 power consumption. I want to check if there is any correlation with power consumption.

0 Chuan-Hsiu Lee over 9 years ago in reply to Badri Narayanan

Intellectual 590 points

HI,

1. I disabled VBI channel.

2. I cannot find out memcpy_neon.S in DVRRDK_4.00.03.

But I google this keyword, I can find memcpy_neon.s in https://github.com/genesi/imx-libc-neon/blob/master/memcpy-neon.S. I used this file to rewrite cpu busy loop as below

==================================================================

#include <stdint.h>
#include <stdio.h>
#include <string.h>
#include <time.h>
#include <stdlib.h>

void *memcpy_neon(void *, const void *, size_t);
//void *memcpy_arm(void *, const void *, size_t);
int main(int argc, char *argv[])
{
unsigned char src[1024],dest[1024];
memset(src,0xAA,1024);
while(1)
{
memcpy_neon(dest,src,1024);
}

}

======================================================================

you can check my log:0181.VIP_overflow_Log_20140430.7z

C.-H. Lee

0 Brijesh Jadav over 9 years ago in reply to Chuan-Hsiu Lee

TI__Guru**** 399000 points

Hi,

What is the discrete sync mode you are using? what all are the input signals? If you are using Actvid signal and scalar enabled in the pipeline, there is a possibility of getting overflow. In any case, can you try trimming one line using VIP trimmer and see if this overflow goes away?

Rgds,

Brijesh

0 hb chen over 9 years ago in reply to Brijesh Jadav

Expert 2640 points

Dear Brijensh,

sprugz8c.pdf: 12.1.3.6 Video Capture Features -- Support both embedded sync and discrete sync.

We modify capturelink_drv.c from embedded sync to discrete sync.

captureLink_drv.c (dvr_rdk\mcfw\src_bios6\links_m3vpss\capture)

CaptureLink_drvCreateInst

#if 0 // if 1 for embedded sync
            pVipCreateArgs->videoCaptureMode =
                VPS_CAPT_VIDEO_CAPTURE_MODE_SINGLE_CH_NON_MUX_EMBEDDED_SYNC;
       #else
        pVipCreateArgs->videoCaptureMode =
           VPS_CAPT_VIDEO_CAPTURE_MODE_SINGLE_CH_NON_MUX_DISCRETE_SYNC_ACTVID_VBLK;
//       VPS_CAPT_VIDEO_CAPTURE_MODE_SINGLE_CH_NON_MUX_DISCRETE_SYNC_ACTVID_VSYNC;

       #endif

Input signal path is: Camcorder SDI (1280x720/60p) --> FPGA --> VIP Port.

Activid signal: vsync + de.

VIP overflow occurred in VPI0. We don't use scalar in VIP0.

"can you try trimming one line using VIP trimmer and see if this overflow goes away"

Sorry, we don't under what is "one line using VIP trimmer"~?!

Currently, we had disabled below in VIP:

010 | 165917 165917 0 59 59 0 1280 / 1280 30 / 30 2 0 0/0 (0/0)

But VIP overflow still occur if we let A8 usage to 100% by simple while loop (sometime less than one hour).

Another testing, we keep

[m3vpss ] 000 | 25751292 25751292 0 59 59 0 1280 / 1280 720 / 720 1 0 0/0 (0/0)
[m3vpss ] 010 | 25751293 25751293 0 59 59 0 1280 / 1280 30 / 30 1 0 0/0 (0/0)

but we don't let A8 usage to 100% (less than 5%), VIP overflow didn't occur over four days.

It seems A8 loading will affect VIP overflow.

0 Brijesh Jadav over 9 years ago in reply to hb chen

TI__Guru**** 399000 points

Hi,

Each VIP port has inline trimmer, which can trim off few lines/pixels and give out cropped output. There is an ioctl to set the enable this trimmer. I dont remember exact ioctl name, but there should be something like SET_CROP_CFG.

Instead of setting and incrementing a variable in a busy loop, can you create a cpu load by just doing while(1);

Regards,

Brijesh

0 Chuan-Hsiu Lee over 9 years ago in reply to Brijesh Jadav

Intellectual 590 points

Hi,

1. I set the VIP parser to capture 1280x2 and create a while loop in A8. The VIP overflow will not occur.

(If VIP parser captures 1280x1, the system will hang up).

2. I set the VIP parser to capture 1280x720 and create a while loop in A8, The VIP overflow will occur.

Please advise us how to avoid VIP overflow.

Thanks

0 Brijesh Jadav over 9 years ago in reply to Chuan-Hsiu Lee

TI__Guru**** 399000 points

Hi,

Can you try slightly less which is 1280x719 or 1280x715?

Rgds,

Brijesh

0 hb chen over 9 years ago in reply to Brijesh Jadav

Expert 2640 points

Dear Brijesh,

We will do this experiment.

Many thanks to your suggestion.

But could you plz tell us your suspicion for each experiment.

We have to reply to customer TI's suspicion and what experiment we are doing.

We hope each experiment can help you to find the root cause.

Thx ~

0 Brijesh Jadav over 9 years ago in reply to hb chen

TI__Guru**** 399000 points

Hi Chen,

We have seen that when vsync and DE mode is used for the discrete sync capture, VIP overflows when scalar is in the path. You dont use scalar in the path, but just wanted to check if this is the one causing overflow.

Also can you check few more things,

1, can you please make sure that you are using latest hdvpss drivers?

2, Can you please confirm that you are observing overflow for embedded and discrete sync interfaces

3, Can you print the value of the registers at the offset 0x481055d8 and 0x481055dc and see if they are set to 0xffffffff.

Regards,

Brijesh

0 hb chen over 9 years ago in reply to Brijesh Jadav

Expert 2640 points

Dear Brijesh,

1) We are using 4.0 hdvpss driver.

2) Both embedded and discrete sync have overflow.

In old testing, we test embedded sync only using iperf, not pure while loop.

Currently, we test discrete sync by pure while loop.

3) Plz check

[root@buildroot ~]# /opt/dvr_rdk/ti814x/bin/mem_rdwr.out --rd 0x481055d8 4
481055d8 48100000 55dc 55d8 0x48100000

0x481055d8: FFFFFFFF
0x481055dc: FFFFFFFF
0x481055e0: 00000000
0x481055e4: 00000000

0 Chuan-Hsiu Lee over 9 years ago in reply to Brijesh Jadav

Intellectual 590 points

Hi,

You mention then "We have seen that when vsync and DE mode is used for the discrete sync capture, VIP overflows when scalar is in the path".

If I change discrete sync mode to Vsync+Hsync, is it possible to avoid VIP overflows?

Thanks

CH. Lee

0 Brijesh Jadav over 9 years ago in reply to Chuan-Hsiu Lee

TI__Guru**** 399000 points

Hi,

It should work in hsync/vsync mode, but please note that this overflow is observed only when scalar is used in the path and this comes immediately.

In this case, scalar does not get much time to flush its internal data causing vip overflow.

Regards,

Brijesh

0 Chuan-Hsiu Lee over 9 years ago in reply to Brijesh Jadav

Intellectual 590 points

Hi ,

1. I disable scaler function in Capture Link.

2. I used SC5 in SCLR Link.

If I don't use VIP scaler, it should not occur VIP overflow in discrete sync mode (Vsync+DE or Vsync+Hsync)?

Which discrete sync mode is better to avoid VIP overflow?

Does discrete sync mode affect VIP overflow?

for(vipInstId=0; vipInstId<capturePrm.numVipInst; vipInstId++)
{
pCaptureInstPrm = &capturePrm.vipInst[vipInstId];
pCaptureInstPrm->vipInstId = SYSTEM_CAPTURE_INST_VIP0_PORTA+vipInstId;

pCaptureInstPrm->videoDecoderId = SYSTEM_DEVICE_VID_DEC_ACLVFE_DRV;
pCaptureInstPrm->inDataFormat = SYSTEM_DF_YUV422P;

pCaptureInstPrm->standard = gVcapModuleContext.videoStatus.chStatus[0].standard;

pCaptureInstPrm->numOutput = 2;

pCaptureOutPrm = &pCaptureInstPrm->outParams[0];

pCaptureOutPrm->dataFormat = SYSTEM_DF_YUV422I_YUYV;
pCaptureOutPrm->scEnable = FALSE;
pCaptureOutPrm->scOutWidth = gVcapModuleContext.videoStatus.chStatus[0].frameWidth;
pCaptureOutPrm->scOutHeight = gVcapModuleContext.videoStatus.chStatus[0].frameHeight;
pCaptureOutPrm->outQueId = 0;

pCaptureOutPrm = &pCaptureInstPrm->outParams[1];

pCaptureOutPrm->dataFormat = SYSTEM_DF_RAW_VBI;
pCaptureOutPrm->scEnable = FALSE;
pCaptureOutPrm->outQueId = 1;

}

static inline void SclrLink_CreateParams_Init(SclrLink_CreateParams *pPrm)
{

memset(pPrm, 0, sizeof(*pPrm));

pPrm->inQueParams.prevLinkId = SYSTEM_LINK_ID_INVALID;
pPrm->inQueParams.prevLinkQueId = 0;

pPrm->outQueParams.nextLink = SYSTEM_LINK_ID_INVALID;
pPrm->outScaleFactor.ratio.widthRatio.numerator = 1;
pPrm->outScaleFactor.ratio.widthRatio.denominator = 1;
pPrm->outScaleFactor.ratio.heightRatio.numerator = 1;
pPrm->outScaleFactor.ratio.heightRatio.denominator = 1;
pPrm->inputFrameRate = 30;
pPrm->outputFrameRate = 30;
pPrm->tilerEnable = FALSE;
pPrm->scaleMode = SCLR_SCALE_MODE_RATIO;
pPrm->enableLineSkipSc = FALSE;

pPrm->numBufsPerCh = SCLR_LINK_NUM_BUFS_PER_CH_DEFAULT;
pPrm->outDataFormat = SYSTEM_DF_YUV422I_YUYV;

pPrm->pathId =SCLR_LINK_SC5;

}

0 Chuan-Hsiu Lee over 9 years ago in reply to Chuan-Hsiu Lee

Intellectual 590 points

Hi,

I found another issue about frame order.

if VIP parser occurs overflow, the video frame order will be wrong.

For example,

[m3vpss ] Capture Link Lost Frame:Old Timestamp:175898,New Timestamp:175951,diff:53,Old Ptr:a8ff9c80,New Ptr:a9fcbc80,count:10404 <==VIP overflow , VIP should be reset.
[m3vpss ] Capture Link Lost Frame:Old Timestamp:176101,New Timestamp:175898,diff:-203,Old Ptr:ac364480,New Ptr:a93ee480,count:10414 <==frame order is wrong. there is old video frame
[m3vpss ] Capture Link Lost Frame:Old Timestamp:175898,New Timestamp:176134,diff:236,Old Ptr:a93ee480,New Ptr:a97e2c80,count:10415

Please advise us how to resolve this issue?

Thanks

0 hb chen over 9 years ago in reply to Brijesh Jadav

Expert 2640 points

Dear Brijesh,

We try 1280x715, but VIP overflow still occur.

Only simple while(1) is used to let A8 usage to 100%

[m3vpss ] 63912337: LOAD: CPU: 4.6% HWI: 0.8%, SWI:1.6%
[m3vpss ]
[m3vpss ] 63912337: LOAD: TSK: SYSTEM_MSGQ         : 0.1%
[m3vpss ] 63912337: LOAD: TSK: CAPTURE             : 0.5%
[m3vpss ] 63912337: LOAD: TSK: NULL0               : 0.2%
[m3vpss ] 63912337: LOAD: TSK: MISC                : 1.4%
[m3vpss ]
[m3video]
[m3video] 63912838: LOAD: CPU: 2.2% HWI: 0.4%, SWI:0.8%
[m3video]
[m3video] 63912839: LOAD: TSK: IPC_IN_M30          : 0.2%
[m3video] 63912839: LOAD: TSK: ENC0                : 0.5%
[m3video] 63912839: LOAD: TSK: MISC                : 0.3%
[m3video]
[c6xdsp ]
[c6xdsp ] 52419720: LOAD: CPU: 0.2% HWI: 0.0%, SWI:0.0%
[c6xdsp ]
[c6xdsp ] 52419720: LOAD: TSK: MISC                : 0.2%
[c6xdsp ]

[m3vpss ] *** Capture Driver Advanced Statistics ***
[m3vpss ]
[m3vpss ] VIP Parser Reset Count : 6
[m3vpss ]
[m3vpss ]      |   Total    Even     Odd Total Even   Odd Min / Max Min / Max Dropped Fid Repeat Frame Error Y/C
[m3vpss ] CH | Fields Fields Fields    FPS   FPS   FPS       Width      Height Fields      Count (Desc Error Y/C)
[m3vpss ] ------------------------------------------------------------------------------------------------------------
[m3vpss ] 000 | 3139870 3139870       0     59    59     0 1280 / 1280 715 / 715       7          0 0/0 (0/0)

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