DM8127 RDK 3.5 How can I apply OCMC memory

piao sun

Prodigy 250 points

Other Parts Discussed in Thread: AM5728

I want to malloc to malloc two buffers on OCMC memory to transfer data from DMA. How can I do that?

Is 0x4030000 physical address or virtul address?

over 9 years ago

0 piao sun over 9 years ago

Prodigy 250 points

I want to send YUV data to ethernet, 25 frames every second. So I want to copy data from DDR to OCMC and then send out .

0 Rajat Sagar over 9 years ago in reply to piao sun

TI__Expert 8780 points

Piao,

Which software stack are you using in the system?

Please refer to OCMC RAM base address in the product technical reference manual and map it as a section in your software build.

Regards

Rajat

0 piao sun over 9 years ago in reply to Rajat Sagar

Prodigy 250 points

I got it .Thank you !

0 Naveen Shetti over 9 years ago in reply to Rajat Sagar

Intellectual 690 points

Hello,

I tried to configure the OCMC sections in platform.xdc file through CCS, but when i try to allocate a global buffer in this region then the DSP image doesn't load at all, looks like its unable to access this theis OCMC region, even once I got an error unable to access corresponding OCMC address.

Please let me know how can i configure these OCMC regions properly.

As per the datasheet of DRA7XX (AM5728 EVM) :

1. OCMC_RAM1 : 0x40300000 (start base address) and max size supported is 512kB

2. OCMC_RAM2 : 0x40400000 (start base address) and max size supported is 1MB

2. OCMC_RAM3 : 0x40500000 (start base address) and max size supported is 1MB

Please find the snippet from linker.cmd file :

MEMORY
{
    EXT_CODE (RWX) : org = 0x95000000, len = 0x200000
    EXT_DATA (RW) : org = 0x95200000, len = 0x800000
    EXT_HEAP (RW) : org = 0x95a00000, len = 0x3200000
    TRACE_BUF (RW) : org = 0x9f000000, len = 0x60000
    EXC_DATA (RW) : org = 0x9f060000, len = 0x10000
    PM_DATA (RWX) : org = 0x9f070000, len = 0x20000
    SR_0 (RWX) : org = 0xbfc00000, len = 0x6400000
    L2SRAM (RWX) : org = 0x800000, len = 0x400000
    OCMC_RAM1 (RWX) : org = 0x40300000, len = 0x80000
    OCMC_RAM2 (RWX) : org = 0x40400000, len = 0x100000
    OCMC_RAM3 (RWX) : org = 0x40500000, len = 0x100000
}

Please find the snippet from platform.xdc file.

metaonly module Platform inherits xdc.platform.IPlatform {

    config ti.platforms.generic.Platform.Instance CPU =
        ti.platforms.generic.Platform.create("CPU", {
            clockRate:      1000,
            catalogName:    "ti.catalog.c6000",
            deviceName:     "Vayu",
            customMemoryMap:
           [
                ["EXT_CODE",
                     {
                        name: "EXT_CODE",
                        base: 0x95000000,
                        len: 0x00200000,
                        space: "code/data",
                        access: "RWX",
                     }
                ],
                ["EXT_DATA",
                     {
                        name: "EXT_DATA",
                        base: 0x95200000,
                        len: 0x00800000,
                        space: "data",
                        access: "RW",
                     }
                ],
                ["EXT_HEAP",
                     {
                        name: "EXT_HEAP",
                        base: 0x95A00000,
                        len: 0x03200000,
                        space: "data",
                        access: "RW",
                     }
                ],
                ["TRACE_BUF",
                     {
                        name: "TRACE_BUF",
                        base: 0x9F000000,
                        len: 0x00060000,
                        space: "data",
                        access: "RW",
                     }
                ],
                ["EXC_DATA",
                     {
                        name: "EXC_DATA",
                        base: 0x9F060000,
                        len: 0x00010000,
                        space: "data",
                        access: "RW",
                     }
                ],
                ["PM_DATA",
                     {
                        name: "PM_DATA",
                        base: 0x9F070000,
                        len: 0x00020000,
                        space: "data",
                        access: "RWX",
                     }
                ],
                ["SR_0",
                     {
                        name: "SR_0",
                        base: 0xBFC00000,
                        len: 0x6400000,
                        space: "data",
                        access: "RWX",
                     }
                ],
                ["L2SRAM",
                     {
                        name: "L2SRAM",
                        base: 0x00800000,
                        len: 0x400000,
                        space: "data",
                        access: "RWX",
                     }
                ],
                ["OCMC_RAM1",
                     {
                        name: "OCMC_RAM1",
                        base: 0x40300000,
                        len: 0x00080000,
                        space: "data",
                        access: "RWX",
                     }
                ],
                ["OCMC_RAM2",
                     {
                        name: "OCMC_RAM2",
                        base: 0x40400000,
                        len: 0x00100000,
                        space: "data",
                        access: "RWX",
                     }
                ],
                ["OCMC_RAM3",
                     {
                        name: "OCMC_RAM3",
                        base: 0x40500000,
                        len: 0x00100000,
                        space: "data",
                        access: "RWX",
                     }
                ],
           ],
          l2Mode: "0k",
          l1PMode: "32k",
          l1DMode: "32k",

    });

Please let me if I have missed out something.

Thanks,

Naveen Shetti

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DM8127 RDK 3.5 How can I apply OCMC memory