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Recover UseCase application after hang or crash

Rachit Shah
Intellectual 320 points

Hi,

We are working on Dm8127 platform and using IPNC RDK 3.5

We are looking solution to recover our usecase application from hang or crash state without doing power cycle.

Is there any way to reset all cores ( DSP, M3VPSS and M3VIDEO) and free occupied resources by usecase ?

 

Thanks,

Rachit

  • 0
    Mastermind 8020 points

    From a hardware point of view: yes.  All cores other than the cortex-A8 can be individually reset through PRCM, and nearly all peripherals and other submodules I'm familiar with also have a reset mechanism available (with exception of things like the control module, main interconnects, etc).  Making software to cope with such a partial reset and getting things up and running again might be tricky, though I'm not familiar with IPNC RDK so I can't really say much about that.  The rough outline is

    • Get the linux drivers (e.g. syslink and vpss stuff) to close or otherwise somehow get rid of all relevant state on the cortex-a8.  This is probably the trickiest part.
    • Put cores into reset.
    • Reset all modules/subsystems normally managed by drivers just closed or cores just reset.
    • Start things up again same way as you normally would at boot.
  • 0 in reply to Matthijs van Duin
    TI__Guru**** 170625 points

    Hi Rachit,

    In addition to the useful info from Matthijs, I would add that C674x DSP, M3-VIDEO and M3-VPSS local reset is described in the TRM, sections:

    2.7.21 HDVICP Power-On Reset Sequence - for M3VIDEO

    2.7.22 HDVICP Software Warm Reset Sequence - for M3VIDEO

    2.7.23 C674x DSP Power-On Reset Sequence

    2.7.24 C674x DSP Warm Reset Sequence

    2.7.25 Media Controller Power-On Reset Sequence - for M3VPSS

    2.7.26 Media Controller Warm Reset Sequence - for M3VPSS

    Best Regards,
    Pavel

  • 0 in reply to Pavel Botev
    Mastermind 8020 points

    Pavel Botev said:
    2.7.22 HDVICP Software Warm Reset Sequence - for M3VIDEO

    Eh, sorry but no.  Although M3VIDEO is also referred to as the "HDVICP Cortex-M3" in the TRM, it is one of the two cores of Media Controller (aka Ducati) subsystem and the name merely refers to the subsystem it is intended to look after.  Specifically, "M3VIDEO" is core 0 and "M3VPSS" is core 1.

    This is probably a common source of confusion and I am personally no fan of this naming, especially since from a hardware point of view, Media Controller has no special relationship with HDVICP or HDVPSS whatsoever (only with ISS).  To make things worse, the CCS target definition files call them the "RTOS" and "ISS" cores instead, inherited from the OMAP4.  While naming the two Media Controller cores after their usage may be appropriate and helpful for applications or SDKs, I think that in general they should simply be called core 0 and core 1 to reflect the fact that they have identical abilities and their application is entirely up to software.

    HDVICP itself houses a pair of ARM926E-S cores, among other things.

      

    In all cases, the actual reset of the subsystems is straightforward and unlikely to be the issue here, the hard part is having software cope with it.  This however needs to be answered by someone who is familiar with the inner workings of the IPNC RDK (which I am not).