DDR SW leveling - non converge issue

Hello,

I'm using DDR3 16-bit interface with DM8148.
It works OK with 250Mhz, but 400Mhz fails in DDR testing: reading fails sometimes - I read 0 instead of 0xa5a5, but the write is successful.

I've followed the instruction in 
http://processors.wiki.ti.com/index.php/TI814x-DDR3-Init-U-Boot_Wordwise_SWleveling
But I get each time different optimum vaslues, and the range is always very small ( 1 to 5).

This is the log of execution of the wording sw leveling utility in CCS5:

Enter 0 for DDR Controller 0 & 1 for DDR Controller 1
0
DDR START ADDR=0x80000000

Enter the Seed Read DQS Gate Ratio Value in Hex to search the RD DQS Gate Window
0x34

Enter the Seed Read DQS Ratio Value in Hex to search the RD DQS Ratio Window
0x38

Enter the Seed Write DQS Ratio Value in Hex to search the Write DQS Ratio Window
0x3
Enter the input file Name
0

*********************************************************
The Slave Ratio Search Program Values are
*********************************************************
PARAMETER MAX MIN OPTIMUM RANGE
*********************************************************
Read DQS 1d 1b 1c 2
Read DQS GATE 1a 15 17 5
Write DQS 4 2 3 2
Write DATA 7b 6 40 75
*********************************************************

===== END OF TEST =====
Enter 0 for DDR Controller 0 & 1 for DDR Controller 1
0
DDR START ADDR=0x80000000

Enter the Seed Read DQS Gate Ratio Value in Hex to search the RD DQS Gate Window
0x17

Enter the Seed Read DQS Ratio Value in Hex to search the RD DQS Ratio Window
0x1c

Enter the Seed Write DQS Ratio Value in Hex to search the Write DQS Ratio Window
0x3
Enter the input file Name
0

*********************************************************
The Slave Ratio Search Program Values are
*********************************************************
PARAMETER MAX MIN OPTIMUM RANGE
*********************************************************
Read DQS 0 3 1 fffffffd
Read DQS GATE 17 14 15 3
Write DQS 2 0 1 2
Write DATA 0 0 0 0
*********************************************************

===== END OF TEST =====


Thanks for any suggestion,

Ran