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Confusion on SATA clock

http://processors.wiki.ti.com/index.php/DM814x_AM387x_PSP_04.01.00.07_Release_Notes

 

States in the known issues…

“The internal 20MHz clock source for SATA PLL has some issues. This is being used as the default clock for SATA. Hence we were seeing interface fatal errors. This is a hardware issue. The workaround is to either use the 100MHz external clock from PCIe or find a 20mhz clock source on the board and feed into XI/CLKIN. The later option is transparent and does not require code change but the former requires code change and the PCIe PLL has to be programmed for this.”

 

The closest thing in the errata is Advisory 2.1.27 that says it only matters if we use VOUT0.  Is there a problem with SATA and the 20MHz clock if we only use HDMI for output?

  • Eric,

    Eric Bryan said:

    http://processors.wiki.ti.com/index.php/DM814x_AM387x_PSP_04.01.00.07_Release_Notes

     

    States in the known issues…

    “The internal 20MHz clock source for SATA PLL has some issues. This is being used as the default clock for SATA. Hence we were seeing interface fatal errors. This is a hardware issue. The workaround is to either use the 100MHz external clock from PCIe or find a 20mhz clock source on the board and feed into XI/CLKIN. The later option is transparent and does not require code change but the former requires code change and the PCIe PLL has to be programmed for this.”

    This PSP 04.01.00.07 release is obsoleted.

    The latest DM814x EZSDK 5.05.02.00 comes with PSP04.04.00.01, where this SATA issue is fixed. We have no SATA related issue in the "Known Issues" section:

    http://processors.wiki.ti.com/index.php/TI81XX_PSP_04.04.00.01_Release_Notes#Known_Issues

    The newest PSP is 04.04.00.02 where we have some know issues, but not the one you have ask for:

    http://processors.wiki.ti.com/index.php/TI81XX_PSP_04.04.00.02_Release_Notes#SATA_2

    Regards,
    Pavel

  • Pavel Botev said:
    The latest DM814x EZSDK 5.05.02.00 comes with PSP04.04.00.01, where this SATA issue is fixed. We have no SATA related issue in the "Known Issues" section.

    In what sense was that issue "fixed", other than by omitting it from the "Known Issues" section?  The kernel from that PSP still reconfigures the SATA PLL to use the 100 MHz PCIe clock as source instead of the 20 MHz devosc (which also means that kernel won't work on boards without the 100 MHz PCIe reference clock).  Same goes for the latest kernel.

  • I should also add that this reconfiguration of the SATA PLL has been reported to destabilize ethernet (whose clocks are also supplied by the SATA PLL) for some people.

  • I need to know if using the 20MHz clock is adequate to run the SATA if I am not using VOUT0 as the errata says or if I have to provide other electronics to make this reliable.  We do not have any of the other hardware on our board to use the other workarounds for this issue so I'm looking at having to respin the PCB.

  • Thanks!  We are using Ethernet so that would be an issue as well.

  • Eric,

    In DM814x datasheet is stated that we must use 100MHz clock for SATA:

    8.18.2 SATA Interface Design Guidelines
    A standard 100-MHz differential clock source must be used for SATA operation (for details, see Section 7.4.2, SERDES_CLKN/P Input Clock).

    Also in the below wiki pages:

    http://processors.wiki.ti.com/index.php/DM814x_Hardware_Design_Guide#Designing_the_Clocking_Subsystem

    A 100-MHz differential clock input is required for SATA and PCIe.

    http://processors.wiki.ti.com/index.php/DM816x_AM389x_PCIe_Clocking_Schemes

    See also the below e2e thread:

    http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/716/p/282655/985761.aspx#985761

    Regards,
    Pavel

  • Pavel Botev said:
    8.18.2 SATA Interface Design Guidelines
    A standard 100-MHz differential clock source must be used for SATA operation (for details, see Section 7.4.2, SERDES_CLKN/P Input Clock).

    The documentation often contradicts this though, for example the referenced section 7.4.2. says the serdes clock is only required for PCIe and is an optional clock source for SATA.  The TRM also presents both choices of clock source as valid for SATA, with the 20 MHz devosc being the default.

    In any case, if the 100 MHz serdes clock is now required that means the problems with using devosc as clock source for the SATA PLL have not been fixed but that this choice has been defeatured.  That's not the same thing.

  • Matthijs,

    Matthijs van Duin said:
    In any case, if the 100 MHz serdes clock is now required that means the problems with using devosc as clock source for the SATA PLL have not been fixed but that this choice has been defeatured.  That's not the same thing.

    You are right at that point. When I state that this is fixed, I mean 100MHz patch was developed by the PSP team. Sorry for the confusion.

    Regards,
    Pavel

  • I would suggest it be added to the Errata sheet as well.  Rather hard to notice changes like this in the larger documents.