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RMII on emac1 - bring-up in u-boot

Guru 20755 points

Hello,

In psp porting guide http://processors.wiki.ti.com/index.php/TI81xx_PSP_Porting_Guide it is said:

CPSW EMAC 1 bringup in uboot

Uboot currently supports only CPSW EMAC 0, to bring up EMAC 1 following steps needs to be ported.

In evm file: Add pinmux for CPSW EMAC 1 in cpsw_pad_config() 

Interchange the cpsw_slaves platform data.

In driver: make cpsw_get_slave_port to return CPSW port 2 offset ie "2"

 
I have some questions on the above guideline:
1. Is it for using of both emac1 and emac 0 or only emac 1 use ?

These are the changes as I did according to the above guideliness:
1. "Interchange the cpsw_slaves platform data.":

static inline u32 cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num)
{

  return 2;

}

2. "Interchange the cpsw_slaves platform data."

in board/ti/ti8148/evm.c I did as following:

from old:
if (PG1_0 != get_cpu_rev()) {
#ifdef CONFIG_MACH_TI814XDVR
cpsw_slaves[0].phy_id = 1;
cpsw_slaves[1].phy_id = 0;
#else
cpsw_slaves[0].phy_id = 0;
cpsw_slaves[1].phy_id = 1;
#endif

to (new) :

if (PG1_0 != get_cpu_rev()) {
#ifdef CONFIG_MACH_TI814XDVR
cpsw_slaves[0].phy_id = 1;
cpsw_slaves[1].phy_id = 0;
#else
cpsw_slaves[0].phy_id = 1;
cpsw_slaves[1].phy_id = 0;
#endif

Another thing, Does the Linux kernel boot need other modifications for emac1 usage ?

I also wander why emac1 is not enabled together with emac 0 by default in u-boot....

Thanks!!
Ran

  • Ran,

    Ran S. said:
    1. Is it for using of both emac1 and emac 0 or only emac 1 use ?

    Based on the below e2e thread, I can state that it is for emac1 use only (in u-boot).

    http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/717/t/237498.aspx

    In U-boot you cannot use both the EMACs simultaneously, you change the interface by changing the base address.
    In kernel both the interface is brought up as two individual interface which can be connected to separate network and can be used.

    See also the below e2e discussions:

    http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/716/p/335796/1171902.aspx#1171902

    http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/716/t/297225.aspx

    http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/716/p/211761/864111.aspx#864111

    Regards,
    Pavel

  • Hi Pavel,

    For setting RMII

    I use the instructions in 

    http://processors.wiki.ti.com/index.php/TI81xx_PSP_Porting_Guide#CPSW_RMII_Phy

    It says:

    • In U-Boot Phy ID should be set in board/ti/<SOC>/evm.c:struct cpsw_slave_data cpsw_slaves[]

    What value should be given to phy id ( emac 1) ?

    • Program GMII_SEL in control module with 0x5 for RMII Interface

    Why do we need to set both port 0 & 1 to RMII ? ( We have in port 0 RGMII, and in port 1 RMII .)

    Are the instruction in the above link suffecient or do I also need to setup clock as in link

    http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/716/t/220287.aspx ?

    Thanks,

    Ran

  • Ran,

    This is how I enable the EMAC1 in EZSDK5.05.00.02 u-boot-2010.06-psp04.04.00.01 (RGMII mode):

     In evm file: Add pinmux for CPSW EMAC 1 in cpsw_pad_config() - this is already done in the latter versions of the u-boot, no need for further actions for EMAC1 RGMII pins

    In evm file: Interchange the cpsw_slaves platform data

    u-boot-2010.06-psp04.04.00.01/board/ti/ti8148/evm.c

    /*static struct cpsw_slave_data cpsw_slaves[] = {
        {
            .slave_reg_ofs  = 0x50,
            .sliver_reg_ofs = 0x700,
            .phy_id         = 1,
        },
        {
            .slave_reg_ofs  = 0x90,
            .sliver_reg_ofs = 0x740,
            .phy_id         = 0,
        },
    };*/

    static struct cpsw_slave_data cpsw_slaves[] = {
        {
            .slave_reg_ofs  = 0x90,
            .sliver_reg_ofs = 0x740,
            .phy_id         = 0,
        },
        {
            .slave_reg_ofs  = 0x50,
            .sliver_reg_ofs = 0x700,
            .phy_id         = 1,
        },
    };

    .............

    if (PG1_0 != get_cpu_rev()) {
            //cpsw_slaves[0].phy_id = 0;
            //cpsw_slaves[1].phy_id = 1;
            cpsw_slaves[0].phy_id = 1;
            cpsw_slaves[1].phy_id = 0;
        }

    In driver: make cpsw_get_slave_port to return CPSW port 2 offset ie "2"

    u-boot-2010.06-psp04.04.00.01/drivers/net/cpsw.c

    static inline u32 cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num)
    {
        /*if (priv->host_port == 0)
            return slave_num + 1;
        else
            return slave_num;*/
        return 2;
    }

    Regards,
    Pavel

  • Ran,

    Ran S. said:
    What value should be given to phy id ( emac 1) ?

    It depends on the PHY integration. See the below e2e threads:

    http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/716/p/241779/847170.aspx#847170

    http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/716/p/209865/856255.aspx#856255

    http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/717/p/210000/744985.aspx#744985

    http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/716/p/353786/1241768.aspx#1241768

    Ran S. said:
    Why do we need to set both port 0 & 1 to RMII ? ( We have in port 0 RGMII, and in port 1 RMII .)

    You can use one port as RGMII and other port as RMII, see the below e2e threads:

    http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/716/t/247403.aspx

    http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/716/t/154601.aspx

    http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/716/t/159889.aspx

    Regards,
    Pavel

  • Hi Pavel,

    I have configured u-boot as in your description, but I still have problems with emac #1:

    list of changes

    ============

    1.  GMII_SEL = 0x106

       __raw_writel(0x106,GMII_SEL);

    2. 

    static struct cpsw_slave_data cpsw_slaves[] = {
    //exchanged
    {
    .slave_reg_ofs = 0x90,
    .sliver_reg_ofs = 0x740,
    .phy_id = 0,
    },
    {
    .slave_reg_ofs = 0x50,
    .sliver_reg_ofs = 0x700,
    .phy_id = 1,
    },
    };

    3. 

    if (PG1_0 != get_cpu_rev()) {
    #ifdef CONFIG_MACH_TI814XDVR
    cpsw_slaves[0].phy_id = 1;
    cpsw_slaves[1].phy_id = 0;
    #else
    //exchanged
    cpsw_slaves[0].phy_id = 1;
    cpsw_slaves[1].phy_id = 0;
    #endif

    static inline u32 cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num)
    {

    return 2;

    }

    4. pinmux of emac1 is used (attached).2330.pinmux.h

    Why Does it says "port 0", while I'm using port 1?
    Does anyone have any suggestions how to continue from here ?

    Ran

  • Hi Pavel,

    Is there a methodology to bring up etherent with DM814x ? 

    I have managed to get link using the changes described in previous post, but I don't ping is failed.
    Is there some way to check why is fails ?
    Thanks

    Ran

  • Ran,

    Ran S. said:

    I see that there is link (led are on), but on doing ping I get

    link up on port 0, speed 100, full duplex

    ping failed.

    Could you please provide me full console output log of the above.

    Ran S. said:
    Why Does it says "port 0", while I'm using port 1?

    The same is on my side, I am using EMAC1 on the DM814x EVM (J27), and it reports "port 0".

    Ran S. said:
    Does anyone have any suggestions how to continue from here ?

    Can you also try with GMII_SEL[9] RGMII1_EN  = 0x1, does it make any difference?


    Regards,
    Pavel

  • Hi Pavel,

    Thanks very much for assistance !!

    I get the following results when doing ping on emac #1 RMII:

    TI8148_EVM#ping 10.0.0.1
    failed to read bmcr
    Using cpsw device
    ping failed; host 10.0.0.1 is not alive
    TI8148_EVM#

    I also don't see led light on the ethernet connection (but I do see the led on the other side (PC) right after u-boot starts). How can it be that there is led activity in the PC, while there is no led activity in the target ethernet ?

    I also tried to change GMII_SEL bit 9 (0x306), but get the same results.

    I really don't know how to continue from this point... Is there a loopback test maybe for RMII emac 1 ? 

    Thanks for any idea,

    Ran

  • Hi,

    My pinmux for emac #1 is as following, do you think something is missing with pinmux ?

    MUX_VAL(PINCNTL157, (IEN | IPD | FCN4 )) /* EMAC[1]_RMRXER_MUX1 */\
    MUX_VAL(PINCNTL158, (IEN | IPU | FCN4 )) /* EMAC[1]_RMRXD[1]_MUX1 */\
    MUX_VAL(PINCNTL159, (IEN | IPU | FCN4 )) /* EMAC[1]_RMRXD[0]_MUX1 */\
    MUX_VAL(PINCNTL160, (IEN | IPD | FCN4 )) /* EMAC[1]_RMCRSDV_MUX1 */\
    MUX_VAL(PINCNTL161, (IEN | IPD | FCN4 )) /* EMAC[1]_RMTXD[0]_MUX1 */\
    MUX_VAL(PINCNTL162, (IEN | IPD | FCN4 )) /* EMAC[1]_RMTXD[1]_MUX1 */\
    MUX_VAL(PINCNTL163, (IEN | IPD | FCN4 )) /* EMAC[1]_RMTXEN_MUX1 */\

    Thanks

    Ran

  • Ran,

    Ran S. said:
    MUX_VAL(PINCNTL161, (IEN | IPD | FCN4 )) /* EMAC[1]_RMTXD[0]_MUX1 */\
    MUX_VAL(PINCNTL162, (IEN | IPD | FCN4 )) /* EMAC[1]_RMTXD[1]_MUX1 */\
    MUX_VAL(PINCNTL163, (IEN | IPD | FCN4 )) /* EMAC[1]_RMTXEN_MUX1 */\

    Can you try make these 3 pins outputs?

    Also, have you configured the EMAC_RMREFCLK/PINCNTL232 pin?

    Can you provide me the exact values in the PINCNTLx registers that are involved in the EMAC1 RMII configuration?

    Regards,
    Pavel

  • Ran,

    Have you tried with EMAC1 RGMII, does it work?

    Ran S. said:
    TI8148_EVM#ping 10.0.0.1

    Is this your host machine (desktop PC) ip addr?

    Ran S. said:
    failed to read bmcr

    See if the below e2e threads will be in help:

    http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/716/t/209865.aspx

    http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/716/p/211761/754554.aspx#754554

    http://e2e.ti.com/support/embedded/linux/f/354/t/238479.aspx

    Regards,
    Pavel

  • Hi Pavel,

    >"Is this your host machine (desktop PC) ip addr?"

    Yes! It is. 

     I will walk over the other suggestions in your post, and get back to you soon.

    Thanks,
    Ran

  • Hi Pavel,

    Thanks very much for the help!!

    > Can you try make these 3 pins outputs? 
    How can I do this ? I see that the pinmux lines you have copied are the same as my previous post.
    >Also, have you configured the EMAC_RMREFCLK/PINCNTL232 pin?
    Yes
    >Can you provide me the exact values in the PINCNTLx registers that are involved in the EMAC1 RMII configuration?

    MUX_VAL(PINCNTL157, (IEN | IPD | FCN4 )) /* EMAC[1]_RMRXER_MUX1 */\
    MUX_VAL(PINCNTL158, (IEN | IPU | FCN4 )) /* EMAC[1]_RMRXD[1]_MUX1 */\
    MUX_VAL(PINCNTL159, (IEN | IPU | FCN4 )) /* EMAC[1]_RMRXD[0]_MUX1 */\
    MUX_VAL(PINCNTL160, (IEN | IPD | FCN4 )) /* EMAC[1]_RMCRSDV_MUX1 */\
    MUX_VAL(PINCNTL161, (IEN | IPD | FCN4 )) /* EMAC[1]_RMTXD[0]_MUX1 */\
    MUX_VAL(PINCNTL162, (IEN | IPD | FCN4 )) /* EMAC[1]_RMTXD[1]_MUX1 */\
    MUX_VAL(PINCNTL163, (IEN | IPD | FCN4 )) /* EMAC[1]_RMTXEN_MUX1 */\
    MUX_VAL(PINCNTL232, (IEN | IPD | FCN1 )) /* EMAC_RMREFCLK */\

     

    the complete pinmux is attached

    3247.pinmux_new.txt
    #ifndef _PINMUX_H_
    #define _PINMUX_H_
    
    /*
     * DISABLED - Disabled
     * FCN1 - Mux Fcn 1
     * FCN2 - Mux Fcn 2
     * FCN3 - Mux Fcn 3
     * FCN4 - Mux Fcn 4
     * FCN5 - Mux Fcn 5
     * FCN6 - Mux Fcn 6
     * FCN7 - Mux Fcn 7
     * FCN8 - Mux Fcn 8
     * IDIS - Receiver disabled
     * IEN - Receiver enabled
     * IPD - Internal pull-down
     * IPU - Internal pull-up
     * DIS - Internal pull disabled
     */
    
    #define MUX_EVM() \
    
    /* Design Status: NO ERRORS */
    
    MUX_VAL(PINCNTL1, (IEN | IPU | DISABLED )) /* safe_mode */\
    MUX_VAL(PINCNTL2, (IEN | IPU | FCN8 )) /* GP0[0] */\
    MUX_VAL(PINCNTL3, (IEN | IPU | DISABLED )) /* safe_mode */\
    MUX_VAL(PINCNTL4, (IEN | IPU | DISABLED )) /* safe_mode */\
    MUX_VAL(PINCNTL5, (IEN | IPU | DISABLED )) /* safe_mode */\
    MUX_VAL(PINCNTL6, (IEN | IPU | DISABLED )) /* safe_mode */\
    MUX_VAL(PINCNTL7, (IEN | IPU | FCN2 )) /* SPI[1]_SCS[1] */\
    MUX_VAL(PINCNTL8, (IEN | IPU | FCN8 )) /* GP0[1] */\
    MUX_VAL(PINCNTL9, (IEN | IPU | FCN8 )) /* GP0[2] */\
    MUX_VAL(PINCNTL10, (IEN | IPU | FCN8 )) /* GP0[3] */\
    MUX_VAL(PINCNTL11, (IEN | IPU | FCN8 )) /* GP0[4] */\
    MUX_VAL(PINCNTL12, (IEN | IPU | FCN8 )) /* GP0[5] */\
    MUX_VAL(PINCNTL13, (IEN | IPU | FCN8 )) /* GP0[6] */\
    MUX_VAL(PINCNTL14, (IEN | IPD | FCN4 )) /* MCA[3]_AHCLKX */\
    MUX_VAL(PINCNTL15, (IEN | IPD | FCN8 )) /* GP0[8] */\
    MUX_VAL(PINCNTL16, (IEN | IPD | FCN3 )) /* MCA[2]_AHCLKX */\
    MUX_VAL(PINCNTL17, (IEN | IPD | DISABLED )) /* safe_mode */\
    MUX_VAL(PINCNTL18, (IEN | IPD | DISABLED )) /* safe_mode */\
    MUX_VAL(PINCNTL19, (IEN | IPD | DISABLED )) /* safe_mode */\
    MUX_VAL(PINCNTL20, (IEN | IPD | DISABLED )) /* safe_mode */\
    MUX_VAL(PINCNTL21, (IEN | IPD | DISABLED )) /* safe_mode */\
    MUX_VAL(PINCNTL22, (IEN | IPU | FCN6 )) /* I2C[3]_SCL_MUX0 */\
    MUX_VAL(PINCNTL23, (IEN | IPU | FCN6 )) /* I2C[3]_SDA_MUX0 */\
    MUX_VAL(PINCNTL24, (IEN | IPD | DISABLED )) /* safe_mode */\
    MUX_VAL(PINCNTL25, (IEN | IPD | DISABLED )) /* safe_mode */\
    MUX_VAL(PINCNTL26, (IEN | IPD | DISABLED )) /* safe_mode */\
    MUX_VAL(PINCNTL27, (IEN | IPD | FCN2 )) /* MCB_DR */\
    MUX_VAL(PINCNTL28, (IEN | IPD | FCN2 )) /* MCB_DX */\
    MUX_VAL(PINCNTL29, (IEN | IPD | FCN2 )) /* MCB_FSX */\
    MUX_VAL(PINCNTL30, (IEN | IPD | FCN2 )) /* MCB_CLKX */\
    MUX_VAL(PINCNTL31, (IEN | IPD | DISABLED )) /* safe_mode */\
    MUX_VAL(PINCNTL32, (IEN | IPD | DISABLED )) /* safe_mode */\
    MUX_VAL(PINCNTL33, (IEN | IPD | DISABLED )) /* safe_mode */\
    MUX_VAL(PINCNTL34, (IEN | IPD | DISABLED )) /* safe_mode */\
    MUX_VAL(PINCNTL35, (IEN | IPU | DISABLED )) /* safe_mode */\
    MUX_VAL(PINCNTL36, (IEN | IPU | DISABLED )) /* safe_mode */\
    MUX_VAL(PINCNTL37, (IEN | IPD | FCN2 )) /* MCB_FSR_MUX0 */\
    MUX_VAL(PINCNTL38, (IEN | IPD | FCN2 )) /* MCB_CLKR_MUX0 */\
    MUX_VAL(PINCNTL39, (IEN | IPU | FCN1 )) /* MCA[2]_ACLKX */\
    MUX_VAL(PINCNTL40, (IEN | IPU | FCN1 )) /* MCA[2]_AFSX */\
    MUX_VAL(PINCNTL41, (IEN | IPU | FCN1 )) /* MCA[2]_AXR[0] */\
    MUX_VAL(PINCNTL42, (IEN | IPU | FCN1 )) /* MCA[2]_AXR[1] */\
    MUX_VAL(PINCNTL43, (IEN | IPD | FCN1 )) /* MCA[2]_AXR[2] */\
    MUX_VAL(PINCNTL44, (IEN | IPD | FCN1 )) /* MCA[2]_AXR[3] */\
    MUX_VAL(PINCNTL45, (IEN | IPD | FCN1 )) /* MCA[3]_ACLKX */\
    MUX_VAL(PINCNTL46, (IEN | IPD | FCN1 )) /* MCA[3]_AFSX */\
    MUX_VAL(PINCNTL47, (IEN | IPD | FCN1 )) /* MCA[3]_AXR[0] */\
    MUX_VAL(PINCNTL48, (IEN | IPD | FCN1 )) /* MCA[3]_AXR[1] */\
    MUX_VAL(PINCNTL49, (IEN | IPD | FCN1 )) /* MCA[3]_AXR[2] */\
    MUX_VAL(PINCNTL50, (IEN | IPD | FCN1 )) /* MCA[3]_AXR[3] */\
    MUX_VAL(PINCNTL51, (IEN | IPD | FCN8 )) /* GP0[21]_MUX1 */\
    MUX_VAL(PINCNTL52, (IEN | IPD | FCN8 )) /* GP0[22]_MUX1 */\
    MUX_VAL(PINCNTL53, (IEN | IPD | FCN8 )) /* GP0[23]_MUX1 */\
    MUX_VAL(PINCNTL54, (IEN | IPD | FCN8 )) /* GP0[24]_MUX1 */\
    MUX_VAL(PINCNTL55, (IEN | IPD | FCN8 )) /* GP0[25]_MUX1 */\
    MUX_VAL(PINCNTL56, (IEN | IPD | FCN8 )) /* GP0[26]_MUX1 */\
    MUX_VAL(PINCNTL57, (IEN | IPD | FCN8 )) /* GP0[27]_MUX1 */\
    MUX_VAL(PINCNTL58, (IEN | IPD | FCN8 )) /* GP0[28]_MUX1 */\
    MUX_VAL(PINCNTL59, (IEN | IPD | FCN4 )) /* UART2_RXD_MUX1 */\
    MUX_VAL(PINCNTL60, (IEN | IPD | FCN8 )) /* GP0[30] */\
    MUX_VAL(PINCNTL61, (IEN | IPD | FCN4 )) /* UART2_TXD_MUX1 */\
    MUX_VAL(PINCNTL62, (IEN | IPD | FCN8 )) /* GP1[7]_MUX1 */\
    MUX_VAL(PINCNTL63, (IEN | IPU | FCN8 )) /* GP1[8]_MUX1 */\
    MUX_VAL(PINCNTL64, (IEN | IPD | FCN8 )) /* GP1[9]_MUX1 */\
    MUX_VAL(PINCNTL65, (IEN | IPU | FCN8 )) /* GP1[10]_MUX1 */\
    MUX_VAL(PINCNTL68, (IEN | IPU | FCN8 )) /* GP1[0] */\
    MUX_VAL(PINCNTL69, (IEN | IPU | FCN8 )) /* GP1[1] */\
    MUX_VAL(PINCNTL70, (IEN | IPU | FCN1 )) /* UART0_RXD */\
    MUX_VAL(PINCNTL71, (IEN | IPU | FCN1 )) /* UART0_TXD */\
    MUX_VAL(PINCNTL72, (IEN | IPU | FCN2 )) /* UART4_RXD_MUX3 */\
    MUX_VAL(PINCNTL73, (IEN | IPU | FCN2 )) /* UART4_TXD_MUX3 */\
    MUX_VAL(PINCNTL74, (IEN | IPU | FCN2 )) /* UART3_RXD_MUX0 */\
    MUX_VAL(PINCNTL75, (IEN | IPU | FCN2 )) /* UART3_TXD_MUX0 */\
    MUX_VAL(PINCNTL76, (IEN | IPU | FCN3 )) /* UART1_TXD_MUX0 */\
    MUX_VAL(PINCNTL77, (IEN | IPU | FCN3 )) /* UART1_RXD_MUX0 */\
    MUX_VAL(PINCNTL78, (IEN | IPU | FCN1 )) /* I2C[1]_SCL */\
    MUX_VAL(PINCNTL79, (IEN | IPU | FCN1 )) /* I2C[1]_SDA */\
    MUX_VAL(PINCNTL80, (IEN | IPU | FCN8 )) /* GP1[6] */\
    MUX_VAL(PINCNTL81, (IEN | IPU | FCN1 )) /* SPI[0]_SCS[0] */\
    MUX_VAL(PINCNTL82, (IEN | IPU | FCN1 )) /* SPI[0]_SCLK */\
    MUX_VAL(PINCNTL83, (IEN | IPU | FCN1 )) /* SPI[0]_D[1] */\
    MUX_VAL(PINCNTL84, (IEN | IPU | FCN1 )) /* SPI[0]_D[0] */\
    MUX_VAL(PINCNTL85, (IEN | IPU | FCN8 )) /* GP1[16]_MUX1 */\
    MUX_VAL(PINCNTL86, (IEN | IPU | FCN1 )) /* SPI[1]_SCLK */\
    MUX_VAL(PINCNTL87, (IEN | IPU | FCN1 )) /* SPI[1]_D[1] */\
    MUX_VAL(PINCNTL88, (IEN | IPU | FCN1 )) /* SPI[1]_D[0] */\
    MUX_VAL(PINCNTL89, (IEN | DIS | FCN1 )) /* GPMC_D[0] */\
    MUX_VAL(PINCNTL90, (IEN | DIS | FCN1 )) /* GPMC_D[1] */\
    MUX_VAL(PINCNTL91, (IEN | DIS | FCN1 )) /* GPMC_D[2] */\
    MUX_VAL(PINCNTL92, (IEN | DIS | FCN1 )) /* GPMC_D[3] */\
    MUX_VAL(PINCNTL93, (IEN | DIS | FCN1 )) /* GPMC_D[4] */\
    MUX_VAL(PINCNTL94, (IEN | DIS | FCN1 )) /* GPMC_D[5] */\
    MUX_VAL(PINCNTL95, (IEN | DIS | FCN1 )) /* GPMC_D[6] */\
    MUX_VAL(PINCNTL96, (IEN | DIS | FCN1 )) /* GPMC_D[7] */\
    MUX_VAL(PINCNTL97, (IEN | DIS | FCN1 )) /* GPMC_D[8] */\
    MUX_VAL(PINCNTL98, (IEN | DIS | FCN1 )) /* GPMC_D[9] */\
    MUX_VAL(PINCNTL99, (IEN | DIS | FCN1 )) /* GPMC_D[10] */\
    MUX_VAL(PINCNTL100, (IEN | DIS | FCN1 )) /* GPMC_D[11] */\
    MUX_VAL(PINCNTL101, (IEN | DIS | FCN1 )) /* GPMC_D[12] */\
    MUX_VAL(PINCNTL102, (IEN | DIS | FCN1 )) /* GPMC_D[13] */\
    MUX_VAL(PINCNTL103, (IEN | DIS | FCN1 )) /* GPMC_D[14] */\
    MUX_VAL(PINCNTL104, (IEN | DIS | FCN1 )) /* GPMC_D[15] */\
    MUX_VAL(PINCNTL105, (IEN | IPD | FCN1 )) /* GPMC_A[16] */\
    MUX_VAL(PINCNTL106, (IEN | IPD | FCN1 )) /* GPMC_A[17] */\
    MUX_VAL(PINCNTL107, (IEN | IPD | FCN1 )) /* GPMC_A[18] */\
    MUX_VAL(PINCNTL108, (IEN | IPD | FCN1 )) /* GPMC_A[19] */\
    MUX_VAL(PINCNTL109, (IEN | IPU | FCN3 )) /* SPI[2]_SCS[1] */\
    MUX_VAL(PINCNTL110, (IEN | IPD | FCN3 )) /* SPI[2]_D[0]_MUX0 */\
    MUX_VAL(PINCNTL111, (IEN | IPU | FCN3 )) /* SPI[2]_D[1]_MUX0 */\
    MUX_VAL(PINCNTL112, (IEN | IPD | FCN3 )) /* SPI[2]_SCLK_MUX0 */\
    MUX_VAL(PINCNTL113, (IEN | IPU | FCN8 )) /* GP1[19] */\
    MUX_VAL(PINCNTL114, (IEN | IPU | FCN8 )) /* GP1[20] */\
    MUX_VAL(PINCNTL115, (IEN | IPU | FCN8 )) /* GP1[21] */\
    MUX_VAL(PINCNTL116, (IEN | IPU | FCN8 )) /* GP1[22] */\
    MUX_VAL(PINCNTL117, (IEN | IPU | FCN2 )) /* GPMC_A[1]_MUX1 */\
    MUX_VAL(PINCNTL118, (IEN | IPU | FCN2 )) /* GPMC_A[2]_MUX1 */\
    MUX_VAL(PINCNTL119, (IEN | IPU | FCN2 )) /* GPMC_A[3]_MUX1 */\
    MUX_VAL(PINCNTL120, (IEN | IPU | FCN2 )) /* GPMC_A[4]_MUX1 */\
    MUX_VAL(PINCNTL121, (IEN | IPU | FCN8 )) /* GP1[15]_MUX1 */\
    MUX_VAL(PINCNTL122, (IEN | IPU | FCN1 )) /* GPMC_CS[0] */\
    MUX_VAL(PINCNTL123, (IEN | IPU | FCN1 )) /* GPMC_CS[1] */\
    MUX_VAL(PINCNTL124, (IEN | IPU | FCN1 )) /* GPMC_CS[2] */\
    MUX_VAL(PINCNTL125, (IEN | IPU | FCN3 )) /* SPI[2]_SCS[0] */\
    MUX_VAL(PINCNTL126, (IEN | IPU | DISABLED )) /* safe_mode */\
    MUX_VAL(PINCNTL127, (IEN | IPU | FCN1 )) /* GPMC_CLK */\
    MUX_VAL(PINCNTL128, (IEN | IPU | FCN1 )) /* GPMC_ADV_ALE */\
    MUX_VAL(PINCNTL129, (IEN | IPU | FCN1 )) /* GPMC_OE_RE */\
    MUX_VAL(PINCNTL130, (IEN | IPU | FCN1 )) /* GPMC_WE */\
    MUX_VAL(PINCNTL131, (IEN | IPD | FCN1 )) /* GPMC_BE[0]_CLE */\
    MUX_VAL(PINCNTL132, (IEN | IPD | FCN1 )) /* GPMC_BE[1] */\
    MUX_VAL(PINCNTL133, (IEN | IPU | FCN1 )) /* GPMC_WAIT[0] */\
    MUX_VAL(PINCNTL134, (IEN | IPD | FCN6 )) /* CLKOUT0 */\
    MUX_VAL(PINCNTL135, (IEN | IPU | FCN8 )) /* GP2[0] */\
    MUX_VAL(PINCNTL136, (IEN | IPU | FCN8 )) /* GP2[1] */\
    MUX_VAL(PINCNTL137, (IEN | IPD | FCN8 )) /* GP2[2]_MUX1 */\
    MUX_VAL(PINCNTL138, (IEN | IPU | FCN8 )) /* GP2[3] */\
    MUX_VAL(PINCNTL139, (IEN | IPU | FCN8 )) /* GP2[4] */\
    MUX_VAL(PINCNTL140, (IEN | IPD | FCN8 )) /* GP1[11]_MUX1 */\
    MUX_VAL(PINCNTL141, (IEN | IPD | FCN8 )) /* GP1[12]_MUX1 */\
    MUX_VAL(PINCNTL142, (IEN | IPD | FCN8 )) /* GP2[7] */\
    MUX_VAL(PINCNTL143, (IEN | IPD | FCN8 )) /* GP2[8] */\
    MUX_VAL(PINCNTL144, (IEN | IPD | FCN8 )) /* GP2[9] */\
    MUX_VAL(PINCNTL145, (IEN | IPD | FCN8 )) /* GP2[10] */\
    MUX_VAL(PINCNTL146, (IEN | IPD | FCN8 )) /* GP2[11] */\
    MUX_VAL(PINCNTL147, (IEN | IPD | FCN8 )) /* GP2[12] */\
    MUX_VAL(PINCNTL148, (IEN | IPD | FCN8 )) /* GP2[13] */\
    MUX_VAL(PINCNTL149, (IEN | IPD | FCN8 )) /* GP2[14] */\
    MUX_VAL(PINCNTL150, (IEN | IPD | FCN8 )) /* GP2[15] */\
    MUX_VAL(PINCNTL151, (IEN | IPD | FCN8 )) /* GP2[16] */\
    MUX_VAL(PINCNTL152, (IEN | IPD | FCN8 )) /* GP2[17] */\
    MUX_VAL(PINCNTL153, (IEN | IPD | FCN8 )) /* GP2[18] */\
    MUX_VAL(PINCNTL154, (IEN | IPD | FCN8 )) /* GP2[19] */\
    MUX_VAL(PINCNTL155, (IEN | IPD | FCN8 )) /* GP2[20] */\
    MUX_VAL(PINCNTL156, (IEN | IPU | FCN8 )) /* GP0[10]_MUX0 */\
    MUX_VAL(PINCNTL157, (IEN | IPD | FCN4 )) /* EMAC[1]_RMRXER_MUX1 */\
    MUX_VAL(PINCNTL158, (IEN | IPU | FCN4 )) /* EMAC[1]_RMRXD[1]_MUX1 */\
    MUX_VAL(PINCNTL159, (IEN | IPU | FCN4 )) /* EMAC[1]_RMRXD[0]_MUX1 */\
    MUX_VAL(PINCNTL160, (IEN | IPD | FCN4 )) /* EMAC[1]_RMCRSDV_MUX1 */\
    MUX_VAL(PINCNTL161, (IEN | IPD | FCN4 )) /* EMAC[1]_RMTXD[0]_MUX1 */\
    MUX_VAL(PINCNTL162, (IEN | IPD | FCN4 )) /* EMAC[1]_RMTXD[1]_MUX1 */\
    MUX_VAL(PINCNTL163, (IEN | IPD | FCN4 )) /* EMAC[1]_RMTXEN_MUX1 */\
    MUX_VAL(PINCNTL164, (IEN | IPU | FCN8 )) /* GP0[18]_MUX0 */\
    MUX_VAL(PINCNTL165, (IEN | IPU | FCN8 )) /* GP0[19]_MUX0 */\
    MUX_VAL(PINCNTL166, (IEN | IPU | FCN8 )) /* GP0[20]_MUX0 */\
    MUX_VAL(PINCNTL167, (IEN | IPU | DISABLED )) /* safe_mode */\
    MUX_VAL(PINCNTL168, (IEN | IPU | DISABLED )) /* safe_mode */\
    MUX_VAL(PINCNTL169, (IEN | IPD | DISABLED )) /* safe_mode */\
    MUX_VAL(PINCNTL170, (IEN | IPD | DISABLED )) /* safe_mode */\
    MUX_VAL(PINCNTL171, (IEN | IPD | DISABLED )) /* safe_mode */\
    MUX_VAL(PINCNTL172, (IEN | IPD | DISABLED )) /* safe_mode */\
    MUX_VAL(PINCNTL173, (IEN | IPU | DISABLED )) /* safe_mode */\
    MUX_VAL(PINCNTL174, (IEN | IPD | DISABLED )) /* safe_mode */\
    MUX_VAL(PINCNTL175, (IEN | IPD | DISABLED )) /* safe_mode */\
    MUX_VAL(PINCNTL176, (IEN | IPD | FCN1 )) /* VOUT[0]_CLK */\
    MUX_VAL(PINCNTL177, (IEN | IPD | FCN1 )) /* VOUT[0]_HSYNC */\
    MUX_VAL(PINCNTL178, (IEN | IPD | FCN1 )) /* VOUT[0]_VSYNC */\
    MUX_VAL(PINCNTL179, (IEN | IPD | FCN8 )) /* GP2[21] */\
    MUX_VAL(PINCNTL180, (IEN | IPD | FCN1 )) /* VOUT[0]_B_CB_C[2] */\
    MUX_VAL(PINCNTL181, (IEN | IPD | FCN1 )) /* VOUT[0]_B_CB_C[3] */\
    MUX_VAL(PINCNTL182, (IEN | IPD | FCN1 )) /* VOUT[0]_B_CB_C[4] */\
    MUX_VAL(PINCNTL183, (IEN | IPD | FCN1 )) /* VOUT[0]_B_CB_C[5] */\
    MUX_VAL(PINCNTL184, (IEN | IPD | FCN1 )) /* VOUT[0]_B_CB_C[6] */\
    MUX_VAL(PINCNTL185, (IEN | IPD | FCN1 )) /* VOUT[0]_B_CB_C[7] */\
    MUX_VAL(PINCNTL186, (IEN | IPD | FCN1 )) /* VOUT[0]_B_CB_C[8] */\
    MUX_VAL(PINCNTL187, (IEN | IPD | FCN1 )) /* VOUT[0]_B_CB_C[9] */\
    MUX_VAL(PINCNTL188, (IEN | IPD | FCN1 )) /* VOUT[0]_G_Y_YC[2] */\
    MUX_VAL(PINCNTL189, (IEN | IPD | FCN1 )) /* VOUT[0]_G_Y_YC[3] */\
    MUX_VAL(PINCNTL190, (IEN | IPD | FCN1 )) /* VOUT[0]_G_Y_YC[4] */\
    MUX_VAL(PINCNTL191, (IEN | IPD | FCN1 )) /* VOUT[0]_G_Y_YC[5] */\
    MUX_VAL(PINCNTL192, (IEN | IPD | FCN1 )) /* VOUT[0]_G_Y_YC[6] */\
    MUX_VAL(PINCNTL193, (IEN | IPD | FCN1 )) /* VOUT[0]_G_Y_YC[7] */\
    MUX_VAL(PINCNTL194, (IEN | IPD | FCN1 )) /* VOUT[0]_G_Y_YC[8] */\
    MUX_VAL(PINCNTL195, (IEN | IPD | FCN1 )) /* VOUT[0]_G_Y_YC[9] */\
    MUX_VAL(PINCNTL196, (IEN | IPD | FCN1 )) /* VOUT[0]_R_CR[2] */\
    MUX_VAL(PINCNTL197, (IEN | IPD | FCN1 )) /* VOUT[0]_R_CR[3] */\
    MUX_VAL(PINCNTL198, (IEN | IPD | FCN1 )) /* VOUT[0]_R_CR[4] */\
    MUX_VAL(PINCNTL199, (IEN | IPD | FCN1 )) /* VOUT[0]_R_CR[5] */\
    MUX_VAL(PINCNTL200, (IEN | IPD | FCN1 )) /* VOUT[0]_R_CR[6] */\
    MUX_VAL(PINCNTL201, (IEN | IPD | FCN1 )) /* VOUT[0]_R_CR[7] */\
    MUX_VAL(PINCNTL202, (IEN | IPD | FCN1 )) /* VOUT[0]_R_CR[8] */\
    MUX_VAL(PINCNTL203, (IEN | IPD | FCN1 )) /* VOUT[0]_R_CR[9] */\
    MUX_VAL(PINCNTL204, (IEN | IPD | FCN3 )) /* VIN[1]A_HSYNC */\
    MUX_VAL(PINCNTL205, (IEN | IPD | FCN3 )) /* VIN[1]A_VSYNC */\
    MUX_VAL(PINCNTL206, (IEN | IPD | FCN3 )) /* VIN[1]A_FLD */\
    MUX_VAL(PINCNTL207, (IEN | IPD | FCN3 )) /* VIN[1]A_CLK */\
    MUX_VAL(PINCNTL208, (IEN | IPD | FCN3 )) /* VIN[1]A_D[0] */\
    MUX_VAL(PINCNTL209, (IEN | IPD | FCN3 )) /* VIN[1]A_D[1] */\
    MUX_VAL(PINCNTL210, (IEN | IPD | FCN3 )) /* VIN[1]A_D[2] */\
    MUX_VAL(PINCNTL211, (IEN | IPD | FCN3 )) /* VIN[1]A_D[3] */\
    MUX_VAL(PINCNTL212, (IEN | IPD | FCN3 )) /* VIN[1]A_D[4] */\
    MUX_VAL(PINCNTL213, (IEN | IPD | FCN3 )) /* VIN[1]A_D[5] */\
    MUX_VAL(PINCNTL214, (IEN | IPD | FCN3 )) /* VIN[1]A_D[6] */\
    MUX_VAL(PINCNTL215, (IEN | IPD | FCN3 )) /* VIN[1]A_D[8] */\
    MUX_VAL(PINCNTL216, (IEN | IPD | FCN3 )) /* VIN[1]A_D[9] */\
    MUX_VAL(PINCNTL217, (IEN | IPD | FCN3 )) /* VIN[1]A_D[10] */\
    MUX_VAL(PINCNTL218, (IEN | IPD | FCN3 )) /* VIN[1]A_D[11] */\
    MUX_VAL(PINCNTL219, (IEN | IPD | FCN3 )) /* VIN[1]A_D[12] */\
    MUX_VAL(PINCNTL220, (IEN | IPD | FCN3 )) /* VIN[1]A_D[13] */\
    MUX_VAL(PINCNTL221, (IEN | IPD | FCN3 )) /* VIN[1]A_D[14] */\
    MUX_VAL(PINCNTL222, (IEN | IPD | FCN3 )) /* VIN[1]A_D[15] */\
    MUX_VAL(PINCNTL223, (IEN | IPD | FCN3 )) /* VIN[1]A_D[16] */\
    MUX_VAL(PINCNTL224, (IEN | IPD | FCN3 )) /* VIN[1]A_D[17] */\
    MUX_VAL(PINCNTL225, (IEN | IPD | FCN3 )) /* VIN[1]A_D[18] */\
    MUX_VAL(PINCNTL226, (IEN | IPD | FCN3 )) /* VIN[1]A_D[19] */\
    MUX_VAL(PINCNTL227, (IEN | IPD | FCN3 )) /* VIN[1]A_D[20] */\
    MUX_VAL(PINCNTL228, (IEN | IPU | FCN3 )) /* VIN[1]A_D[21] */\
    MUX_VAL(PINCNTL229, (IEN | IPU | FCN3 )) /* VIN[1]A_D[22] */\
    MUX_VAL(PINCNTL230, (IEN | IPD | FCN3 )) /* VIN[1]A_D[23] */\
    MUX_VAL(PINCNTL231, (IEN | IPU | FCN3 )) /* VIN[1]A_D[7] */\
    MUX_VAL(PINCNTL232, (IEN | IPD | FCN1 )) /* EMAC_RMREFCLK */\
    MUX_VAL(PINCNTL233, (IEN | IPU | FCN1 )) /* MDCLK */\
    MUX_VAL(PINCNTL234, (IEN | IPU | FCN1 )) /* MDIO */\
    MUX_VAL(PINCNTL235, (IEN | IPD | FCN1 )) /* EMAC[0]_MTCLK/EMAC[0]_RGRXC */\
    MUX_VAL(PINCNTL236, (IEN | IPD | FCN1 )) /* EMAC[0]_MCOL/EMAC[0]_RGRXCTL */\
    MUX_VAL(PINCNTL237, (IEN | IPD | FCN1 )) /* EMAC[0]_MCRS/EMAC[0]_RGRXD[2] */\
    MUX_VAL(PINCNTL238, (IEN | IPD | FCN1 )) /* EMAC[0]_MRXER/EMAC[0]_RGTXCTL */\
    MUX_VAL(PINCNTL239, (IEN | IPD | FCN1 )) /* EMAC[0]_MRCLK/EMAC[0]_RGTXC */\
    MUX_VAL(PINCNTL240, (IEN | IPD | FCN1 )) /* EMAC[0]_MRXD[0]/EMAC[0]_RGTXD[0] */\
    MUX_VAL(PINCNTL241, (IEN | IPD | FCN1 )) /* EMAC[0]_MRXD[1]/EMAC[0]_RGRXD[0] */\
    MUX_VAL(PINCNTL242, (IEN | IPD | FCN1 )) /* EMAC[0]_MRXD[2]/EMAC[0]_RGRXD[1] */\
    MUX_VAL(PINCNTL243, (IEN | IPD | FCN5 )) /* GPMC_A[0]_MUX0 */\
    MUX_VAL(PINCNTL244, (IEN | IPD | FCN1 )) /* EMAC[0]_MRXD[4]/EMAC[0]_RGRXD[3] */\
    MUX_VAL(PINCNTL245, (IEN | IPD | FCN1 )) /* EMAC[0]_MRXD[5]/EMAC[0]_RGTXD[3] */\
    MUX_VAL(PINCNTL246, (IEN | IPD | FCN1 )) /* EMAC[0]_MRXD[6]/EMAC[0]_RGTXD[2] */\
    MUX_VAL(PINCNTL247, (IEN | IPD | FCN1 )) /* EMAC[0]_MRXD[7]/EMAC[0]_RGTXD[1] */\
    MUX_VAL(PINCNTL248, (IEN | IPD | FCN5 )) /* GPMC_A[5]_MUX0 */\
    MUX_VAL(PINCNTL249, (IEN | IPD | FCN5 )) /* GPMC_A[6]_MUX0 */\
    MUX_VAL(PINCNTL250, (IEN | IPD | FCN5 )) /* GPMC_A[7]_MUX0 */\
    MUX_VAL(PINCNTL251, (IEN | IPD | FCN5 )) /* GPMC_A[8]_MUX0 */\
    MUX_VAL(PINCNTL252, (IEN | IPD | FCN5 )) /* GPMC_A[9]_MUX0 */\
    MUX_VAL(PINCNTL253, (IEN | IPD | FCN5 )) /* GPMC_A[10]_MUX0 */\
    MUX_VAL(PINCNTL254, (IEN | IPD | FCN5 )) /* GPMC_A[11]_MUX0 */\
    MUX_VAL(PINCNTL255, (IEN | IPD | FCN5 )) /* GPMC_A[12]_MUX0 */\
    MUX_VAL(PINCNTL256, (IEN | IPD | FCN5 )) /* GPMC_A[13]_MUX0 */\
    MUX_VAL(PINCNTL257, (IEN | IPD | FCN5 )) /* GPMC_A[14]_MUX0 */\
    MUX_VAL(PINCNTL258, (IEN | IPD | FCN5 )) /* GPMC_A[15]_MUX0 */\
    MUX_VAL(PINCNTL259, (IEN | IPD | FCN8 )) /* GP3[31] */\
    MUX_VAL(PINCNTL260, (IEN | IPU | DISABLED )) /* safe_mode */\
    MUX_VAL(PINCNTL261, (IEN | IPU | DISABLED )) /* safe_mode */\
    MUX_VAL(PINCNTL262, (IEN | DIS | DISABLED )) /* safe_mode */\
    MUX_VAL(PINCNTL263, (IEN | IPU | FCN1 )) /* I2C[0]_SCL */\
    MUX_VAL(PINCNTL264, (IEN | IPU | FCN1 )) /* I2C[0]_SDA */\
    MUX_VAL(PINCNTL270, (IEN | IPD | FCN1 )) /* USB0_DRVVBUS */
    
    #endif
    

    Should I try to run the loopback test from Mistral with modifications for RMII ?

    Thanks!

    Ran

  • Ran,

    Ran S. said:
    > Can you try make these 3 pins outputs? 
    How can I do this ? I see that the pinmux lines you have copied are the same as my previous post.

    I Quote your 3 pin lines that are configured for input, but might be needed to be set as output. When I quote something, it is for better understanding what I am referring to, not the ready made solution that you should replace in your code. I think the "IEN" flag means "Input ENable", so you can try to change it for output.

    Regards,
    Pavel

  • Hi Pavel,

    Thanks, I was not familiar with that.

    I will try this now.

    Regards,

    Ran

  • Ran,

    Ran S. said:
    the complete pinmux is attached
    3247.pinmux_new.txt
    #ifndef _PINMUX_H_
    #define _PINMUX_H_
    
    /*
     * DISABLED - Disabled
     * FCN1 - Mux Fcn 1
     * FCN2 - Mux Fcn 2
     * FCN3 - Mux Fcn 3
     * FCN4 - Mux Fcn 4
     * FCN5 - Mux Fcn 5
     * FCN6 - Mux Fcn 6
     * FCN7 - Mux Fcn 7
     * FCN8 - Mux Fcn 8
     * IDIS - Receiver disabled
     * IEN - Receiver enabled
     * IPD - Internal pull-down
     * IPU - Internal pull-up
     * DIS - Internal pull disabled
     */
    
    #define MUX_EVM() \
    
    /* Design Status: NO ERRORS */
    
    MUX_VAL(PINCNTL1, (IEN | IPU | DISABLED )) /* safe_mode */\
    MUX_VAL(PINCNTL2, (IEN | IPU | FCN8 )) /* GP0[0] */\
    MUX_VAL(PINCNTL3, (IEN | IPU | DISABLED )) /* safe_mode */\
    MUX_VAL(PINCNTL4, (IEN | IPU | DISABLED )) /* safe_mode */\
    MUX_VAL(PINCNTL5, (IEN | IPU | DISABLED )) /* safe_mode */\
    MUX_VAL(PINCNTL6, (IEN | IPU | DISABLED )) /* safe_mode */\
    MUX_VAL(PINCNTL7, (IEN | IPU | FCN2 )) /* SPI[1]_SCS[1] */\
    MUX_VAL(PINCNTL8, (IEN | IPU | FCN8 )) /* GP0[1] */\
    MUX_VAL(PINCNTL9, (IEN | IPU | FCN8 )) /* GP0[2] */\
    MUX_VAL(PINCNTL10, (IEN | IPU | FCN8 )) /* GP0[3] */\
    MUX_VAL(PINCNTL11, (IEN | IPU | FCN8 )) /* GP0[4] */\
    MUX_VAL(PINCNTL12, (IEN | IPU | FCN8 )) /* GP0[5] */\
    MUX_VAL(PINCNTL13, (IEN | IPU | FCN8 )) /* GP0[6] */\
    MUX_VAL(PINCNTL14, (IEN | IPD | FCN4 )) /* MCA[3]_AHCLKX */\
    MUX_VAL(PINCNTL15, (IEN | IPD | FCN8 )) /* GP0[8] */\
    MUX_VAL(PINCNTL16, (IEN | IPD | FCN3 )) /* MCA[2]_AHCLKX */\
    MUX_VAL(PINCNTL17, (IEN | IPD | DISABLED )) /* safe_mode */\
    MUX_VAL(PINCNTL18, (IEN | IPD | DISABLED )) /* safe_mode */\
    MUX_VAL(PINCNTL19, (IEN | IPD | DISABLED )) /* safe_mode */\
    MUX_VAL(PINCNTL20, (IEN | IPD | DISABLED )) /* safe_mode */\
    MUX_VAL(PINCNTL21, (IEN | IPD | DISABLED )) /* safe_mode */\
    MUX_VAL(PINCNTL22, (IEN | IPU | FCN6 )) /* I2C[3]_SCL_MUX0 */\
    MUX_VAL(PINCNTL23, (IEN | IPU | FCN6 )) /* I2C[3]_SDA_MUX0 */\
    MUX_VAL(PINCNTL24, (IEN | IPD | DISABLED )) /* safe_mode */\
    MUX_VAL(PINCNTL25, (IEN | IPD | DISABLED )) /* safe_mode */\
    MUX_VAL(PINCNTL26, (IEN | IPD | DISABLED )) /* safe_mode */\
    MUX_VAL(PINCNTL27, (IEN | IPD | FCN2 )) /* MCB_DR */\
    MUX_VAL(PINCNTL28, (IEN | IPD | FCN2 )) /* MCB_DX */\
    MUX_VAL(PINCNTL29, (IEN | IPD | FCN2 )) /* MCB_FSX */\
    MUX_VAL(PINCNTL30, (IEN | IPD | FCN2 )) /* MCB_CLKX */\
    MUX_VAL(PINCNTL31, (IEN | IPD | DISABLED )) /* safe_mode */\
    MUX_VAL(PINCNTL32, (IEN | IPD | DISABLED )) /* safe_mode */\
    MUX_VAL(PINCNTL33, (IEN | IPD | DISABLED )) /* safe_mode */\
    MUX_VAL(PINCNTL34, (IEN | IPD | DISABLED )) /* safe_mode */\
    MUX_VAL(PINCNTL35, (IEN | IPU | DISABLED )) /* safe_mode */\
    MUX_VAL(PINCNTL36, (IEN | IPU | DISABLED )) /* safe_mode */\
    MUX_VAL(PINCNTL37, (IEN | IPD | FCN2 )) /* MCB_FSR_MUX0 */\
    MUX_VAL(PINCNTL38, (IEN | IPD | FCN2 )) /* MCB_CLKR_MUX0 */\
    MUX_VAL(PINCNTL39, (IEN | IPU | FCN1 )) /* MCA[2]_ACLKX */\
    MUX_VAL(PINCNTL40, (IEN | IPU | FCN1 )) /* MCA[2]_AFSX */\
    MUX_VAL(PINCNTL41, (IEN | IPU | FCN1 )) /* MCA[2]_AXR[0] */\
    MUX_VAL(PINCNTL42, (IEN | IPU | FCN1 )) /* MCA[2]_AXR[1] */\
    MUX_VAL(PINCNTL43, (IEN | IPD | FCN1 )) /* MCA[2]_AXR[2] */\
    MUX_VAL(PINCNTL44, (IEN | IPD | FCN1 )) /* MCA[2]_AXR[3] */\
    MUX_VAL(PINCNTL45, (IEN | IPD | FCN1 )) /* MCA[3]_ACLKX */\
    MUX_VAL(PINCNTL46, (IEN | IPD | FCN1 )) /* MCA[3]_AFSX */\
    MUX_VAL(PINCNTL47, (IEN | IPD | FCN1 )) /* MCA[3]_AXR[0] */\
    MUX_VAL(PINCNTL48, (IEN | IPD | FCN1 )) /* MCA[3]_AXR[1] */\
    MUX_VAL(PINCNTL49, (IEN | IPD | FCN1 )) /* MCA[3]_AXR[2] */\
    MUX_VAL(PINCNTL50, (IEN | IPD | FCN1 )) /* MCA[3]_AXR[3] */\
    MUX_VAL(PINCNTL51, (IEN | IPD | FCN8 )) /* GP0[21]_MUX1 */\
    MUX_VAL(PINCNTL52, (IEN | IPD | FCN8 )) /* GP0[22]_MUX1 */\
    MUX_VAL(PINCNTL53, (IEN | IPD | FCN8 )) /* GP0[23]_MUX1 */\
    MUX_VAL(PINCNTL54, (IEN | IPD | FCN8 )) /* GP0[24]_MUX1 */\
    MUX_VAL(PINCNTL55, (IEN | IPD | FCN8 )) /* GP0[25]_MUX1 */\
    MUX_VAL(PINCNTL56, (IEN | IPD | FCN8 )) /* GP0[26]_MUX1 */\
    MUX_VAL(PINCNTL57, (IEN | IPD | FCN8 )) /* GP0[27]_MUX1 */\
    MUX_VAL(PINCNTL58, (IEN | IPD | FCN8 )) /* GP0[28]_MUX1 */\
    MUX_VAL(PINCNTL59, (IEN | IPD | FCN4 )) /* UART2_RXD_MUX1 */\
    MUX_VAL(PINCNTL60, (IEN | IPD | FCN8 )) /* GP0[30] */\
    MUX_VAL(PINCNTL61, (IEN | IPD | FCN4 )) /* UART2_TXD_MUX1 */\
    MUX_VAL(PINCNTL62, (IEN | IPD | FCN8 )) /* GP1[7]_MUX1 */\
    MUX_VAL(PINCNTL63, (IEN | IPU | FCN8 )) /* GP1[8]_MUX1 */\
    MUX_VAL(PINCNTL64, (IEN | IPD | FCN8 )) /* GP1[9]_MUX1 */\
    MUX_VAL(PINCNTL65, (IEN | IPU | FCN8 )) /* GP1[10]_MUX1 */\
    MUX_VAL(PINCNTL68, (IEN | IPU | FCN8 )) /* GP1[0] */\
    MUX_VAL(PINCNTL69, (IEN | IPU | FCN8 )) /* GP1[1] */\
    MUX_VAL(PINCNTL70, (IEN | IPU | FCN1 )) /* UART0_RXD */\
    MUX_VAL(PINCNTL71, (IEN | IPU | FCN1 )) /* UART0_TXD */\
    MUX_VAL(PINCNTL72, (IEN | IPU | FCN2 )) /* UART4_RXD_MUX3 */\
    MUX_VAL(PINCNTL73, (IEN | IPU | FCN2 )) /* UART4_TXD_MUX3 */\
    MUX_VAL(PINCNTL74, (IEN | IPU | FCN2 )) /* UART3_RXD_MUX0 */\
    MUX_VAL(PINCNTL75, (IEN | IPU | FCN2 )) /* UART3_TXD_MUX0 */\
    MUX_VAL(PINCNTL76, (IEN | IPU | FCN3 )) /* UART1_TXD_MUX0 */\
    MUX_VAL(PINCNTL77, (IEN | IPU | FCN3 )) /* UART1_RXD_MUX0 */\
    MUX_VAL(PINCNTL78, (IEN | IPU | FCN1 )) /* I2C[1]_SCL */\
    MUX_VAL(PINCNTL79, (IEN | IPU | FCN1 )) /* I2C[1]_SDA */\
    MUX_VAL(PINCNTL80, (IEN | IPU | FCN8 )) /* GP1[6] */\
    MUX_VAL(PINCNTL81, (IEN | IPU | FCN1 )) /* SPI[0]_SCS[0] */\
    MUX_VAL(PINCNTL82, (IEN | IPU | FCN1 )) /* SPI[0]_SCLK */\
    MUX_VAL(PINCNTL83, (IEN | IPU | FCN1 )) /* SPI[0]_D[1] */\
    MUX_VAL(PINCNTL84, (IEN | IPU | FCN1 )) /* SPI[0]_D[0] */\
    MUX_VAL(PINCNTL85, (IEN | IPU | FCN8 )) /* GP1[16]_MUX1 */\
    MUX_VAL(PINCNTL86, (IEN | IPU | FCN1 )) /* SPI[1]_SCLK */\
    MUX_VAL(PINCNTL87, (IEN | IPU | FCN1 )) /* SPI[1]_D[1] */\
    MUX_VAL(PINCNTL88, (IEN | IPU | FCN1 )) /* SPI[1]_D[0] */\
    MUX_VAL(PINCNTL89, (IEN | DIS | FCN1 )) /* GPMC_D[0] */\
    MUX_VAL(PINCNTL90, (IEN | DIS | FCN1 )) /* GPMC_D[1] */\
    MUX_VAL(PINCNTL91, (IEN | DIS | FCN1 )) /* GPMC_D[2] */\
    MUX_VAL(PINCNTL92, (IEN | DIS | FCN1 )) /* GPMC_D[3] */\
    MUX_VAL(PINCNTL93, (IEN | DIS | FCN1 )) /* GPMC_D[4] */\
    MUX_VAL(PINCNTL94, (IEN | DIS | FCN1 )) /* GPMC_D[5] */\
    MUX_VAL(PINCNTL95, (IEN | DIS | FCN1 )) /* GPMC_D[6] */\
    MUX_VAL(PINCNTL96, (IEN | DIS | FCN1 )) /* GPMC_D[7] */\
    MUX_VAL(PINCNTL97, (IEN | DIS | FCN1 )) /* GPMC_D[8] */\
    MUX_VAL(PINCNTL98, (IEN | DIS | FCN1 )) /* GPMC_D[9] */\
    MUX_VAL(PINCNTL99, (IEN | DIS | FCN1 )) /* GPMC_D[10] */\
    MUX_VAL(PINCNTL100, (IEN | DIS | FCN1 )) /* GPMC_D[11] */\
    MUX_VAL(PINCNTL101, (IEN | DIS | FCN1 )) /* GPMC_D[12] */\
    MUX_VAL(PINCNTL102, (IEN | DIS | FCN1 )) /* GPMC_D[13] */\
    MUX_VAL(PINCNTL103, (IEN | DIS | FCN1 )) /* GPMC_D[14] */\
    MUX_VAL(PINCNTL104, (IEN | DIS | FCN1 )) /* GPMC_D[15] */\
    MUX_VAL(PINCNTL105, (IEN | IPD | FCN1 )) /* GPMC_A[16] */\
    MUX_VAL(PINCNTL106, (IEN | IPD | FCN1 )) /* GPMC_A[17] */\
    MUX_VAL(PINCNTL107, (IEN | IPD | FCN1 )) /* GPMC_A[18] */\
    MUX_VAL(PINCNTL108, (IEN | IPD | FCN1 )) /* GPMC_A[19] */\
    MUX_VAL(PINCNTL109, (IEN | IPU | FCN3 )) /* SPI[2]_SCS[1] */\
    MUX_VAL(PINCNTL110, (IEN | IPD | FCN3 )) /* SPI[2]_D[0]_MUX0 */\
    MUX_VAL(PINCNTL111, (IEN | IPU | FCN3 )) /* SPI[2]_D[1]_MUX0 */\
    MUX_VAL(PINCNTL112, (IEN | IPD | FCN3 )) /* SPI[2]_SCLK_MUX0 */\
    MUX_VAL(PINCNTL113, (IEN | IPU | FCN8 )) /* GP1[19] */\
    MUX_VAL(PINCNTL114, (IEN | IPU | FCN8 )) /* GP1[20] */\
    MUX_VAL(PINCNTL115, (IEN | IPU | FCN8 )) /* GP1[21] */\
    MUX_VAL(PINCNTL116, (IEN | IPU | FCN8 )) /* GP1[22] */\
    MUX_VAL(PINCNTL117, (IEN | IPU | FCN2 )) /* GPMC_A[1]_MUX1 */\
    MUX_VAL(PINCNTL118, (IEN | IPU | FCN2 )) /* GPMC_A[2]_MUX1 */\
    MUX_VAL(PINCNTL119, (IEN | IPU | FCN2 )) /* GPMC_A[3]_MUX1 */\
    MUX_VAL(PINCNTL120, (IEN | IPU | FCN2 )) /* GPMC_A[4]_MUX1 */\
    MUX_VAL(PINCNTL121, (IEN | IPU | FCN8 )) /* GP1[15]_MUX1 */\
    MUX_VAL(PINCNTL122, (IEN | IPU | FCN1 )) /* GPMC_CS[0] */\
    MUX_VAL(PINCNTL123, (IEN | IPU | FCN1 )) /* GPMC_CS[1] */\
    MUX_VAL(PINCNTL124, (IEN | IPU | FCN1 )) /* GPMC_CS[2] */\
    MUX_VAL(PINCNTL125, (IEN | IPU | FCN3 )) /* SPI[2]_SCS[0] */\
    MUX_VAL(PINCNTL126, (IEN | IPU | DISABLED )) /* safe_mode */\
    MUX_VAL(PINCNTL127, (IEN | IPU | FCN1 )) /* GPMC_CLK */\
    MUX_VAL(PINCNTL128, (IEN | IPU | FCN1 )) /* GPMC_ADV_ALE */\
    MUX_VAL(PINCNTL129, (IEN | IPU | FCN1 )) /* GPMC_OE_RE */\
    MUX_VAL(PINCNTL130, (IEN | IPU | FCN1 )) /* GPMC_WE */\
    MUX_VAL(PINCNTL131, (IEN | IPD | FCN1 )) /* GPMC_BE[0]_CLE */\
    MUX_VAL(PINCNTL132, (IEN | IPD | FCN1 )) /* GPMC_BE[1] */\
    MUX_VAL(PINCNTL133, (IEN | IPU | FCN1 )) /* GPMC_WAIT[0] */\
    MUX_VAL(PINCNTL134, (IEN | IPD | FCN6 )) /* CLKOUT0 */\
    MUX_VAL(PINCNTL135, (IEN | IPU | FCN8 )) /* GP2[0] */\
    MUX_VAL(PINCNTL136, (IEN | IPU | FCN8 )) /* GP2[1] */\
    MUX_VAL(PINCNTL137, (IEN | IPD | FCN8 )) /* GP2[2]_MUX1 */\
    MUX_VAL(PINCNTL138, (IEN | IPU | FCN8 )) /* GP2[3] */\
    MUX_VAL(PINCNTL139, (IEN | IPU | FCN8 )) /* GP2[4] */\
    MUX_VAL(PINCNTL140, (IEN | IPD | FCN8 )) /* GP1[11]_MUX1 */\
    MUX_VAL(PINCNTL141, (IEN | IPD | FCN8 )) /* GP1[12]_MUX1 */\
    MUX_VAL(PINCNTL142, (IEN | IPD | FCN8 )) /* GP2[7] */\
    MUX_VAL(PINCNTL143, (IEN | IPD | FCN8 )) /* GP2[8] */\
    MUX_VAL(PINCNTL144, (IEN | IPD | FCN8 )) /* GP2[9] */\
    MUX_VAL(PINCNTL145, (IEN | IPD | FCN8 )) /* GP2[10] */\
    MUX_VAL(PINCNTL146, (IEN | IPD | FCN8 )) /* GP2[11] */\
    MUX_VAL(PINCNTL147, (IEN | IPD | FCN8 )) /* GP2[12] */\
    MUX_VAL(PINCNTL148, (IEN | IPD | FCN8 )) /* GP2[13] */\
    MUX_VAL(PINCNTL149, (IEN | IPD | FCN8 )) /* GP2[14] */\
    MUX_VAL(PINCNTL150, (IEN | IPD | FCN8 )) /* GP2[15] */\
    MUX_VAL(PINCNTL151, (IEN | IPD | FCN8 )) /* GP2[16] */\
    MUX_VAL(PINCNTL152, (IEN | IPD | FCN8 )) /* GP2[17] */\
    MUX_VAL(PINCNTL153, (IEN | IPD | FCN8 )) /* GP2[18] */\
    MUX_VAL(PINCNTL154, (IEN | IPD | FCN8 )) /* GP2[19] */\
    MUX_VAL(PINCNTL155, (IEN | IPD | FCN8 )) /* GP2[20] */\
    MUX_VAL(PINCNTL156, (IEN | IPU | FCN8 )) /* GP0[10]_MUX0 */\
    MUX_VAL(PINCNTL157, (IEN | IPD | FCN4 )) /* EMAC[1]_RMRXER_MUX1 */\
    MUX_VAL(PINCNTL158, (IEN | IPU | FCN4 )) /* EMAC[1]_RMRXD[1]_MUX1 */\
    MUX_VAL(PINCNTL159, (IEN | IPU | FCN4 )) /* EMAC[1]_RMRXD[0]_MUX1 */\
    MUX_VAL(PINCNTL160, (IEN | IPD | FCN4 )) /* EMAC[1]_RMCRSDV_MUX1 */\
    MUX_VAL(PINCNTL161, (IEN | IPD | FCN4 )) /* EMAC[1]_RMTXD[0]_MUX1 */\
    MUX_VAL(PINCNTL162, (IEN | IPD | FCN4 )) /* EMAC[1]_RMTXD[1]_MUX1 */\
    MUX_VAL(PINCNTL163, (IEN | IPD | FCN4 )) /* EMAC[1]_RMTXEN_MUX1 */\
    MUX_VAL(PINCNTL164, (IEN | IPU | FCN8 )) /* GP0[18]_MUX0 */\
    MUX_VAL(PINCNTL165, (IEN | IPU | FCN8 )) /* GP0[19]_MUX0 */\
    MUX_VAL(PINCNTL166, (IEN | IPU | FCN8 )) /* GP0[20]_MUX0 */\
    MUX_VAL(PINCNTL167, (IEN | IPU | DISABLED )) /* safe_mode */\
    MUX_VAL(PINCNTL168, (IEN | IPU | DISABLED )) /* safe_mode */\
    MUX_VAL(PINCNTL169, (IEN | IPD | DISABLED )) /* safe_mode */\
    MUX_VAL(PINCNTL170, (IEN | IPD | DISABLED )) /* safe_mode */\
    MUX_VAL(PINCNTL171, (IEN | IPD | DISABLED )) /* safe_mode */\
    MUX_VAL(PINCNTL172, (IEN | IPD | DISABLED )) /* safe_mode */\
    MUX_VAL(PINCNTL173, (IEN | IPU | DISABLED )) /* safe_mode */\
    MUX_VAL(PINCNTL174, (IEN | IPD | DISABLED )) /* safe_mode */\
    MUX_VAL(PINCNTL175, (IEN | IPD | DISABLED )) /* safe_mode */\
    MUX_VAL(PINCNTL176, (IEN | IPD | FCN1 )) /* VOUT[0]_CLK */\
    MUX_VAL(PINCNTL177, (IEN | IPD | FCN1 )) /* VOUT[0]_HSYNC */\
    MUX_VAL(PINCNTL178, (IEN | IPD | FCN1 )) /* VOUT[0]_VSYNC */\
    MUX_VAL(PINCNTL179, (IEN | IPD | FCN8 )) /* GP2[21] */\
    MUX_VAL(PINCNTL180, (IEN | IPD | FCN1 )) /* VOUT[0]_B_CB_C[2] */\
    MUX_VAL(PINCNTL181, (IEN | IPD | FCN1 )) /* VOUT[0]_B_CB_C[3] */\
    MUX_VAL(PINCNTL182, (IEN | IPD | FCN1 )) /* VOUT[0]_B_CB_C[4] */\
    MUX_VAL(PINCNTL183, (IEN | IPD | FCN1 )) /* VOUT[0]_B_CB_C[5] */\
    MUX_VAL(PINCNTL184, (IEN | IPD | FCN1 )) /* VOUT[0]_B_CB_C[6] */\
    MUX_VAL(PINCNTL185, (IEN | IPD | FCN1 )) /* VOUT[0]_B_CB_C[7] */\
    MUX_VAL(PINCNTL186, (IEN | IPD | FCN1 )) /* VOUT[0]_B_CB_C[8] */\
    MUX_VAL(PINCNTL187, (IEN | IPD | FCN1 )) /* VOUT[0]_B_CB_C[9] */\
    MUX_VAL(PINCNTL188, (IEN | IPD | FCN1 )) /* VOUT[0]_G_Y_YC[2] */\
    MUX_VAL(PINCNTL189, (IEN | IPD | FCN1 )) /* VOUT[0]_G_Y_YC[3] */\
    MUX_VAL(PINCNTL190, (IEN | IPD | FCN1 )) /* VOUT[0]_G_Y_YC[4] */\
    MUX_VAL(PINCNTL191, (IEN | IPD | FCN1 )) /* VOUT[0]_G_Y_YC[5] */\
    MUX_VAL(PINCNTL192, (IEN | IPD | FCN1 )) /* VOUT[0]_G_Y_YC[6] */\
    MUX_VAL(PINCNTL193, (IEN | IPD | FCN1 )) /* VOUT[0]_G_Y_YC[7] */\
    MUX_VAL(PINCNTL194, (IEN | IPD | FCN1 )) /* VOUT[0]_G_Y_YC[8] */\
    MUX_VAL(PINCNTL195, (IEN | IPD | FCN1 )) /* VOUT[0]_G_Y_YC[9] */\
    MUX_VAL(PINCNTL196, (IEN | IPD | FCN1 )) /* VOUT[0]_R_CR[2] */\
    MUX_VAL(PINCNTL197, (IEN | IPD | FCN1 )) /* VOUT[0]_R_CR[3] */\
    MUX_VAL(PINCNTL198, (IEN | IPD | FCN1 )) /* VOUT[0]_R_CR[4] */\
    MUX_VAL(PINCNTL199, (IEN | IPD | FCN1 )) /* VOUT[0]_R_CR[5] */\
    MUX_VAL(PINCNTL200, (IEN | IPD | FCN1 )) /* VOUT[0]_R_CR[6] */\
    MUX_VAL(PINCNTL201, (IEN | IPD | FCN1 )) /* VOUT[0]_R_CR[7] */\
    MUX_VAL(PINCNTL202, (IEN | IPD | FCN1 )) /* VOUT[0]_R_CR[8] */\
    MUX_VAL(PINCNTL203, (IEN | IPD | FCN1 )) /* VOUT[0]_R_CR[9] */\
    MUX_VAL(PINCNTL204, (IEN | IPD | FCN3 )) /* VIN[1]A_HSYNC */\
    MUX_VAL(PINCNTL205, (IEN | IPD | FCN3 )) /* VIN[1]A_VSYNC */\
    MUX_VAL(PINCNTL206, (IEN | IPD | FCN3 )) /* VIN[1]A_FLD */\
    MUX_VAL(PINCNTL207, (IEN | IPD | FCN3 )) /* VIN[1]A_CLK */\
    MUX_VAL(PINCNTL208, (IEN | IPD | FCN3 )) /* VIN[1]A_D[0] */\
    MUX_VAL(PINCNTL209, (IEN | IPD | FCN3 )) /* VIN[1]A_D[1] */\
    MUX_VAL(PINCNTL210, (IEN | IPD | FCN3 )) /* VIN[1]A_D[2] */\
    MUX_VAL(PINCNTL211, (IEN | IPD | FCN3 )) /* VIN[1]A_D[3] */\
    MUX_VAL(PINCNTL212, (IEN | IPD | FCN3 )) /* VIN[1]A_D[4] */\
    MUX_VAL(PINCNTL213, (IEN | IPD | FCN3 )) /* VIN[1]A_D[5] */\
    MUX_VAL(PINCNTL214, (IEN | IPD | FCN3 )) /* VIN[1]A_D[6] */\
    MUX_VAL(PINCNTL215, (IEN | IPD | FCN3 )) /* VIN[1]A_D[8] */\
    MUX_VAL(PINCNTL216, (IEN | IPD | FCN3 )) /* VIN[1]A_D[9] */\
    MUX_VAL(PINCNTL217, (IEN | IPD | FCN3 )) /* VIN[1]A_D[10] */\
    MUX_VAL(PINCNTL218, (IEN | IPD | FCN3 )) /* VIN[1]A_D[11] */\
    MUX_VAL(PINCNTL219, (IEN | IPD | FCN3 )) /* VIN[1]A_D[12] */\
    MUX_VAL(PINCNTL220, (IEN | IPD | FCN3 )) /* VIN[1]A_D[13] */\
    MUX_VAL(PINCNTL221, (IEN | IPD | FCN3 )) /* VIN[1]A_D[14] */\
    MUX_VAL(PINCNTL222, (IEN | IPD | FCN3 )) /* VIN[1]A_D[15] */\
    MUX_VAL(PINCNTL223, (IEN | IPD | FCN3 )) /* VIN[1]A_D[16] */\
    MUX_VAL(PINCNTL224, (IEN | IPD | FCN3 )) /* VIN[1]A_D[17] */\
    MUX_VAL(PINCNTL225, (IEN | IPD | FCN3 )) /* VIN[1]A_D[18] */\
    MUX_VAL(PINCNTL226, (IEN | IPD | FCN3 )) /* VIN[1]A_D[19] */\
    MUX_VAL(PINCNTL227, (IEN | IPD | FCN3 )) /* VIN[1]A_D[20] */\
    MUX_VAL(PINCNTL228, (IEN | IPU | FCN3 )) /* VIN[1]A_D[21] */\
    MUX_VAL(PINCNTL229, (IEN | IPU | FCN3 )) /* VIN[1]A_D[22] */\
    MUX_VAL(PINCNTL230, (IEN | IPD | FCN3 )) /* VIN[1]A_D[23] */\
    MUX_VAL(PINCNTL231, (IEN | IPU | FCN3 )) /* VIN[1]A_D[7] */\
    MUX_VAL(PINCNTL232, (IEN | IPD | FCN1 )) /* EMAC_RMREFCLK */\
    MUX_VAL(PINCNTL233, (IEN | IPU | FCN1 )) /* MDCLK */\
    MUX_VAL(PINCNTL234, (IEN | IPU | FCN1 )) /* MDIO */\
    MUX_VAL(PINCNTL235, (IEN | IPD | FCN1 )) /* EMAC[0]_MTCLK/EMAC[0]_RGRXC */\
    MUX_VAL(PINCNTL236, (IEN | IPD | FCN1 )) /* EMAC[0]_MCOL/EMAC[0]_RGRXCTL */\
    MUX_VAL(PINCNTL237, (IEN | IPD | FCN1 )) /* EMAC[0]_MCRS/EMAC[0]_RGRXD[2] */\
    MUX_VAL(PINCNTL238, (IEN | IPD | FCN1 )) /* EMAC[0]_MRXER/EMAC[0]_RGTXCTL */\
    MUX_VAL(PINCNTL239, (IEN | IPD | FCN1 )) /* EMAC[0]_MRCLK/EMAC[0]_RGTXC */\
    MUX_VAL(PINCNTL240, (IEN | IPD | FCN1 )) /* EMAC[0]_MRXD[0]/EMAC[0]_RGTXD[0] */\
    MUX_VAL(PINCNTL241, (IEN | IPD | FCN1 )) /* EMAC[0]_MRXD[1]/EMAC[0]_RGRXD[0] */\
    MUX_VAL(PINCNTL242, (IEN | IPD | FCN1 )) /* EMAC[0]_MRXD[2]/EMAC[0]_RGRXD[1] */\
    MUX_VAL(PINCNTL243, (IEN | IPD | FCN5 )) /* GPMC_A[0]_MUX0 */\
    MUX_VAL(PINCNTL244, (IEN | IPD | FCN1 )) /* EMAC[0]_MRXD[4]/EMAC[0]_RGRXD[3] */\
    MUX_VAL(PINCNTL245, (IEN | IPD | FCN1 )) /* EMAC[0]_MRXD[5]/EMAC[0]_RGTXD[3] */\
    MUX_VAL(PINCNTL246, (IEN | IPD | FCN1 )) /* EMAC[0]_MRXD[6]/EMAC[0]_RGTXD[2] */\
    MUX_VAL(PINCNTL247, (IEN | IPD | FCN1 )) /* EMAC[0]_MRXD[7]/EMAC[0]_RGTXD[1] */\
    MUX_VAL(PINCNTL248, (IEN | IPD | FCN5 )) /* GPMC_A[5]_MUX0 */\
    MUX_VAL(PINCNTL249, (IEN | IPD | FCN5 )) /* GPMC_A[6]_MUX0 */\
    MUX_VAL(PINCNTL250, (IEN | IPD | FCN5 )) /* GPMC_A[7]_MUX0 */\
    MUX_VAL(PINCNTL251, (IEN | IPD | FCN5 )) /* GPMC_A[8]_MUX0 */\
    MUX_VAL(PINCNTL252, (IEN | IPD | FCN5 )) /* GPMC_A[9]_MUX0 */\
    MUX_VAL(PINCNTL253, (IEN | IPD | FCN5 )) /* GPMC_A[10]_MUX0 */\
    MUX_VAL(PINCNTL254, (IEN | IPD | FCN5 )) /* GPMC_A[11]_MUX0 */\
    MUX_VAL(PINCNTL255, (IEN | IPD | FCN5 )) /* GPMC_A[12]_MUX0 */\
    MUX_VAL(PINCNTL256, (IEN | IPD | FCN5 )) /* GPMC_A[13]_MUX0 */\
    MUX_VAL(PINCNTL257, (IEN | IPD | FCN5 )) /* GPMC_A[14]_MUX0 */\
    MUX_VAL(PINCNTL258, (IEN | IPD | FCN5 )) /* GPMC_A[15]_MUX0 */\
    MUX_VAL(PINCNTL259, (IEN | IPD | FCN8 )) /* GP3[31] */\
    MUX_VAL(PINCNTL260, (IEN | IPU | DISABLED )) /* safe_mode */\
    MUX_VAL(PINCNTL261, (IEN | IPU | DISABLED )) /* safe_mode */\
    MUX_VAL(PINCNTL262, (IEN | DIS | DISABLED )) /* safe_mode */\
    MUX_VAL(PINCNTL263, (IEN | IPU | FCN1 )) /* I2C[0]_SCL */\
    MUX_VAL(PINCNTL264, (IEN | IPU | FCN1 )) /* I2C[0]_SDA */\
    MUX_VAL(PINCNTL270, (IEN | IPD | FCN1 )) /* USB0_DRVVBUS */
    
    #endif
    

    I do not see the PINCNTLx registers values in your u-boot.

    For example, in the default u-boot for EMAC1 RGMII, the register value of PINCNTL253 in u-boot is 0x00000001, which means EMAC1_RGTXD0 is selected and set as output:

    TI8148_EVM#md 0x48140BF0 1
    48140bf0: 00000001    ....

    And the register value of PINCNTL256 in u-boot is 0x00040001, which means EMAC1_RGRXD0 is selected and set as input:

    TI8148_EVM#md 0x48140BFC 1
    48140bfc: 00040001    ....


    So, I need to know your PINCNTLx (i.e. 161,162,162, etc) values. I suspect these might be configured for input, not for output.

    Regards.
    Pavel

  • Hi Pavel,

    I have tried to change the setting of this pins to output (you can see it below in yellow color), but I still get no response from ping. Is there some other method or something I can try ? I have the EVM, maybe I should try to configure it as RMII in emac #1 , or is that not possible ? Is there any method to try solve this ?

    pinmux: 0x48140800:0x60000

    pinmux: 0x48140804:0x60080
    pinmux: 0x48140808:0x60000
    pinmux: 0x4814080c:0x60000
    pinmux: 0x48140810:0x60000
    pinmux: 0x48140814:0x60000
    pinmux: 0x48140818:0x60002
    pinmux: 0x4814081c:0x60080
    pinmux: 0x48140820:0x60080
    pinmux: 0x48140824:0x60080
    pinmux: 0x48140828:0x60080
    pinmux: 0x4814082c:0x60080
    pinmux: 0x48140830:0x60080
    pinmux: 0x48140834:0x40008
    pinmux: 0x48140838:0x40080
    pinmux: 0x4814083c:0x40004
    pinmux: 0x48140840:0x40000
    pinmux: 0x48140844:0x40000
    pinmux: 0x48140848:0x40000
    pinmux: 0x4814084c:0x40000
    pinmux: 0x48140850:0x40000
    pinmux: 0x48140854:0x60020
    pinmux: 0x48140858:0x60020
    pinmux: 0x4814085c:0x40000
    pinmux: 0x48140860:0x40000
    pinmux: 0x48140864:0x40000
    pinmux: 0x48140868:0x40002
    pinmux: 0x4814086c:0x40002
    pinmux: 0x48140870:0x40002
    pinmux: 0x48140874:0x40002
    pinmux: 0x48140878:0x40000
    pinmux: 0x4814087c:0x40000
    pinmux: 0x48140880:0x40000
    pinmux: 0x48140884:0x40000
    pinmux: 0x48140888:0x60000
    pinmux: 0x4814088c:0x60000
    pinmux: 0x48140890:0x40002
    pinmux: 0x48140894:0x40002
    pinmux: 0x48140898:0x60001
    pinmux: 0x4814089c:0x60001
    pinmux: 0x481408a0:0x60001
    pinmux: 0x481408a4:0x60001
    pinmux: 0x481408a8:0x40001
    pinmux: 0x481408ac:0x40001
    pinmux: 0x481408b0:0x40001
    pinmux: 0x481408b4:0x40001
    pinmux: 0x481408b8:0x40001
    pinmux: 0x481408bc:0x40001
    pinmux: 0x481408c0:0x40001
    pinmux: 0x481408c4:0x40001
    pinmux: 0x481408c8:0x40080
    pinmux: 0x481408cc:0x40080
    pinmux: 0x481408d0:0x40080
    pinmux: 0x481408d4:0x40080
    pinmux: 0x481408d8:0x40080
    pinmux: 0x481408dc:0x40080
    pinmux: 0x481408e0:0x40080
    pinmux: 0x481408e4:0x40080
    pinmux: 0x481408e8:0x40008
    pinmux: 0x481408ec:0x40080
    pinmux: 0x481408f0:0x40008
    pinmux: 0x481408f4:0x40080
    pinmux: 0x481408f8:0x60080
    pinmux: 0x481408fc:0x40080
    pinmux: 0x48140900:0x60080
    pinmux: 0x4814090c:0x60080
    pinmux: 0x48140910:0x60080
    pinmux: 0x48140914:0x60001
    pinmux: 0x48140918:0x60001
    pinmux: 0x4814091c:0x60002
    pinmux: 0x48140920:0x60002
    pinmux: 0x48140924:0x60002
    pinmux: 0x48140928:0x60002
    pinmux: 0x4814092c:0x60004
    pinmux: 0x48140930:0x60004
    pinmux: 0x48140934:0x60001
    pinmux: 0x48140938:0x60001
    pinmux: 0x4814093c:0x60080
    pinmux: 0x48140940:0x60001
    pinmux: 0x48140944:0x60001
    pinmux: 0x48140948:0x60001
    pinmux: 0x4814094c:0x60001
    pinmux: 0x48140950:0x60080
    pinmux: 0x48140954:0x60001
    pinmux: 0x48140958:0x60001
    pinmux: 0x4814095c:0x60001
    pinmux: 0x48140960:0x50001
    pinmux: 0x48140964:0x50001
    pinmux: 0x48140968:0x50001
    pinmux: 0x4814096c:0x50001
    pinmux: 0x48140970:0x50001
    pinmux: 0x48140974:0x50001
    pinmux: 0x48140978:0x50001
    pinmux: 0x4814097c:0x50001
    pinmux: 0x48140980:0x50001
    pinmux: 0x48140984:0x50001
    pinmux: 0x48140988:0x50001
    pinmux: 0x4814098c:0x50001
    pinmux: 0x48140990:0x50001
    pinmux: 0x48140994:0x50001
    pinmux: 0x48140998:0x50001
    pinmux: 0x4814099c:0x50001
    pinmux: 0x481409a0:0x40001
    pinmux: 0x481409a4:0x40001
    pinmux: 0x481409a8:0x40001
    pinmux: 0x481409ac:0x40001
    pinmux: 0x481409b0:0x60004
    pinmux: 0x481409b4:0x40004
    pinmux: 0x481409b8:0x60004
    pinmux: 0x481409bc:0x40004
    pinmux: 0x481409c0:0x60080
    pinmux: 0x481409c4:0x60080
    pinmux: 0x481409c8:0x60080
    pinmux: 0x481409cc:0x60080
    pinmux: 0x481409d0:0x60002
    pinmux: 0x481409d4:0x60002
    pinmux: 0x481409d8:0x60002
    pinmux: 0x481409dc:0x60002
    pinmux: 0x481409e0:0x60080
    pinmux: 0x481409e4:0x60001
    pinmux: 0x481409e8:0x60001
    pinmux: 0x481409ec:0x60001
    pinmux: 0x481409f0:0x60004
    pinmux: 0x481409f4:0x60000
    pinmux: 0x481409f8:0x60001
    pinmux: 0x481409fc:0x60001
    pinmux: 0x48140a00:0x60001
    pinmux: 0x48140a04:0x60001
    pinmux: 0x48140a08:0x40001
    pinmux: 0x48140a0c:0x40001
    pinmux: 0x48140a10:0x60001
    pinmux: 0x48140a14:0x40020
    pinmux: 0x48140a18:0x60080
    pinmux: 0x48140a1c:0x60080
    pinmux: 0x48140a20:0x40080
    pinmux: 0x48140a24:0x60080
    pinmux: 0x48140a28:0x60080
    pinmux: 0x48140a2c:0x40080
    pinmux: 0x48140a30:0x40080
    pinmux: 0x48140a34:0x40080
    pinmux: 0x48140a38:0x40080
    pinmux: 0x48140a3c:0x40080
    pinmux: 0x48140a40:0x40080
    pinmux: 0x48140a44:0x40080
    pinmux: 0x48140a48:0x40080
    pinmux: 0x48140a4c:0x40080
    pinmux: 0x48140a50:0x40080
    pinmux: 0x48140a54:0x40080
    pinmux: 0x48140a58:0x40080
    pinmux: 0x48140a5c:0x40080
    pinmux: 0x48140a60:0x40080
    pinmux: 0x48140a64:0x40080
    pinmux: 0x48140a68:0x40080
    pinmux: 0x48140a6c:0x60080
    pinmux: 0x48140a70:0x40008
    pinmux: 0x48140a74:0x60008
    pinmux: 0x48140a78:0x60008
    pinmux: 0x48140a7c:0x40008
    pinmux: 0x48140a80:0x8
    pinmux: 0x48140a84:0x8
    pinmux: 0x48140a88:0x8
    pinmux: 0x48140a8c:0x60080
    pinmux: 0x48140a90:0x60080
    pinmux: 0x48140a94:0x60080
    pinmux: 0x48140a98:0x60000
    pinmux: 0x48140a9c:0x60000
    pinmux: 0x48140aa0:0x40000
    pinmux: 0x48140aa4:0x40000
    pinmux: 0x48140aa8:0x40000
    pinmux: 0x48140aac:0x40000
    pinmux: 0x48140ab0:0x60000
    pinmux: 0x48140ab4:0x40000
    pinmux: 0x48140ab8:0x40000
    pinmux: 0x48140abc:0x40001
    pinmux: 0x48140ac0:0x40001
    pinmux: 0x48140ac4:0x40001
    pinmux: 0x48140ac8:0x40080
    pinmux: 0x48140acc:0x40001
    pinmux: 0x48140ad0:0x40001
    pinmux: 0x48140ad4:0x40001
    pinmux: 0x48140ad8:0x40001
    pinmux: 0x48140adc:0x40001
    pinmux: 0x48140ae0:0x40001
    pinmux: 0x48140ae4:0x40001
    pinmux: 0x48140ae8:0x40001
    pinmux: 0x48140aec:0x40001
    pinmux: 0x48140af0:0x40001
    pinmux: 0x48140af4:0x40001
    pinmux: 0x48140af8:0x40001
    pinmux: 0x48140afc:0x40001
    pinmux: 0x48140b00:0x40001
    pinmux: 0x48140b04:0x40001
    pinmux: 0x48140b08:0x40001
    pinmux: 0x48140b0c:0x40001
    pinmux: 0x48140b10:0x40001
    pinmux: 0x48140b14:0x40001
    pinmux: 0x48140b18:0x40001
    pinmux: 0x48140b1c:0x40001
    pinmux: 0x48140b20:0x40001
    pinmux: 0x48140b24:0x40001
    pinmux: 0x48140b28:0x40001
    pinmux: 0x48140b2c:0x40004
    pinmux: 0x48140b30:0x40004
    pinmux: 0x48140b34:0x40004
    pinmux: 0x48140b38:0x40004
    pinmux: 0x48140b3c:0x40004
    pinmux: 0x48140b40:0x40004
    pinmux: 0x48140b44:0x40004
    pinmux: 0x48140b48:0x40004
    pinmux: 0x48140b4c:0x40004
    pinmux: 0x48140b50:0x40004
    pinmux: 0x48140b54:0x40004
    pinmux: 0x48140b58:0x40004
    pinmux: 0x48140b5c:0x40004
    pinmux: 0x48140b60:0x40004
    pinmux: 0x48140b64:0x40004
    pinmux: 0x48140b68:0x40004
    pinmux: 0x48140b6c:0x40004
    pinmux: 0x48140b70:0x40004
    pinmux: 0x48140b74:0x40004
    pinmux: 0x48140b78:0x40004
    pinmux: 0x48140b7c:0x40004
    pinmux: 0x48140b80:0x40004
    pinmux: 0x48140b84:0x40004
    pinmux: 0x48140b88:0x40004
    pinmux: 0x48140b8c:0x60004
    pinmux: 0x48140b90:0x60004
    pinmux: 0x48140b94:0x40004
    pinmux: 0x48140b98:0x60004
    pinmux: 0x48140b9c:0x40001
    pinmux: 0x48140ba0:0x60001
    pinmux: 0x48140ba4:0x60001
    pinmux: 0x48140ba8:0x40001
    pinmux: 0x48140bac:0x40001
    pinmux: 0x48140bb0:0x40001
    pinmux: 0x48140bb4:0x40001
    pinmux: 0x48140bb8:0x40001
    pinmux: 0x48140bbc:0x40001
    pinmux: 0x48140bc0:0x40001
    pinmux: 0x48140bc4:0x40001
    pinmux: 0x48140bc8:0x40010
    pinmux: 0x48140bcc:0x40001
    pinmux: 0x48140bd0:0x40001
    pinmux: 0x48140bd4:0x40001
    pinmux: 0x48140bd8:0x40001
    pinmux: 0x48140bdc:0x40010
    pinmux: 0x48140be0:0x40010
    pinmux: 0x48140be4:0x40010
    pinmux: 0x48140be8:0x40010
    pinmux: 0x48140bec:0x40010
    pinmux: 0x48140bf0:0x40010
    pinmux: 0x48140bf4:0x40010
    pinmux: 0x48140bf8:0x40010
    pinmux: 0x48140bfc:0x40010
    pinmux: 0x48140c00:0x40010
    pinmux: 0x48140c04:0x40010
    pinmux: 0x48140c08:0x40080
    pinmux: 0x48140c0c:0x60000
    pinmux: 0x48140c10:0x60000
    pinmux: 0x48140c14:0x50000
    pinmux: 0x48140c18:0x60001
    pinmux: 0x48140c1c:0x60001
    pinmux: 0x48140c34:0x40001‎

    Thanks,

    Ran

  • I thought of trying my luck with emac #1 on linux maybe, 

    But the porting guide is not too clear with regards to the following steps:

    • In kernel Phy ID should be set in arch/arm/mach-omap2/devices.c:struct cpsw_slave_data cpsw_slaves[]
    • Remove runtime phy id update in devices.c:ti814x_cpsw_init()

    1. Should I do the porting in kernel for the RMII even though the u-boot already initialized the emac for RMII ?
    2. phy ID = 0 is used with emac 1 which is RMII, does it mean I should put in cpsw_slaves[0] .phy_id = "0:00", (instead of .phy_id = "0:01" ) ? Why the correct phy_id is relevant only for RMII (according to this section) , and for RGMII too ? 

    3. the second emac is rgmii, should I remove the phy id update only for cpsw_slaves[1] (and leave the update for cpsw_slaves[0] ) ?

    Thanks,

    Ran

  • Hi Pavel,

    I also don't succeed with getting it to work on Linux.

    I also tried to figure out the meaning of the following lines in PSP

    CPSW RMII Phy

    While a PHY is populated on the board, its address on the MDIO bus is to be noted. This is to be supplied as a mask to the CPSW driver platform data for probing the PHY by the MDIO bus framework. For example, if the PHY address on the bus is 2 (in decimal), then this goes into the phy_mask of the cpsw_mdio_device as 0x04 (bit position/weight represents the PHY address). Please refer arch/arm/mach-omap2/devices.c and drivers/net/cpsw.c

    What is the meaning of the above, do I need to set phy_id or phy_mask ? Does it mean that phy_id address is set as described in the lines or phy_mask (I don't find any such argument).

    Regards,

    Ran

  • Ran,

    Ran S. said:
    I have tried to change the setting of this pins to output (you can see it below in yellow color), but I still get no response from ping. Is there some other method or something I can try ? I have the EVM, maybe I should try to configure it as RMII in emac #1 , or is that not possible ? Is there any method to try solve this ?

    No, I do not think you can try with RMII on the DM814x EVM, as EVM has ethernet PHY AR8031, which is stated as RGMII/SGMII.

    From the pinmux you have sent, I see you are not trying with EMAC1 RMII M0 mode. Can you try configuring as below:

    emac_rmrefclk PINCNTL232 = 0x40001

    emac1_rmcrsdv_m0 PINCNTL255 = 0x40002

    emac1_rmrxd0_m0 PINCNTL252 = 0x40002

    emac1_rmrxd1_m0 PINCNTL253 = 0x40002

    emac1_rmrxer_m0 PINCNTL254 = 0x40002

    emac1_rmtxd0_m0 PINCNTL256 = 0x2

    emac1_rmtxd1_m0 PINCNTL257 = 0x2

    emac1_rmtxen_m0 PINCNTL258 = 0x2

    Regards,
    Pavel

  • Hi Pavel,

    Thanks very much for the quick response. 

    I'm not sure I understand your suggestion. In order to do this I need to physically connect the ethernet to other pins on board, right ?
    I'm not sure I will be able to do that ( PINCNTL252- PINCNTL258 are used for GPMC in my board as you can see from pinmux table). I have sent you the complete pinmux configuration in previous post. As you can see the relevant pins for emac1 are as following:

    MUX_VAL(PINCNTL157, (IEN | IPD | FCN4 )) /* EMAC[1]_RMRXER_MUX1 */\
    MUX_VAL(PINCNTL158, (IEN | IPU | FCN4 )) /* EMAC[1]_RMRXD[1]_MUX1 */\
    MUX_VAL(PINCNTL159, (IEN | IPU | FCN4 )) /* EMAC[1]_RMRXD[0]_MUX1 */\
    MUX_VAL(PINCNTL160, (IEN | IPD | FCN4 )) /* EMAC[1]_RMCRSDV_MUX1 */\
    MUX_VAL(PINCNTL161, (IDIS | IPD | FCN4 )) /* EMAC[1]_RMTXD[0]_MUX1 */\
    MUX_VAL(PINCNTL162, (IDIS | IPD | FCN4 )) /* EMAC[1]_RMTXD[1]_MUX1 */\
    MUX_VAL(PINCNTL163, (IDIS | IPD | FCN4 )) /* EMAC[1]_RMTXEN_MUX1 */\

    MUX_VAL(PINCNTL232, (IEN | IPD | FCN1 )) /* EMAC_RMREFCLK */

    Do you think there might be some problem with these pins , and I should try to replace them to the other pins option for emac1?

    Regards,

    Ran

  • Ran,

    Ran S. said:
    Do you think there might be some problem with these pins , and I should try to replace them to the other pins option for emac1?

    If you are sure that you have connect EMAC1 MUX1 pins, then these should be fine. I noticed in your EMAC1 RMII MUX1 pins, that you have:

    emac1_rmrxd0_m1 PINCNTL159 = 0x60008 -> can you try with 0x4_0008?

    emac1_rmrxd1_m1 PINCNTL158 = 0x60008 -> can you try with 0x4_0008?

    Regards,
    Pavel

  • Ran,

    What is your ethernet PHY that you have connected to EMAC1? In DM814x EVM, we have AR8031. Have you check that PHY is supporting RMII mode?

    Regards,
    Pavel

  • Hi Pavel,

    Thanks very much for the suggestions.

    We are using KSZ8091RNDIA which supports RMII,
    If you are also familiar with other tests that should be done for checking  RMII connectivity/link please tell me. Do you think Mistral loopback test (used for RGMII) can somehow be used for RMII ? 

    I will check the issues you raised and get back to you. 
    Thanks a lot,

    Ran

  • Ran,

    Ran S. said:
    Do you think Mistral loopback test (used for RGMII) can somehow be used for RMII ? 

    You can try it.

    Check also that you have valid 50MHz clock source, needed for RMII mode to work properly. DM814x can be set to either source this 50MHz clock (though the SATA SerDes PLL) or receive it through the refclk pin. See TRM for more info.

    Regards,
    Pavel

  • Pavel,

    Thanks very much for assistance, now ethernet works in u-boot. :)

    Regards,

    Ran