We need to generate a 24.576MHz clock from the DEVOSC at 20MHz. This is a requirement. No other solution will work. We intended for the TI8148 Audio PLL to do this. We have tried the following values in u-boot:
AUDIO_M=768, AUDIO_N=24, AUDIO_M2=25 and AUDIO_CLKCTRL=0x801
The pll will not start. The processor hangs in the audio_pll_config() function. I do not see anything in the TRM or Datasheet indicating that this will not work.
Are there other registers or bits that must be changed to use the PLL with the values AUDIO_M=768, AUDIO_N=24, AUDIO_M2=25?
If these values do not work then are there other PLL values known to work that give any exact multiple of 12.288MHz from the 20MHz DEVOSC clock?
Thanks,
Rob aka Philip Flopp