DM8148: Audio PLL at 24.576MHz from DEVOSC 20MHz

Haven't tried it in u-boot, but the audio PLL locks without problem for me using those parameters, and they are well within the valid range as far as I can tell.

Can you dump the PLL's registers while it's stuck in pll_config? (10 words at 0x481c5230)

Ah actually M2 is required to be even to avoid an asymmetric clock output; though this wouldn't affect PLL locking. In any case, since you're generating 24.576 MHz now you can just use M2=50 to get 12.228 MHz.  If you prefer 24.576 MHz then you can set M=1536.

There's also very little choice here: you have a factor of 5⁴ you need to divide out, and since the M2 needs to be even and < 128 it can only take 5² leaving the other 5² to the predivider, so that forces N=24 and you get (M,M2)=(768,50) as minimal solution and you can optionally scale those by (2,1), (2,2), (3,1), but anything higher would exceed some limit.

Hello,

I tried with these values (AUDIO_N=24, AUDIO_M=768, AUDIO_M2=25, AUDIO_CLKCTRL=0x801) in u-boot on DM814x EVM, and the u-boot loads fine, it does not stuck/hang.

clocks_ti814x.h

/* Put the pll config values over here */
#define AUDIO_N        24//19
#define AUDIO_M        768//500
#define AUDIO_M2    25//2
#define AUDIO_CLKCTRL    0x801

As Matthijs stated, the M2 is post divider, it is not involved in the lock sequence (it is not part of the loop), thus wouldn't affect PLL locking. Odd value of M2 will result in Non-50% duty cycle, and the drawback of this is: any half cycle paths on this clock, timing will be impacted. Pulse width requirements for clock will also get impacted.

Regards,
Pavel

Pavel Botev said:

AUDIO_N=19,

typo: you meant 24 (your code shows it correctly).

For reference, since I noticed my previous post may have been a bit unclear, the (exhaustive) list of choices of parameters that yield some integer multiple of 12.288 MHz from 20 MHz devosc within the constraints of the PLL (including the requirement for even M2) are:

Configuration parameters highlighted in yellow.  BTW, I just noticed that the pll_config() function in u-boot ignores the supplied clkctrl value and automatically determines whether HS2 (0x800) or HS1 (0x1000) should be selected.

Matthijs van Duin said:

AUDIO_N=19,

typo: you meant 24 (your code shows it correctly).

[/quote]

I edit my first post. Thanks for the note.

Hello,

I have similar issue, but the oscillator in our board is 25.576M (and we need to generate 24.576MHz clock )

I have tried several values for :
AUDIO_M, AUDIO_N, AUDIO_M2 but it only hangs or no change in behaviour.

Does anyone have any idea ?

Regards,

Ran

Ran Shalit said:

25.576M (and we need to generate 24.576MHz

Wow that is a very awkward clock ratio...

Out of curiosity I checked whether it's possible to configure this ratio (3072 / 3197) exactly... but it is not. The prime factorization of the denominator is 23 * 139, and you would need to achieve that with dividers N and M2, but 139 does not even fit in M2 (never mind that M2 should also be even) and putting it into N would result in a reference clock far below the valid range.

The values Pavel suggested look like an excellent alternative though: my by calculation it yields a clock rate of 24.5760001532 MHz... very nice!

Matthijs van Duin,

Thanks,

 25.476 is a typo :(

 I actually ment:  24.576 oscillator.

Ran,

Ran Shalit said:

Are the values you've suggested are for oscillator: 24.576Mhz ? (I had typo in the previous message) ?

No, the values are for oscillator 25.576MHz, I was not aware you made a typo.

So finally, you have 24.576MHz oscillator going to Audio PLL, and you need to have 24.576MHz output of the Audio PLL?

BR
Pavel

Hi Pavel,

Can you please see here: (I've answered some details you've requested there)

Regards,

Ran

Ran Shalit said:

N = 0
M2 = 1
M = 1

This violates all sorts of specs: the PLL reference clock (= input clock / (N+1)) needs to be in range 0.5 MHz - 2.5 MHz. Also, M2 needs to be even for most PLLs (including the Audio PLL). The minimum value of M is 2. The dco clock (= reference clock * M) must be in range 0.5 - 2.0 GHz. 

To get output = input you could just put the PLL into bypass (with bypass divider set to 1), though this probably results in an asymmetrical clock so it would be preferred to enable the PLL values (for example) N=24, M=650, M2=26. (sddiv = 3)

It would have been preferred if you connected the 24.576 osc to the "auxosc" (aka osc 1) of the processor and a separate 20 MHz crystal as devosc (osc 0). Auxosc can be routed to the McASPs directly, bypassing the PLLs.

Also, having devosc at a value other than 20 MHz will cause all sorts of problems: the RTC will run at the wrong speed, nearly all clocks will need non-default config, you will need an external 100 MHz reference clock to be able to use SATA, PCIe, or Ethernet, and many boot modes will not work since ROM assumes devosc is 20 MHz.