Hi Pavel,
After entering linux,The chip_select pin SPI[0]_CS[3] is always low.But I want to set it to high.
How to do ?Configure which register , And where ?Thank you .
BR
Bob
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Bob,
I will have a look on your questions and provide you me feedback when I have something.
Regards,
Pavel
Hi Pavel,
I have double checked the pinmux and it is right.
root@dm814x-evm:/mnt/omap_mux# cat uart0_dcdn
name: uart0_dcdn.spi0_cs3 (0x48140924/0x924 = 0x20010), b NA, t NA
mode: OMAP_PIN_OUTPUT | OMAP_MUX_MODE0
signals: uart0_dcdn | uart3_rxd_mux0 | NA | NA | spi0_cs3 | i2c2_scl_mux0 | mmc1_pow | gpio1_2
BR
Bob
Bob,
The SPI chip select 3 is active low, which means that when it is low, you have selected the slave device connected on this chip select. Do you want to unselect/disable the slave device connected to SPI chip select 3?
Regards,
Pavel
Bob,
bob lee said:0x48140924/0x924 = 0x20010
Make sure you are aligned with the DM814x Silicon Errata, advisory 2.1.87 and 2.1.88.
Regards,
Pavel
Hi Pavel,
It will be active low in order to select the chip when we read/write SPI device.
Now it is ok now after add the below code to the struct ti8148_spi_slave_info[].
{
.modalias = "spidev",
.irq = -1,
.max_speed_hz = 500000,
.bus_num = 1,
.chip_select = 3,
.mode = SPI_MODE_3,
},
I try to read/write DS26521 chip now.But I don't know how to do.
f
Would you give me some suggestions ? Thank you very much.
BR
Bob
Hi Pavel,
For example,if I want to read DS26521 chip ID,but how to send the command to the chip ?
I find the Device Identification register (IDR) is 0x0F8 and "1" stands for read.
So I could send 0x10F8 to the register.Is it right?
BR
Bob
Bob,
bob lee said:The chip_select pin SPI[0]_CS[3] is always low.But I want to set it to high.
How to do ?Configure which register
Have you tried to disable the channel associated with the chip select signal?
See DM814x TRM:
22.2.2.3.3 Programmable SPI Enable (SPI_SCS[n])
The polarity of the SPI_SCS[n] signals is programmable. SPI_SCS[n] signals can be active high or low.
The assertion of the SPI_SCS[n] signals is programmable: SPI_SCS[n] signals can be manually asserted
or can be automatically asserted.
22.2.3.1 Dedicated Resources Per Channel
– SPI_SCS[n] polarity, programmable with the bit EPOL.
– SPI_SCS[n] kept active between words, programmable with the bit FORCE.
The configuration parameters SPI_SCS[n] polarity, Turbo mode, SPI_SCLK phase and SPI_SCLK polarity can be loaded in the (I)CONF register only when the channel is disabled.
22.2.3.6.2 Keep SPI_SCS[n] Active Mode (Force SPI_SCS[n])
Continuous transfers are manually allowed by keeping the SPI_SCS[n] signal active for successive SPI words transfer. Several sequences (configuration/enable/disable of the channel) can be run without deactivating the SPI_SCS[n] line.
The state of the SPI_SCS[n] signal is programmable.
– Writing 1 into the bit FORCE of the register MCSPI_CH(I)CONF drives high the SPI_SCS[n] line when MCSPI_CHCONF(I)[EPOL] is cleared to 0, and drives it low when MCSPI_CHCONF(I)[EPOL] is set.
– Writing 0 into the bit FORCE of the register MCSPI_CH(I)CONF drives low the SPI_SCS[n] line when MCSPI_CHCONF(I)[EPOL] is cleared to 0, and drives it high when MCSPI_CHCONF(I)[EPOL] is set.
A single channel is enabled (MCSPI_CH(I)CTRL[En] set to 1) . The first enabled channel activates the
SPI_SCS[n] line.
Once the channel is enabled, the SPI_SCS[n] signal is activated with the programmed polarity.
At the end of the last SPI word, the channel must be deactivated (MCSPI_CH(I)CTRL[En] is cleared to 0)
and the SPI_SCS[n] can be forced to its inactive state (MCSPI_CH(I)CONF[Force]).
Regards,
Pavel
Bob,
bob lee said:It will be active low in order to select the chip when we read/write SPI device
Correct.
bob lee said:I try to read/write DS26521 chip now.
Refer to the below resources for examples:
/drivers/mtd/devices/m25p80.c
/drivers/spi/omap2_mcspi.c
/Documentation/spi/spi-summary spidev spidev_test.c spidev_fdx.c
http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/716/t/297161.aspx
http://e2e.ti.com/support/embedded/linux/f/354/t/373988.aspx
http://e2e.ti.com/support/embedded/linux/f/354/t/158070.aspx
Regards,
Pavel