Hi,
We used to have a design using DM8107's EMAC1 RMII interface to RTL8201, it worked fine. But we want to upgrade the product to work on 1000M/Giga interface, so change the design to EMAC0 RGMII interface with RTL8211E-VL giga-phy. But, it doesn't work.
1. The Uboot version is TI813X-GP rev 1.1, At Uboot stage, the network mesage..
Net: Ethernet clocking: 0x0
Detected MACID:7c:66:9d:fa:c4:ae
cpsw
Hit any key to stop autoboot: 0
------- We Try to set ip and ping to outside 192.168.1.29 -----------
UBOOT # set ipaddr 192.168.1.177;ping 192.168.1.29
link up on port 0, speed 100, full duplex
Using cpsw device
ping failed; host 192.168.1.29 is not alive
2. At Kernel booting stage, the message...
- When it connects to a Giga LAN, the message from console as below.
[ 14.650000] CPSW phy found : id is : 0x1cc915
[ 14.660000]
[ 14.660000] CPSW phy found : id is : 0x1cc915
[ 16.650000] PHY: 0:01 - Link is Up - 1000/Full
[ 16.650000] PHY: 0:00 - Link is Up - 1000/Full
[ 25.360000] ip_tables: (C) 2000-2006 Netfilter Core Team
[ 25.470000] nf_conntrack version 0.5.0 (9724 buckets, 38896 max)
[ 67.360000] NET: Registered protocol family 10
- When it connects to a 10/100M LAN, the message from console as below.
[ 14.750000] CPSW phy found : id is : 0x1cc915
[ 14.760000]
[ 14.760000] CPSW phy found : id is : 0x1cc915
[ 16.750000] PHY: 0:01 - Link is Up - 100/Full
[ 16.750000] PHY: 0:00 - Link is Up - 100/Full
[ 25.450000] ip_tables: (C) 2000-2006 Netfilter Core Team
[ 25.570000] nf_conntrack version 0.5.0 (9724 buckets, 38896 max)
[ 67.450000] NET: Registered protocol family 10
3. The signal measured form oscilloscope...
- The clock frequency is 500KHz on MDCLK.
- The frequency of EMAC[0]_RGRXC is 25MHz at 10/100M connection and 125MHz at Giga connection, but can't get any frequency output form EMAC[0]_RGTXC.
- There is a short signal puls around 5us~10us on EMAC[0]_RGRXCTL at 10/100M connection, but nothing on EMAC[0]_RGTXCTL.
- There is a short signal puls around 500ns on EMAC[0]_RGRXCTL at 1000M connection, but nothing on EMAC[0]_RGTXCTL.
We also change the DM8107's GMII_SEL register from 0x30a to 0x33a or vice versa to enable/disable internal delay, but it still doesn't work.
The pin mux for RGMII lists as below..
/*configure pin mux for rmii_refclk,mdio_clk,mdio_d */
val = PAD232_CNTRL;
PAD232_CNTRL = (volatile unsigned int) (BIT(18) | BIT(0));
val = PAD233_CNTRL;
PAD233_CNTRL = (volatile unsigned int) (BIT(19) | BIT(17) | BIT(0));
val = PAD234_CNTRL;
PAD234_CNTRL = (volatile unsigned int) (BIT(19) | BIT(18) | BIT(17) |
BIT(0));
/* setup rgmii0/rgmii1 pins here */
val = PAD235_CNTRL; /*rgmii0_rxc*/
PAD235_CNTRL = (volatile unsigned int) (BIT(18) | BIT(0));
val = PAD236_CNTRL; /*rgmii0_rxctl*/
PAD236_CNTRL = (volatile unsigned int) (BIT(18) | BIT(0));
val = PAD237_CNTRL; /*rgmii0_rxd[2]*/
PAD237_CNTRL = (volatile unsigned int) (BIT(18) | BIT(0));
val = PAD238_CNTRL; /*rgmii0_txctl*/
PAD238_CNTRL = (volatile unsigned int) BIT(0);
val = PAD239_CNTRL; /*rgmii0_txc*/
PAD239_CNTRL = (volatile unsigned int) BIT(0);
val = PAD240_CNTRL; /*rgmii0_txd[0]*/
PAD240_CNTRL = (volatile unsigned int) BIT(0);
val = PAD241_CNTRL; /*rgmii0_rxd[0]*/
PAD241_CNTRL = (volatile unsigned int) (BIT(18) | BIT(0));
val = PAD242_CNTRL; /*rgmii0_rxd[1]*/
PAD242_CNTRL = (volatile unsigned int) (BIT(18) | BIT(0));
val = PAD243_CNTRL; /*rgmii1_rxctl*/
PAD243_CNTRL = (volatile unsigned int) (BIT(18) | BIT(0));
val = PAD244_CNTRL; /*rgmii0_rxd[3]*/
PAD244_CNTRL = (volatile unsigned int) (BIT(18) | BIT(0));
val = PAD245_CNTRL; /*rgmii0_txd[3]*/
PAD245_CNTRL = (volatile unsigned int) BIT(0);
val = PAD246_CNTRL; /*rgmii0_txd[2]*/
PAD246_CNTRL = (volatile unsigned int) BIT(0);
val = PAD247_CNTRL; /*rgmii0_txd[1]*/
PAD247_CNTRL = (volatile unsigned int) BIT(0);
val = PAD248_CNTRL; /*rgmii1_rxd[1]*/
PAD248_CNTRL = (volatile unsigned int) (BIT(18) | BIT(0));
val = PAD249_CNTRL; /*rgmii1_rxc*/
PAD249_CNTRL = (volatile unsigned int) (BIT(18) | BIT(0));
val = PAD250_CNTRL; /*rgmii1_rxd[3]*/
PAD250_CNTRL = (volatile unsigned int) (BIT(18) | BIT(0));
val = PAD251_CNTRL; /*rgmii1_txd[1]*/
PAD251_CNTRL = (volatile unsigned int) (BIT(0));
val = PAD252_CNTRL; /*rgmii1_txctl*/
PAD252_CNTRL = (volatile unsigned int) (BIT(0));
val = PAD253_CNTRL; /*rgmii1_txd[0]*/
PAD253_CNTRL = (volatile unsigned int) (BIT(0));
val = PAD254_CNTRL; /*rgmii1_txd[2]*/
PAD254_CNTRL = (volatile unsigned int) (BIT(0));
val = PAD255_CNTRL; /*rgmii1_txc*/
PAD255_CNTRL = (volatile unsigned int) (BIT(0));
val = PAD256_CNTRL; /*rgmii1_rxd[0]*/
PAD256_CNTRL = (volatile unsigned int) (BIT(18) | BIT(0));
val = PAD257_CNTRL; /*rgmii1_txd[3]*/
PAD257_CNTRL = (volatile unsigned int) (BIT(0));
val = PAD258_CNTRL; /*rgmii1_rxd[2]*/
PAD258_CNTRL = (volatile unsigned int) (BIT(18) | BIT(0));
Can someone please give us a suggestion to fix this issue.
Thanks & regards
