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Fine tune DEEMP and SWING for PCIe on DM8148

Hi all,

I used DM814x EZSDK and I did the PCIe eye diagram test on DM8148.

But I encountered the fail status on voltage amplitude.

I found SERDES_TXCFG0 register and try to fine tune DEEMP and SWING fields.

I executed following command, but there is no change in voltage amplitude when I did the PCIe eye diagram test.

====================================

# ./memtool -32 0x510003a4=0x01001600

# ./memtool -32 0x510003a4=0x0100F600

# ./memtool -32 0x510003a4=0x01010600

# ./memtool -32 0x510003a4=0x0101F600

====================================

Did fine tune DEEMP and SWING fields for PCIe have the sequence must be followed?

Could anyone please give me some hints?

Thanks in advance.

Sherry

  • Sherry,

    I see you are using memtool, can you also try with devmem2 tool? Can you also verify that the value you wrote is properly set in the register?

    The default setting enables de-emphasis and is full swing.

    BR
    Pavel
  • Hi Pavel,

    I used "devmem2" to read 0x510003a4. The value at 0x510003a4 is 0x0101F600.

    As below test, I think the value that I wrote was setting successfully. (Modified 0x0101F600 to 0x0101E000)

    I used "devmem2" to execute following commands to tune  DEEMP and SWING.

    DEEMP tuning:

    ===========================================

    #./devmem2 0x510003a4 w 0x01003600

    #./devmem2 0x510003a4 w 0x01021600

    #./devmem2 0x510003a4 w 0x0101F600

    #./devmem2 0x510003a4 w 0x0103F600

    ===========================================

    SWING tuning:

    ===========================================

    #./devmem2 0x510003a4 w 0x0101E000

    #./devmem2 0x510003a4 w 0x0101E200

    #./devmem2 0x510003a4 w 0x0101E400

    #./devmem2 0x510003a4 w 0x0101E600

    #./devmem2 0x510003a4 w 0x0101E800

    #./devmem2 0x510003a4 w 0x0101EA00

    #./devmem2 0x510003a4 w 0x0101EC00

    #./devmem2 0x510003a4 w 0x0101EE00

    #./devmem2 0x510003a4 w 0x0101F000

    #./devmem2 0x510003a4 w 0x0101F200

    #./devmem2 0x510003a4 w 0x0101F400

    #./devmem2 0x510003a4 w 0x0101F600

    #./devmem2 0x510003a4 w 0x0101F800

    #./devmem2 0x510003a4 w 0x0101FA00

    #./devmem2 0x510003a4 w 0x0101FC00

    #./devmem2 0x510003a4 w 0x0101FE00

    ===========================================

    But there is still no change in voltage amplitude when I did the PCIe eye diagram test.

    The PCIe eye diagram test result as below. 

    Is there any suggestions to improve eye diagram test result(hardware or software)?

    Thanks in advance.

    B.R.

    Sherry

  • Hi Sherry,

    We would recommend that you re-measure the eye diagram using the TI software/driver. This will eliminate any possible issue in the device configuration.

    Make sure you are using the latest u-boot and linux kernel available at:

    http://arago-project.org/git/projects/u-boot-omap3.git?p=projects/u-boot-omap3.git;a=shortlog;h=refs/heads/ti81xx-master

    http://arago-project.org/git/projects/?p=linux-omap3.git;a=shortlog;h=refs/heads/ti81xx-master

    Make a try with the PCIe example from EZSDK 5.04.01.04:
    ti-ezsdk_dm814x-evm_5_05_01_04/example-applications/linux-driver-examples-psp04.04.00.01/pcie/

    Make sure you are aligned with the below wiki pages:

    http://processors.wiki.ti.com/index.php/TI81XX_PCIe_FAQs
    http://processors.wiki.ti.com/index.php/TI81XX_PSP_PCI_Express_Root_Complex_Driver_User_Guide
    http://processors.wiki.ti.com/index.php/TI81XX_PSP_PCI_Express_Endpoint_Driver_User_Guide
    http://processors.wiki.ti.com/index.php/TI81XX_PSP_PCI_Express_Endpoint_Boot_Driver_User_Guide
    http://processors.wiki.ti.com/index.php/TI81XX_PSP_U-Boot_PCIe_Boot_User_Guide

    Regards,
    Pavel
  • Pavel,

    To adjust SERDES_TXCFGx.DEEMP (De-emphasis) register bit value to reduce PCIe output drivability, is there any specific configuration sequence to fllow?  Or we can just use "devmem2" or "memtool" command in Linux to adjust it directly?  Because we are not seeing any change in  the output waveform when we changed DEEMP value. We have confirmed the DEEMP value is changed in the register by reading it back.

    Is DEEMP function ever validated during device test/characterization?

    Regards - Edward

  • Edward,

    Edward Yao said:

    To adjust SERDES_TXCFGx.DEEMP (De-emphasis) register bit value to reduce PCIe output drivability, is there any specific configuration sequence to fllow?  Or we can just use "devmem2" or "memtool" command in Linux to adjust it directly?  Because we are not seeing any change in  the output waveform when we changed DEEMP value. We have confirmed the DEEMP value is changed in the register by reading it back.

    Is DEEMP function ever validated during device test/characterization?

    Let me check with the PCIe team. I will come back to you when/if I have something.

    BR
    Pavel

  • Edward,

    I sent you e-mail regarding the PCIe eye diagram.

    Regards,
    Pavel