DM8127 can,t boot after load u-boot.min.uart

Could you try the uboot.min.nand for uart boot?

Holy,

 

holy said:

Now I designed a board use DM8127 refer to the appro design，RDK vision is 3.5.0 . When “CCCC” characters appear on TeraTerm ，I load the u-boot.min.uart to the board，but after finished load ,it can,t  appear  prompt “TI-MIN#” ,it doesn,t work!

See if you are aligned with the below flow:

holy said:

the appro desigener used four 128M DDR3  altogether 512M，but I used two 128M DDR3  altogether 256M，and used the same DDR3. is it related to the matter?

It might be. See the below wiki:

processors.wiki.ti.com/index.php/Understanding_u-boot-min_startup_for_DM814x

Check if the flow stuck at the DDR init function in board/ti/ti8148/evm.c s_init()

Have you made the needed changes in your DMM LISA MAP registers?

holy said:

I must to modify anywhere? Meanwhile ,I made  a SD card to boot the board ,it could  work on the appro board ,but when I used on my board ,changed the boot mode to SD mode ,power on , nothing appear on the console ,it can,t work too, why?

See the below wiki page:

Regards,
Pavel

yes，I tried, it could,t work too

Pavel Botev:
thanks for your answer!
Check if the flow stuck at the DDR init function in board/ti/ti8148/evm.c s_init()
Have you made the needed changes in your DMM LISA MAP registers?
-- I used two 128M DDR3 altogether 256M, so I only used EMIF0 to connect two pieces DDR3, EMIF1 is empty.
so ,in /home/dm8127/Source/ti_tools/ipnc_psp_arago/u-boot/arch/arm/include/asm/arch-ti81xx/ddr_defs_ti816x.h, I modified as below:

* TI814X PG2.1 DMM LISA MAPPING
* 1G contiguous section with 128-byte interleaving
*/
#define PG2_1_DMM_LISA_MAP__0 0x0
#define PG2_1_DMM_LISA_MAP__1 0x0
//#define PG2_1_DMM_LISA_MAP__2 0x805C0300
//#define PG2_1_DMM_LISA_MAP__3 0xA05C0300
#define PG2_1_DMM_LISA_MAP__2 0x0 //modified
#define PG2_1_DMM_LISA_MAP__3 0xA0400100 //256-MB section,No interleaving,Mapped on SDRC 0 only (not interleaved)

in board/ti/ti8148/evm.c s_init()
__raw_writel(0x2, CM_DEFAULT_EMIF_0_CLKCTRL); /*Enable EMIF0 Clock*/
//__raw_writel(0x2, CM_DEFAULT_EMIF_1_CLKCTRL); /*Enable EMIF1 Clock*/ // modified , disable EMIF1 CLOCK

then I made the u-boot.min.uart ,it still can,t work,after load it by the TeraTerm,nothing appear on the console.
so somewhere else must to change ?

Hi，Pavel Botev：
when I modified DMM_LISA_MAP like this:
#define PG2_1_DMM_LISA_MAP__2 0x80400100 //modified
#define PG2_1_DMM_LISA_MAP__3 0xA0400100 //modified
then make the u-boot.min.uart,it could work now, after I load it to the board,then appear prompt “TI-MIN#”.
but when I write the "u-boot.min.nand" and "u-boot.bin" to nand flash ,then changed the boot mode to nand boot , ,power on , nothing appear on the console once again!
I write the u-boot.min.nand and u-boot.bin refer to
processors.wiki.ti.com/.../TI81XX_PSP_UBOOT_User_Guide --- U-Boot UART support
so why?

Hi Holy,

holy said:

I used two 128M DDR3 altogether 256M, so I only used EMIF0 to connect two pieces DDR3, EMIF1 is empty.

Check the below DM814x patch, for DM8127 should be similar:

Regards,
Pavel

Holy,

holy said:

when I modified DMM_LISA_MAP like this:
#define PG2_1_DMM_LISA_MAP__2 0x80400100 //modified
#define PG2_1_DMM_LISA_MAP__3 0xA0400100 //modified
then make the u-boot.min.uart,it could work now, after I load it to the board,then appear prompt “TI-MIN#”.

Could you please provide full console log? Are you able then to load and start the 2nd stage u-boot (u-boot.bin) through the UART?

Regards,
Pavel