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configure 2Gib memory on DM8127

Hagai Moshe
Prodigy 120 points

hi all
I'm working on a project where I use the DM8127
The hardware I use is very similar to the appro IPNC DM8127 hardware.
One of the few things that are different is the memory, I use 2Gib instead of 512 Mb (the new memory is k4B4G16).

I've updated the file ddr_defs_ti814x.h:

#define PG2_1_DMM_LISA_MAP__0  0x0
#define PG2_1_DMM_LISA_MAP__1  0x0
#define PG2_1_DMM_LISA_MAP__2  0x0
#define PG2_1_DMM_LISA_MAP__3  0x807C0300

According to the board layout files A13 and A14 are connected between the DDR and the dm8127,

but I still seem to use only 512Mb of memory (I read the the same data from 0x80000000, 0xA0000000, 0xC0000000 and 0xE0000000)

I can see this problem both from the ARM (uboot) and from the DSP

I assume there is another configuration I need to change, but I can't find what it is.

Assuming the problem is software and not HW, What else can cause this problem?

Thanks,

Hagai

  • 0
    TI__Guru* 80190 points
    Hello,

    I will notify the IPNC team for help.

    BR
    Margarita
  • 0
    TI__Guru**** 170625 points
    Hagai,

    While waiting for IPNC team input, can you try with:

    1. Switch from 512 byte interleaving to 128 byte interleaving - is there any difference?

    2. Try with the below LISA MAP settings - is there any difference?

    #define PG2_1_DMM_LISA_MAP__0 0x0
    #define PG2_1_DMM_LISA_MAP__1 0x0
    #define PG2_1_DMM_LISA_MAP__2 0x80640300
    #define PG2_1_DMM_LISA_MAP__3 0xC0640320

    Regards,
    Pavel
  • 0 in reply to Pavel Botev
    Prodigy 120 points

    Hi Pavel.
    Thanks for your reply.
    I've already tried that configuration, I'll try it again just to make sure, but the last time I did It didn't work.

    Hagai.

  • 0 in reply to Hagai Moshe
    TI__Expert 8920 points

    8814.Feb20_1GB_memMap.zipHi,

     

    In the attached patch, there are modifications in the uboot for 1 GB memory.

    Can you make changes for 2 GB on the similar lines and do the DDR testing using uboot 'autotest' command.

     

    regards,

    Anand

  • 0 in reply to Anand Kulkarni71405
    Prodigy 120 points

    Hi Anand

    I couldn't even change to 1Gib configuration.

    after compiling and flashing the new uboot

    I tried to access the memory in address 0xA0003000 (memory that doesn't exist in the 512M configuration)

    When I did, I saw the same thing -  that address 0xA0000000 is maped to adress 0x80000000.

    that is what I wrote

    in file ti8148_ipnc.h:

    #if 0
     /**
      * Physical Memory Map
      */
     #define CONFIG_NR_DRAM_BANKS  2   /* we have 2 banks of DRAM */
     #define PHYS_DRAM_1     0x80000000 /* DRAM Bank #1 */
     #define PHYS_DRAM_1_SIZE   0x10000000 /* 256 MB */
     #define PHYS_DRAM_2     0xB0000000 /* DRAM Bank #2 */
     #define PHYS_DRAM_2_SIZE   0x10000000 /* 256 MB */
    #else
     #if defined(CONFIG_CMD_AUTOTEST)
      #define CONFIG_SYS_MEMTEST_SIZE 0x20000000 /* autotest memory size*/
     #endif
     /**
      * Physical Memory Map
      */
     #define CONFIG_NR_DRAM_BANKS  2   /* we have 2 banks of DRAM */
     #define PHYS_DRAM_1     0x80000000 /* DRAM Bank #1 */
     #define PHYS_DRAM_1_SIZE   0x20000000 /* 512 MB */
     #define PHYS_DRAM_2     0xA0000000 /* DRAM Bank #2 */
     #define PHYS_DRAM_2_SIZE   0x20000000 /* 512 MB */
    #endif

    in file ddr_defs_ti814x.h:

    #if 0
     /*
      * TI814X PG2.1 DMM LISA MAPPING
      * Two 256MB sections with 512-byte interleaving
      */
     #define PG2_1_DMM_LISA_MAP__0  0x0
     #define PG2_1_DMM_LISA_MAP__1  0x0
     #define PG2_1_DMM_LISA_MAP__2  0x805C0300
     #define PG2_1_DMM_LISA_MAP__3  0xA05C0300
    #else
     /*
      * TI814X PG2.1 DMM LISA MAPPING
      * 1 GB section with 512-byte interleaving
      */
     #define PG2_1_DMM_LISA_MAP__0  0x806C0300
     #define PG2_1_DMM_LISA_MAP__1  0x806C0300
     #define PG2_1_DMM_LISA_MAP__2  0x806C0300
     #define PG2_1_DMM_LISA_MAP__3  0x806C0300
    #endif

    my terminal output:

    root@dm814x-evm:/opt/ipnc/bin#
    root@dm814x-evm:/opt/ipnc/bin# ./mem_rdwr.out --rd a0003000

     [host]

     [host]  0xa0003000:
     [host]  FFFFFFFF
     [host]

     [host]
    root@dm814x-evm:/opt/ipnc/bin# ./mem_rdwr.out --rd 80003000

     [host]

     [host]  0x80003000:
     [host]  FFFFFFFF
     [host]

     [host]
    root@dm814x-evm:/opt/ipnc/bin# ./mem_rdwr.out --wr 80003000 123456

     [host]

     [host]  ORG 0x80003000: ffffffff

     [host]  NEW 0x80003000: 123456

     [host]
    root@dm814x-evm:/opt/ipnc/bin# ./mem_rdwr.out --rd a0003000

     [host]

     [host]  0xa0003000:
     [host]  00123456
     [host]

     [host]
    root@dm814x-evm:/opt/ipnc/bin# ./mem_rdwr.out --rd 80003000

     [host]

     [host]  0x80003000:
     [host]  00123456
     [host]

     [host]
    root@dm814x-evm:/opt/ipnc/bin#

  • 0 in reply to Hagai Moshe
    TI__Guru**** 170625 points
    Hagai,

    This might be DDR3 HW design malfunction. This is what I have in the DM814x TI EVM with u-boot:

    TI8148_EVM#md 0xa0003000 1
    a0003000: 969dbd16 ....
    TI8148_EVM#md 0x80030000 1
    80030000: 1ebf5d96 .]..
    TI8148_EVM#mw 0x80030000 123456
    TI8148_EVM#md 0x80030000 1
    80030000: 00123456 V4..
    TI8148_EVM#md 0xa0003000 1
    a0003000: 969dbd16 ....

    The DM814x TI EVM comes with 1GB DDR3 with the below u-boot settings:

    ti8148_evm.h

    /**
    * Physical Memory Map
    */
    #define CONFIG_NR_DRAM_BANKS 2 /* we have 2 banks of DRAM */
    #define PHYS_DRAM_1 0x80000000 /* DRAM Bank #1 */
    #define PHYS_DRAM_1_SIZE 0x20000000 /* 512 MB */
    #define PHYS_DRAM_2 0xA0000000 /* DRAM Bank #2 */
    #define PHYS_DRAM_2_SIZE 0x20000000 /* 512 MB */


    ddr_defs_ti814x.h

    /*
    * TI814X PG2.1 DMM LISA MAPPING
    * 1G contiguous section with 128-byte interleaving
    */
    #define PG2_1_DMM_LISA_MAP__0 0x0
    #define PG2_1_DMM_LISA_MAP__1 0x0
    #define PG2_1_DMM_LISA_MAP__2 0x0
    #define PG2_1_DMM_LISA_MAP__3 0x80640300


    Regards,
    Pavel
  • 0 in reply to Pavel Botev
    Prodigy 120 points

    Pavel.
    It really could be a DDR design mistake.
    regardless to that you have a little mistake in  the read write

    you should read/write to 0x80003000  not  0x80030000  (watch the possition of the number 3).

  • 0 in reply to Hagai Moshe
    TI__Guru**** 170625 points

    Hagai,

    Hagai Moshe said:

    regardless to that you have a little mistake in  the read write

    you should read/write to 0x80003000  not  0x80030000  (watch the possition of the number 3).

    You are correct. Below is the new u-boot log:

    Net:   <ethaddr> not set. Reading from E-fuse
    Detected MACID:90:d7:eb:d5:13:96
    cpsw
    Hit any key to stop autoboot:  0
    TI8148_EVM#md 0x4E000040 1
    4e000040: 00000000    ....
    TI8148_EVM#md 0x4E000044 1
    4e000044: 00000000    ....
    TI8148_EVM#md 0x4E000048 1
    4e000048: 00000000    ....
    TI8148_EVM#md 0x4E00004C 1
    4e00004c: 80640300    ..d.
    TI8148_EVM#md 0xa0003000 1
    a0003000: f4ff5fc3    ._..
    TI8148_EVM#md 0x80003000 1
    80003000: 86977d96    .}..
    TI8148_EVM#mw 0x80003000 123456
    TI8148_EVM#md 0x80003000 1
    80003000: 00123456    V4..
    TI8148_EVM#md 0xa0003000 1
    a0003000: f4ff5fc3    ._..

    When I set DMM_LISA_MAP_3/0x4E00004C to 0x80600100 (EMIF0 only used), I have the same as you.


    Regards,
    Pavel

  • 0 in reply to Pavel Botev
    Guru 10750 points

    Hi Pavel,

    Is there a gel file we can use to configure the 2Gb without using any RTOS, it could be for the ARM or the DSP,

    Many Thanks,

    HR

  • 0 in reply to HRi
    TI__Guru**** 170625 points

    HRi,

    Most of the DM814x GEL files are to configure DDR3 at 1GByte as DM814x TI EVM comes with 1GByte DDR3.

    I found only one GEL file (TI814x_ES_2x_evm_A8_ddr3_iss.gel) that is configuring DDR2 to 2Gbit/256MByte and DDR3 to 512MByte.

    TI814x_ES_2x_evm_A8_ddr3_iss.gel

    Regards,
    Pavel

  • 0 in reply to Hagai Moshe
    TI__Intellectual 810 points

    Hagai,

    Your settings for 2GB with 512 byte interleaving(your first post) looks correct, but Iam puzzled as to why it is not taking effect.

    Could you confirm that the changes you make in u-boot are indeed taking effect.

    Have you replaced both u-boot.min and u-boot after changin the LISA settings?

    Please read the LISA mapping registers from the u-boot prompt and confirm that they match with what you have set in the code.

    -Prashant.

  • 0 in reply to Prashant Nandakumar
    Prodigy 120 points

    Hi Prashant

    yes, the registers do seem to have the right value

    Hit any key to stop autoboot: 0
    TI8148_IPNC#
    TI8148_IPNC#
    TI8148_IPNC#md 4E000040
    4e000040: 00000000 00000000 00000000 807c0300 ..............|.
    4e000050: 00000000 00000000 00000000 00000000 ................
    4e000060: 00000000 00000000 00000000 00000000 ................
    4e000070: 00000000 00000000 00000000 00000000 ................
    4e000080: 00000000 00000000 00000000 00000000 ................
    4e000090: 00000000 00000000 00000000 00000000 ................
    4e0000a0: 00000000 00000000 00000000 00000000 ................
    4e0000b0: 00000000 00000000 00000000 00000000 ................
    4e0000c0: 00000000 00000000 00000000 00000000 ................
    4e0000d0: 00000000 00000000 00000000 00000000 ................
    4e0000e0: 00000000 00000000 00000000 00000000 ................
    4e0000f0: 00000000 00000000 00000000 00000000 ................
    4e000100: 00000000 00000000 00000000 00000000 ................
    4e000110: 00000000 00000000 00000000 00000000 ................
    4e000120: 00000000 00000000 00000000 00000000 ................
    4e000130: 00000000 00000000 00000000 00000000 ................
    TI8148_IPNC#