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DM814x Nand BCH8 implementation in GPMC

I am working on 8 bit BCH support using GPMC on Mistral DM814x EVM. Nand flash with software ECC is already working. I have implemented GPMC support without ELM. I have couple of queries regarding GPMCs BCH support.My flash has 2k page size, 64bytes spare and 512 bytes of sector with

1. TRM says that ECC is calculated on the fly and can be inserted in spare region on the fly too. But i was unable to find any info of how it is inserted on the fly? Consequently, I had to fetch these results from result register in a buffer and write on spare as a separate process. Any suggestion to insert it on the fly?

2. TRM says that  ECC result register contains result for complete page. I first implemented this in a scheme in which I write complete page followed by fetching of ECC  and insert them to spare region. However, my reads contains just results of last sector which was written. The rest of registers are empty. It looks results of all the sectors are placed in first set (i=0) registers. Am I missing something in configuration?

3. During read operation, ECC result register is supposed to contain syndrome only (if there are errors) and should contain zero if no errors are found. If errors are found, ELM module is used to detect the location and number of errors with the information of syndrome. Is this perception correct? My normal reads (test data) always contain non zero syndrome. Is there something problematic in my configuration?


I am using wrap mode 1. Is there some reference implementation of GPMC for BCH8?

  • Ejaz,

    Have you search for that info in the NAND chip datasheet? See also if the below documents will be in help:

    Regards,
    Pavel

  • Pavel,

    Thanks for your response. I have gone through these docs. I was however unable to find out U-boot/Linux sources. EZSdk source which I pulled yesterday just contains utilites like zlibe, qt4 etc. Mainline linux (kernel.org) contains davinci nand with 4bit bch (sort of useful for me). Mainline uboot just copied this driver from linux. Can you point me to a location where I could fetch ubott/linux with proper nand BCH support? I just came across gitorious.org/.../u-boot-am33x repo but it clearly mentions that error correction code is not functional.
  • u-boot code base:

    http://arago-project.org/git/projects/u-boot-omap3.git?p=projects/u-boot-omap3.git;a=shortlog;h=refs/heads/ti81xx-master

    linux kernel code base:

    http://arago-project.org/git/projects/?p=linux-omap3.git;a=shortlog;h=refs/heads/ti81xx-master

    Regards,
    Pavel

  • After following U-Boot, some of the questions have been answered but BCH support is still non-functional. Here is current status.

    >>1. TRM says that ECC is calculated on the fly and can be inserted in spare region on the fly too. But i was unable to find any info of how it is inserted on the fly? Consequently, I had to fetch these results from result register in a buffer and write on spare as a separate process. Any suggestion to insert it on the fly?
    This part is still unanswered. I am manually writing ECC.

    >>2. TRM says that ECC result register contains result for complete page. I first implemented this in a scheme in which I write complete page followed by fetching of ECC and insert them to spare region. However, my reads contains just results of last sector which was written. The rest of registers are empty. It looks results of all the sectors are placed in first set (i=0) registers. Am I missing something in configuration?
    This part is fixed as I was not specifying number of sectors to read/write.

    >>3. During read operation, ECC result register is supposed to contain syndrome only (if there are errors) and should contain zero if no errors are found. If errors are found, ELM module is used to detect the location and number of errors with the information of syndrome. Is this perception correct? My normal reads (test data) always contain non zero syndrome. Is there something problematic in my configuration?

    This part is still not functional. I suspect is it functioning properly in U-Boot too? Can somebody confirm this? Here is a suspicious comment from a U-Boot repo (not an official TI repo). gitorious.org/.../ti81xx_nand.c
    This is comment text.
    /* This currently sees all pages as being completely full of
    * uncorrectable errors. The suspicion is that this is due
    * to limitations in the elm support we have in U-Boot today
    */

    I have raised an email request for support too but got no response yet.
  • Hi Ejaz,

    DM814x ROM Code, u-boot and linux kernel support BCH8 ECC by default, see the below wiki page:

    processors.wiki.ti.com/.../TI81XX_PSP_NAND_Driver_User_Guide

    What exactly you need to change from the existing SW support in u-boot and/or linux kernel?

    Regards,
    Pavel
  • Pavel,

    I am implementing NAND BCH8 support in Nucleus OS with SAFE filesystem. It is not different from what U-Boot does. I am not using U-Boot nor I have built it for this board. I am using Nucleus ReadyStart and loading image via JTAG. Raw nand is working properly. When I enable BCH8 support and feed GPMC error polynomial results to ELM, it says that this data is full of uncorrectable errors. I want to figure out where does the problem exist? In ELM or GPMC? Documentation says that GPMC should result in zero syndrome if data being read has no errors. However, when I perform a read operation, it returns non-zero syndrome every time I read some data. I have written a program to read verify written data. Data being read and written is same but GPMC returns non-zero syndrome. Any idea if it is normal behavior or not? My configurations are same as U-Boot's one.
  • Ejaz,

    Make sure you are aligned with the programming model from the TRM:

    11.3.4 GPMC Configuration in NAND Mode

    You can check also your NAND-Flash for its ability to perform write access; read access and data storing ability. Refer to the Mistral web page:

    www.mistralsolutions.com/.../support-downloads
    Software -> Diagnostic software -> Base Board -> Rev D -> CCS_Code_BB -> src -> CCS_Test_code -> Base_Board -> NAND

    Regards,
    Pavel
  • Pavel,

    >Make sure you are aligned with the programming model from the TRM

    NAND (without BCH8) is working properly with Nucleus. I am just extending this to support hardware BCH8. I even have working setup for software BCH8.

  • Ejaz,

    You can also refer to the linux kernel source to see how BCH8 is implemented there:

    http://arago-project.org/git/projects/?p=linux-omap3.git;a=shortlog;h=refs/heads/ti81xx-master

    BR
    Pavel

  • Ejaz,

    Ejaz Ahmed28 said:
    GPMC should result in zero syndrome if data being read has no errors. However, when I perform a read operation, it returns non-zero syndrome every time I read some data.

    Could you provide more details regarding your read operation?

    Best regards,
    Pavel

  • Here is pseudo code/step for read operation:
    1. Enable ECC BCH8 support in GPMC
    2. Read 512 bytes chunk + spare (stored ECC)
    3. Read GPMC result registers for syndrome
    4. If syndrome is non-zero, load syndrome in ELM
    5. If ELM returns correctable errors, correct the errors by flipping bits.
    6. If errors are un-correctable, mark this block as bad.
    7. Repeat step untill complete page is read.
  • Ejaz,

    Can you provide me your GPMC register map, I can compare with mine?

    Ejaz Ahmed28 said:
    1. Enable ECC BCH8 support in GPMC

    This should be register GPMC_ECC_CONFIG

    Ejaz Ahmed28 said:
    Read 512 bytes chunk + spare (stored ECC)

    I read 512bytes + 64bytes spare, total 576bytes (0x240), from NAND chip to DDR location, read operation is reported as successful

    Ejaz Ahmed28 said:
    3. Read GPMC result registers for syndrome

    Do you mean register GPMC_BCH_RESULT0_0, ... , GPMC_BCH_RESULT6_0?

    Before NAND read operation I have some values in GPMC_BCH_RESULT0/1/2/3_0 and 0 in GPMC_BCH_RESULT4/5/6_0. After NAND read operation I have 0 in all the GPMC_BCH_RESULTx_0 registers.

    Regards,
    Pavel