Hi.
In page 247 in tms320dm8148 in Timing Requirements section , Note A, it's written:
EMAC[x]_RGRXC must be externally delayed relative to the data and control pins. The internal delay can be enabled or disabled via the EMAC RGMIIx_ID_MODE register.
From which I can understand that this bit controls an internal delay of the RX clock.
On the other hand, on page 1458 in dm8148 Techinal Reference manual, it says:
The RGMII0/1_ID_MODE bit value in the GMII_SEL register determines whether or not the transmit delay is included in the CPRGMII or not. When RGMII0/1_ID_MODE bit is cleared to 0, the transmit delay is included. The RGMII0/1_ID_MODE input is a configuration input only and is not intended to be changed during packet operations.
My question is:
Which lines exactly this bit affects? rx? tx? both?
Much Appreciated
Boris-Ben Shapiro
RT Embedded Enginner
Elspec LTD
