Hi all.
I have a question about DDR configuration in DM8148 ARM+DSP custom board. The DDR chip is 2Gb MT41J128M16 – 16 Meg x 16 x 8 banks.
I cannot quite understand what is the correct DMM_LISA..0-3 registers configuration. Why are there 4 registers and the first 2 are not used?
How should i configure this registers according to the layout i have?
my current configuration is:
PG2_1_DMM_LISA_MAP__0 0x0 PG2_1_DMM_LISA_MAP__1 0x0 PG2_1_DMM_LISA_MAP__2 0x80540300 PG2_1_DMM_LISA_MAP__3 0xC0540300 DDR3_EMIF_REF_CTRL 0x00000C30 DDR3_EMIF_SDRAM_CONFIG 0x61C01032 DDR3_EMIF_SDRAM_ZQCR 0x50074BE1
My bootargs are:
console=ttyO3,115200n8 no_console_suspend rootdelay=2 rootwait noinitrd earlyprintk print_fatal_signals=1 nolock irqpoll boot_delay=5 rw root=/dev/mmcblk0p6 vram=50M ti814xfb.vram=0:24M,1:16M,2:6M notifyk.vpssm3_sva=0xbf900000 mem=248M ddr_mem=1024M debug=1 5
I also use firmware_loader with the dm8148_hdvpss.xem3 default memory map file to load VPSS core.
I get these weird alignment exceptions and memory faults sometimes during firmaware_loader VPSS firmware loading and sometimes during kernel loading and rarely when loading DSP core. Which leads me to think it's some sort of memory problem/misconfiguration.
I couldn't find anywhere a good manual that explains how to get the correct configuration for the DDR registers for dm8148.
Can someone tell me what's the correct LISA_MAP__* and EMIF_SDRAM_* registers for my chip, or even better, where i can learn how to retrieve that information myself :D
Much Appreciated.
Boris-Ben Shapiro
