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GPMC Burst Mode

kashetty pranay kumar
Intellectual 775 points

Hi,

We are using DM8148 in our board. DM8148 is interface with FPGA using GPMC. we have connected FPGA on CS1. We are able to read and write using single Access. Now our goal is to do burst access between 8148 and FPGA using GPMC. I am new to GPMC and Burst modes.

1.How does it work basically ?? I have configured all the config registers in Burst mode. But who to give required amount of data for burst to GPMC.Is there any Hardware buffer of FIFO which takes burst data and writes using GPMC ?? 

2.Is there any sample Linux Code to perform Burst access using GPMC ??

3. Any software driver cannot supply data to GPMC in single clock level. So there has to be hardware support, in which all the data is written and a burst access will be issued. Is my understanding is correct ? If correct what hardware support is GPMC is providing ??

4. After going through the TRM I found pre fetch engine and FIFO. But it is mentioned that, it is used only while accesing stream devices like NAND. We are accessing FPGA like a NOR device. How to achieve burst mode ??

Regards,

PK

  • 0
    TI__Guru**** 170625 points

    Hi PK,

    kashetty pranay kumar said:
    1.How does it work basically ?? I have configured all the config registers in Burst mode. But who to give required amount of data for burst to GPMC.Is there any Hardware buffer of FIFO which takes burst data and writes using GPMC ?? 

    The host (i.e. Cortex-A8 ARM core, DSP core, DMA) should give the required amount of data for burst. There is no hardware buffer/FIFO in NOR mode.

    kashetty pranay kumar said:
    2.Is there any sample Linux Code to perform Burst access using GPMC ??

    I can not find such.

    kashetty pranay kumar said:
    3. Any software driver cannot supply data to GPMC in single clock level. So there has to be hardware support, in which all the data is written and a burst access will be issued. Is my understanding is correct ? If correct what hardware support is GPMC is providing ??

    Burst read/write is synchronous to the GPMC clock (GPMC_CLK). You have one data transfer for a single clock. Next data transfer start on the next clock.

    kashetty pranay kumar said:
    After going through the TRM I found pre fetch engine and FIFO. But it is mentioned that, it is used only while accesing stream devices like NAND. We are accessing FPGA like a NOR device. How to achieve burst mode ??

    For how to achieve burst mode for NOR like device, see 11.3.3 GPMC Configuration in NOR Mode:

    Set a single or multiple access for read operations - GPMC_CONFIG1_i[30] READMULTIPLE  = 1

    Set a single or multiple access for write operations - GPMC_CONFIG1_i[28] WRITEMULTIPLE = 1

    11.2.4.10.4 Page and Burst Support
    11.2.4.10.5 System Burst Versus External Device Burst Support

    11.3.5 Set Memory Access


    11.4.1.3 GPMC Configuration for Synchronous Burst Read Access

     
    See also if the below e2e threads will be in help:


    BR
    Pavel