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Jacinto 5 Eco - chip select going high between words when using FIFO, how do I keep it low?

Staffan Johansson
Intellectual 565 points
Other Parts Discussed in Thread: SYSCONFIG

I have a Jacinto 5 Eco board.

When I use the FIFO to transmit 2 words of size 8 I can see the chip select going high (active low) for a very short time between the words.

Shouldn't the SPI unit keep the chip select low until all words have been transmitted?

Found this:

"Manual SPI_SCS[n] assertion to keep SPI_SCS[n] active between SPI words. (single channel master
mode only)"

Does that mean that you cannot have multichannel master and keep the chip select alive between words?

But you could change the SINGLE bit between talking to different devices right? No need to RESET the module if you change between MULTI and SINGLE?

I am also unsure what the correct way is to check if the entire FIFO has been transmitted.

#define MCSPI_CHnSTAT_EOT_MASK (1uL << MCSPI_EOT_OFFSET)
//#define MCSPI_CHnSTAT_FIFO_TX_FIN_MASK (MCSPI_CHnSTAT_EOT_MASK | (1uL << MCSPI_TXFFE_OFFSET))
#define MCSPI_EOW_OFFSET 17uL
#define MCSPI_IRQSTATUS_EOW_MASK (1uL << MCSPI_EOW_OFFSET)

With MCSPI_CHnSTAT_FIFO_TX_FIN_MASK the TXFFE bit becomes 0 after transmitting, but after I sent, shouldnt this be 1 as in "tx buffer empty"?

  • 0
    TI__Guru**** 170625 points

    Staffan,

    Staffan Johansson said:
    Does that mean that you cannot have multichannel master and keep the chip select alive between words?

    Yes. Force mode is available only in master single channel mode. See the below links for more info:

    BR
    Pavel

  • 0
    TI__Guru**** 170625 points

    Staffan Johansson said:
    But you could change the SINGLE bit between talking to different devices right? No need to RESET the module if you change between MULTI and SINGLE?

    I made a search in TRM and I can not find such requirement, to reset the McSPI module when switch from SINGLE to MULTI and from MULTI to SINGLE (change the value in bit MCSPI_MODULCTRL[0] SINGLE). The only requirement I found is to reset the McSPI module when switch between Master and Slave mode:

    21.2.12 Programming Aid
    21.2.12.1 Module Initialization
    To avoid hazardous behavior, it is advised to reset the module before changing from MASTER mode to SLAVE mode or from SLAVE mode to MASTER mode.

    But I think it will be better to make SW reset (MCSPI_SYSCONFIG[1] SOFTRESET = 1) and then wait for a while till MCSPI_SYSSTATUS[0] RESETDONE == 1, when switching between single channel and multi channel mode.

    BR
    Pavel

  • 0
    TI__Guru**** 170625 points

    Staffan Johansson said:
    I am also unsure what the correct way is to check if the entire FIFO has been transmitted.

    Staffan Johansson said:
    With MCSPI_CHnSTAT_FIFO_TX_FIN_MASK the TXFFE bit becomes 0 after transmitting, but after I sent, shouldnt this be 1 as in "tx buffer empty"?

    There are TX_empty and TX_underflow interrupt events to notify the data is transferred. TX_underflow is harmless warning that FIFO is empty. See also section 21.2.3.10.4 End of Transfer Management


    BR
    Pavel