Wrong speed in recorded sound

ranchu

Guru 20755 points

Other Parts Discussed in Thread: DM385

Hello,

On recording mcasp2 input (using arecord), and then playback the recorded file in PC, we've noticed that it speed is faster.

We use external oscillator 24.576Mhz which is conneced to DM8148.

With the help of the below links, I understand that u-boot configures this MCLK clock in clocks_ti814xx.c

#define AUDIO_N 19
#define AUDIO_M 500
#define AUDIO_M2 2
#define AUDIO_CLKCTRL 0x801

I also see that the formula is:

M/(N+1) * CLKINP * 1/M2

I therefore tried to change it as following:

#define AUDIO_N 0
#define AUDIO_M 1
#define AUDIO_M2 1

(in order to ger '1' factor), but then u-boot (minimal) hangs.

I also tried to understand how it works with evm, but it still does not make sense to me:

1. evm hw uses 22.579MHz osscilator, and the code shows:

#define AUDIO_N 19
#define AUDIO_M 500
#define AUDIO_M2 2
#define AUDIO_CLKCTRL 0x801

trying this with the formula I get:

freq = M/(N+1) * CLKINP * 1/M2 = 500/20*22.579M*(1/2) = 282.2375M ,

while I expected to get 24.576M , becuase this is what I see in evm code:

static int ti81xx_evm_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{....

/* default */
sysclk = 24576000;

}

Is there anything wrong in the above assumptions ?

Regards,

Ran

over 8 years ago

0 ranchu over 8 years ago

Guru 20755 points

I have also tried other options for
#define AUDIO_N
#define AUDIO_M
#define AUDIO_M2

But It seems that the rate is not changed, otr u-boot hangs.
It seems that I'm stuck at this point.

Is there any idea ?

0 Pavel Botev over 8 years ago in reply to ranchu

TI__Guru**** 170625 points

Ran,

In DM814x EVM, the MCASP2_ACLKHX pin is not used, AIC3106 MCLK is coming from U43 (24.5760MHz clock generator), going through U36 (buffer). This U43 is not DEVOSC, nor AUXOSC, neither AUDIO PLL.

In DM811x/J5Eco EVM, the McASP2_ACLKHX pin is used, it goes into the AIC3106 MCLK input.

What is the clock source for AIC3x MCLK input in your custom board?

BR
Pavel

0 ranchu over 8 years ago in reply to Pavel Botev

Guru 20755 points

Hi Pavel,

This is the schema for the audio pll for mcasp 2&3, with the oscillator of 24.576Mhz.

I am not a HW engineer (I will later check it with the HW staff) , but as far as I understand from this schematic, it seems that we use MCASP2_ACLKHX/MCASP3_ACLKHX.

Does it explain the wrong speed ?

Thank you very much for your time.

Ran

0 Pavel Botev over 8 years ago in reply to ranchu

TI__Guru**** 170625 points

Ran Shalit said:
This is the schema for the audio pll for mcasp 2&3, with the oscillator of 24.576Mhz.

I do not see how Audio PLL is involved here. Can you clarify on that point?

So finally, what is the source for the codec MCLK: MCA2_AHCLKX or oscillator U39?

BR
Pavel

0 Pavel Botev over 8 years ago in reply to Pavel Botev

TI__Guru**** 170625 points

Ran,

If NA means that these resistors (R553, R552, R551 and R610) are not mounted, then the clock source for the codec MCLK will come from AHCLKX, not from U39 oscillator. Thus you will need to set up the right frequency for this pin. You can refer to the J5Eco/DM811x/TI811x linux kernel code base, where the same approach is applied.

arago-project.org/.../

BR
Pavel

0 ranchu over 8 years ago in reply to Pavel Botev

Guru 20755 points

Hi Pavel,

The initial HW design aim was to give two alternatives ,so that in case we have problem in one of them, we can try the other....

But Now I start to suspect that maybe these 2 alternatives interfere with each other ? Our SW is based on dm8148 evm

Best Regards,
Ran

0 Pavel Botev over 8 years ago in reply to ranchu

TI__Guru**** 170625 points

Ran,

You can not have these two alternatives at the same time. If you have these resistors (R553, R552, R551 and R610) populated on the HW, then the U39/U40 alternative can not be controlled, it will be aways active (U40 OE is aways high), thus when you set the other alternative (AHCLKX), there will be conflict between these two.

So make sure:

1. If you need U39/U40 alternative, remove resistors R552, R553, R534, R535. And populate resistors R551 and R610

2. If you need AHCLKX alternative, remove resistors R553, R552, R551, R610. And populate resistors R534 and R535

BR
Pavel

0 ranchu over 8 years ago in reply to Pavel Botev

Guru 20755 points

Hi Pavel,

Thank you very much for the suggestion.

I just made another test in which I've disabled AHCLKX pins in u-boot pinmux , but I still got the same behaviour.
If disabling these pins still gives wrong results, I guess it can also be some issue of bad 24.576Mhz clock signal after u39/u40 ?

Regards,

Ran

0 ranchu over 8 years ago in reply to ranchu

Guru 20755 points

Pavel,

We will probably need to fix HW as you suggested and try again,

Thank you very much.
Ran

0 Pavel Botev over 8 years ago in reply to ranchu

TI__Guru**** 170625 points

Ran Shalit said:
If disabling these pins still gives wrong results, I guess it can also be some issue of bad 24.576Mhz clock signal after u39/u40 ?

Remove resistors R552, R553, R534, R535, populate resistors R551 and R610, and measure with scope the clock signal of codec MCLK to verify it exist and it is 24.576MHz.

BR
Pavel

0 ranchu over 8 years ago in reply to Pavel Botev

Guru 20755 points

Hi Pavel,

The NA means that it is not connected (not assembled). It mans that we are using AHCLKX alternative . So as I understand there is some reference in DM811X for using it ?
Do you have a more specific pointer as to where it is configured in code ?

Another question - Is there any reason why EVM uses external oscillator and not AHCLKX ? I ask becuase if there is some issue here (performace, etc.) which makes the external oscillatorm a better choice, we might want to change HW for that alternative.

Regards,
Ran

0 ranchu over 8 years ago in reply to ranchu

Guru 20755 points

Hi Pavel,

I made some progress here, with clues from other thread on the same subject.
But I had to make some workaround to make it works I wondered if you know why the original method did not work:

1. My original goal: I tried to make the following changes: A. AUXOSC instead of DEVOSC B. clk20 instead of clk22 , similar to the suggestion you've provided in e2e.ti.com/.../816917
2. I've added in board file

static void __init ti8148_evm_init(void)
{
....
/* initialize usb */
usb_musb_init(&musb_board_data);
ti8148_spi_init();

audio_init();/*ranranx */ <<-------------

...
}

static int audio_init()
{
struct clk *clkp_osc1, *clkp_audio_pll, *clkp_sysclk20, *clkp_mcasp2;
int reg, ret;
unsigned long clk_rate;

clkp_osc1 = clk_get(NULL,"osc1_clkin_ck");
clk_rate = clk_get_rate(clkp_osc1);
printk(KERN_INFO "dvm_vmpp_audio_init: clock rate: %d\n", clk_rate) ;
clk_set_rate(clkp_osc1, 24576000) ;

clkp_audio_pll = clk_get(NULL,"audio_dpll_clkin_ck");
if(!clkp_audio_pll)
printk("audio_dpll_clkin_ck\n");
else
printk("audio_dpll_clkin_ck success.\n");

ret = clk_set_parent(clkp_audio_pll, clkp_osc1);
printk(KERN_INFO "dvm_vmpp_audio_init: clk_set_parent(osc1) %d\n", ret) ;

clkp_mcasp2 = clk_get(NULL,"davinci-mcasp.2");
if(!clkp_mcasp2)
printk("davinci-mcasp.2\n");
else
printk("davinci-mcasp.2 success.\n");

clkp_sysclk20 = clk_get(NULL,"sysclk20_ck");
if(!clkp_sysclk20)
printk("sysclk20_ck\n");
else
printk("sysclk20_ck success.\n");

ret = clk_set_parent(clkp_mcasp2, clkp_sysclk20);
printk(KERN_INFO "dvm_vmpp_audio_init: clk_set_parent(clkp_sysclk20) %d\n", ret) ;

clk_put(clkp_mcasp2) ;
clk_put(clkp_osc1) ;
clk_put(clkp_audio_pll) ;
}

But it did not work.......
the clock of osc1 in shell debugfs still showed 22579000 although the module did not show any error !

I had to add this patches:
1, in u-boot (according to patch you've provided in the above link
/*
* McASP2
* select mcasp2 clk from sys_clk_22 (OSC 0)
* so that audio clk (sys_clk_20) can be used for RMII
* ToDo :
* This can be removed once kernel exports set_parent()
*/
//__raw_writel(0x2, CM_AUDIOCLK_MCASP2_CLKSEL);
//while (__raw_readl(CM_AUDIOCLK_MCASP2_CLKSEL) != 0x2);

2. in kernel clock814x_data.c:
/* Additional clock source */
static struct clk osc1_clkin_ck = {
.name = "osc1_clkin_ck",
.ops = &clkops_null,
.rate = 24576000,/*ranranx 22579000,*/ /* Typically at 27M or 22.579MHz */
.flags = RATE_IN_TI814X | RATE_IN_DM385 | RATE_IN_TI811X,
};

With the workaround it seems to work.

Thanks,
Ran

0 Pavel Botev over 8 years ago in reply to ranchu

TI__Guru**** 170625 points

Ran Shalit said:
The NA means that it is not connected (not assembled). It mans that we are using AHCLKX alternative . So as I understand there is some reference in DM811X for using it ?
Do you have a more specific pointer as to where it is configured in code ?

Refer to the below linux kernel code base:

See files:

linux-omap3/sound/soc/davinci/davinci-mcasp.c

linux-omap3/arch/arm/mach-omap2/devices.c

linux-omap3/arch/arm/mach-omap2/board-ti811xevm.c

This is valid for TI811x device.

Ran Shalit said:
Another question - Is there any reason why EVM uses external oscillator and not AHCLKX ? I ask becuase if there is some issue here (performace, etc.) which makes the external oscillatorm a better choice, we might want to change HW for that alternative.

The 8148 EVM is manufactured by Mistral, so you can contact Mistral support team.

BR
Pavel

0 ranchu over 8 years ago in reply to Pavel Botev

Guru 20755 points

Hi Pavel,

Thanks,
I've posted above another message with a solution (workaround) which solved the speed issue.

Regards,
Ran

0 ranchu over 8 years ago in reply to ranchu

Guru 20755 points

Hi Pavel,

One more thing on this issue:
Is there any reason why the following did not change the rate of clkp_osc1, although there is no error ?

clkp_osc1 = clk_get(NULL,"osc1_clkin_ck");
clk_rate = clk_get_rate(clkp_osc1);
clk_set_rate(clkp_osc1, 24576000) ;

(I had to change the default rate of osc1_clkin_ck in clock814x_data.c to make it work)

Regards,
Ran

0 Pavel Botev over 8 years ago in reply to ranchu

TI__Guru**** 170625 points

processors.wiki.ti.com/.../TI81XX_PSP_PM_CLOCK_FRAMEWORK_User_Guide

Q: Why am i not able to change rate of a clock using clk_set_rate()?

A:Check if the clock is sourced from a PLL or a fixed clock. Only Clocks, whose root source is from a pll can be changed to run at different rates.

0 ranchu over 8 years ago in reply to Pavel Botev

Guru 20755 points

Thank you very much, Pavel

Processors

Processors forum

Wrong speed in recorded sound