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Only find axr0-axr9,no axr10-axr15

Hi Pavel,

In TRM,it says there are 16 axrs.But in kernel,I only find arx0-axr9, no axr10-axr15.

In Mux814x.c file,I also can't find axr10-axr15.

Would you please give me some more details?

And I also find if I set aic3x_iis_serializer_direction[0]=TX_MODE as below,

static u8 aic3x_iis_serializer_direction[]= {
 TX_MODE,  INACTIVE_MODE,   INACTIVE_MODE, INACTIVE_MODE, 
 INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE,
 INACTIVE_MODE, INACTIVE_MODE,   INACTIVE_MODE, INACTIVE_MODE,
 INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE,
};

the value of SRCTL registers as below.I really don't why.

SRCTL0   =0x11
SRCTL1   =0x0
SRCTL2   =0x0
SRCTL3   =0x0
SRCTL4   =0x0
SRCTL5   =0x0
SRCTL6   =0x0
SRCTL7   =0x0
SRCTL8   =0x0
SRCTL9   =0x0
SRCTL10  =0x11
SRCTL11  =0x11
SRCTL12  =0x11
SRCTL13  =0x11
SRCTL14  =0x11
SRCTL15  =0x11

BR

Bob

  • bob lee said:
    In TRM,it says there are 16 axrs.

    Yes, but it also says to see the DM814x data manual (datasheet) for more details regarding the McASP data pins. If you follow this instruction and see datasheet, you will find that TRM is very generic, and the datasheet is the right source for the McASP pins details, where McASP0/1 have 10 data pins (axr9 to axr0) and McASP2/3/4/5 have 4 data pins (axr3 to axr0).

    BR
    Pavel

  • Hi Pavel,

    Thanks for your reply.But one more question.

    I set  array aic3x_iis_serializer_direction as below,so I think only the value of SRCTL0 is 0x11.But the value of SRCTL10~SRCTL15 is also 0x11.

    I want to know whether the SRCTL10~SRCTL15(0x11) are  effecting the data transmission.

    Array:

    static u8 aic3x_iis_serializer_direction[]= {
     TX_MODE,  INACTIVE_MODE,   INACTIVE_MODE, INACTIVE_MODE, 
     INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE,
     INACTIVE_MODE, INACTIVE_MODE,   INACTIVE_MODE, INACTIVE_MODE,
     INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE,
    };

    Register SRCTL:

    SRCTL0   =0x11
    SRCTL1   =0x0
    SRCTL2   =0x0
    SRCTL3   =0x0
    SRCTL4   =0x0
    SRCTL5   =0x0
    SRCTL6   =0x0
    SRCTL7   =0x0
    SRCTL8   =0x0
    SRCTL9   =0x0
    SRCTL10  =0x11
    SRCTL11  =0x11
    SRCTL12  =0x11
    SRCTL13  =0x11
    SRCTL14  =0x11
    SRCTL15  =0x11

     

  • Bob,

    bob lee said:
    I want to know whether the SRCTL10~SRCTL15(0x11) are  effecting the data transmission.

    I do not think these registers are effecting the data transmission. Just keep in mind the TRM note (page 2126):

    NOTE:
    Device-specific registers
    Accessing SRCTLn not implemented on a specific device may cause improper device operation.

    BR
    Pavel

  • Bob,

    This seems to be fixed in linux kernel v3.10, so you might need to backport mcasp from v3.10 to v2.6.37

    lxr.free-electrons.com/.../davinci-mcasp.c

    See functions davinci_mcasp_hw_params() and davinci_hw_common_param()

    BR
    Pavel
  • Hi Pavel,

    Would you send us linux kernel v3.10 full code ? I want to try the v3.10 code.

    Thank you .

    BR

    Bob

  • Hi Pavel,

    I get it.Thank you very much.

    Bob