I am trying to bring up broadcom BCM89811 phy chip in our custom board based on ti811x. ping command is not working even though phy shows link up. Board connected to PC using cross cable. Both pc(192.168.1.52) and board(192.168.1.49) assigned with static ip. uboot console message shown below. and code is also copied for your reference. Can someone help me to fix this communication issue.
board: custom board based on J5 ti811x
Ethernet Phy: BCM89811 from broadcom. configured in RMII mode and interfaced with EMAC0. Phy address: 01
ezsdk uboot version :u-boot-2010.06-psp04.07.00.02
ezsdk kernel version :linux-2.6.37-psp04.07.00.02
PC network configuration:
--------------------------
eth0 Link encap:Ethernet HWaddr 54:53:ed:25:41:91
inet addr:192.168.1.52 Bcast:192.168.1.255 Mask:255.255.255.0
inet6 addr: fe80::5653:edff:fe25:4191/64 Scope:Link
UP BROADCAST RUNNING MULTICAST MTU:1500 Metric:1
RX packets:0 errors:0 dropped:0 overruns:0 frame:0
TX packets:31076 errors:0 dropped:0 overruns:0 carrier:0
collisions:0 txqueuelen:1000
RX bytes:0 (0.0 B) TX bytes:2369137 (2.3 MB)
board uboot console:
--------------------
U-Boot 2010.06-00013-g5158f2a-dirty (Oct 04 2015 - 17:21:48)
TI811X-GP rev 1.1
ARM clk: 600MHz
DDR clk: 333MHz
I2C: ready
DRAM: 1 GiB
NAND: HW ECC BCH8 Selected
No NAND device found!!!
0 MiB
MMC: OMAP SD/MMC: 0
*** Warning - bad CRC or MMC, using default environment
@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
@@ @@
@@ @@
@@ @@
@@ @@
@@ @@
@@ 88888888888 8888888 .d8888b. d888 d888 @@
@@ 888 888 d88P Y88b d8888 d8888 @@
@@ 888 888 Y88b. d88P 888 888 @@
@@ 888 888 Y88888 888 888 888 888 @@
@@ 888 888 .d8P88Y8b. 888 888 Y8 8P @@
@@ 888 888 888 888 888 888 88 @@
@@ 888 888 Y88b d88P 888 888 .d8 8b. @@
@@ 888 8888888 Y8888P 8888888 8888888 888 888 @@
@@ @@
@@ @@
@@ @@
@@ @@
@@ @@
@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
Net: pad muxing for RSB
Enable GPIO_0 clock
Writing CM_ALWON_GPIO_0_CLKCTRL:0x4818155c with 0x102
Validating CM_ALWON_GPIO_0_CLKCTRL reg write
Enable GPIO_1 clock
Writing CM_ALWON_GPIO_1_CLKCTRL:0x48181560 with 0x102
Validating CM_ALWON_GPIO_1_CLKCTRL reg write
Setting pin as: output
Reading register: 481ae134
writing register: 481ae134 with ff7fffff
Setting pin 23 with 1
Configuring PAD58_CNTRL for E0_RESET_N
Setting pin as: output
Reading register: 48032134
writing register: 48032134 with efffffff
Setting pin 28 with 1
In loop
Out loop
Ethernet clocking: 0x0
<ethaddr> not set. Reading from E-fuse
Detected MACID:ec:11:27:d7:fd:e0
cpsw
Hit any key to stop autoboot: 0
TI811X_EVM#setenv ipaddr 192.168.1.49
TI811X_EVM#printenv
bootcmd=if mmc rescan 0; then if run loadbootscript; then run bootscript; else echi
bootdelay=3
baudrate=115200
verify=yes
bootfile=uImage
ramdisk_file=ramdisk.gz
loadaddr=0x81000000
script_addr=0x80900000
loadbootscript=fatload mmc 0 ${script_addr} boot.scr
bootscript= echo Running bootscript from MMC/SD to set the ENV...; source ${script}
stdin=serial
stdout=serial
stderr=serial
ethaddr=65:63:3a:31:31:3a
ethact=cpsw
ipaddr=192.168.1.49
Environment size: 739/8188 bytes
TI811X_EVM#ping 192.168.1.52
Initializing BCM89811 Eth Phy: name:cpsw addr:1
/*******************begin EMI optimization portion********************************/
ETH_TRCV_CTRL_REG: 0x200
Setting Phy Address 0x1 into MII Lite mode
Setting PORT 0x1 to 100Mbps 1Pair Slave
ETH_TRCV_STATUS_REG: 0x63cd
link status active: 1 Pair 100 Mbps
link up on port 0, speed 100, full duplex
Using cpsw device
ping failed; host 192.168.1.52 is not alive
TI811X_EVM#
-----------------------------------------------------------------------------------------
int board_init(void)
{
/* setup RMII_REFCLK .its an input from external src */
__raw_writel(0x30005, RMII_REFCLK_SRC);
/*program GMII_SEL register for RMII mode */
__raw_writel(0x305, GMII_SEL);
}
static struct cpsw_slave_data cpsw_slaves[] = {
{
.slave_reg_ofs = 0x208,
.sliver_reg_ofs = 0xd80,
.phy_id = 1,
},
{
.slave_reg_ofs = 0x308,
.sliver_reg_ofs = 0xdc0,
.phy_id = 1,
},
};
static struct cpsw_platform_data cpsw_data = {
.mdio_base = TI811X_CPSW_MDIO_BASE,
.cpsw_base = TI814X_CPSW_BASE,
.mdio_div = 0xff,
.channels = 8,
.cpdma_reg_ofs = 0x800,
.cpdma_sram_ofs = 0xa00,
.slaves = 1,
.slave_data = cpsw_slaves,
.ale_reg_ofs = 0xd00,
.ale_entries = 1024,
.host_port_reg_ofs = 0x108,
.hw_stats_reg_ofs = 0x900,
.mac_control = (BIT(15) | BIT(0)),/* BIT(15)RMII/RGMII Gasket Control */ /*BIT(0)Full Duplex*/ /*(1 << 5),*/ /* MIIEN */
.control = cpsw_control,
.phy_init = phy_init,
.host_port_num = 0,
.bd_ram_ofs = 0x2000,
};
static void cpsw_pad_config()
{
volatile u32 val = 0;
printf("pad muxing for RSB\n");
enable_gpio_clk();
/*configure pin mux for rmii_refclk,mdio_clk,mdio_d */
//E_GTXCLK. 50 MHz RMII Ref clock is an input to j5-prime and BCM89811. Its an external clock from oscilator
val = PAD232_CNTRL;
PAD232_CNTRL = (volatile unsigned int) (BIT(18) | BIT(0));
//E_MDC
val = PAD233_CNTRL;
PAD233_CNTRL = (volatile unsigned int) (BIT(19) | BIT(17) | BIT(0));
//E_MDIO
val = PAD234_CNTRL;
PAD234_CNTRL = (volatile unsigned int) (BIT(19) | BIT(18) | BIT(17) |
BIT(0));
/*setup rmii0/rmii1 pins here*/
/* In this case we enable rgmii_en bit in GMII_SEL register and
* still program the pins in gmii mode: gmii0 pins in mode 2 */
val = PAD236_CNTRL; /*E0_RXD0*/
PAD236_CNTRL = (volatile unsigned int) (BIT(18) | BIT(2));
val = PAD237_CNTRL; /*E0_RXD1*/ //sample this pin to assign RMII mode RXD1 should be 1 during reset RXD[2]=0
PAD237_CNTRL = (volatile unsigned int) (BIT(18) | BIT(17) | BIT(2));
val = PAD238_CNTRL; /*RMRXER*/ //PullDown
PAD238_CNTRL = (volatile unsigned int) (BIT(18) | BIT(2));
val = PAD239_CNTRL; /*E0_RXDV*/ //sample this pin to assign phy address 0x00000 or 0x00001 during reset
PAD239_CNTRL = (volatile unsigned int) (BIT(18) | BIT(2));
val = PAD240_CNTRL; /*E0_TXD0*/
PAD240_CNTRL = (volatile unsigned int) (BIT(18) | BIT(2));
val = PAD241_CNTRL; /*E0_TXD1*/
PAD241_CNTRL = (volatile unsigned int) (BIT(18) | BIT(2));
val = PAD242_CNTRL; /*E0_TXEN*/
PAD242_CNTRL = (volatile unsigned int) (BIT(18) | BIT(2));
val = PAD235_CNTRL; /*E0_PHY_EN--OUT*/ //set to 1
PAD235_CNTRL = (volatile unsigned int) (BIT(18) | /*BIT(17) |*/ BIT(7));
set_pin_direction(GPIO3_BASE, PHY_EN_GPIO3_PIN, OUTPUT);
set_pin_value(GPIO3_BASE, PHY_EN_GPIO3_PIN, 1);
val = PAD230_CNTRL; /*E0_PHY_INT_N*/
PAD230_CNTRL = (volatile unsigned int) (BIT(18) | BIT(7));
val = PAD224_CNTRL; /*E0_PHY_WAKE--OUT*/
PAD224_CNTRL = (volatile unsigned int) (BIT(18) | BIT(7));
printf("Configuring PAD58_CNTRL for E0_RESET_N \n ");
val = PAD58_CNTRL; /*GP0[28]E0_RESET_N--OUT*/ //set to 1
PAD58_CNTRL = (volatile unsigned int) (BIT(18) | /*BIT(17) |*/ BIT(7));
set_pin_direction(GPIO0_BASE, PHY_RESET_GPIO0_PIN, OUTPUT);
set_pin_value(GPIO0_BASE, PHY_RESET_GPIO0_PIN, 1);
val = PAD140_CNTRL; /*ETH0_INH_N*/
PAD140_CNTRL = (volatile unsigned int) (BIT(18) | BIT(7));
}