DM8107 Pixel Clock issue with n/1.001 Hz Display formats

Shawn Rainey1

Other Parts Discussed in Thread: DM8107

Hi,

I'm running into an issue outputting SMPTE x/1.001 FPS video from the DM8107. The DM8107 is being used on a custom board ultimately as a source for SDI output. Although we can set the mode through the dvrrdk framework, the VPSS kernel module as released will set the pixel clock out of spec for SMTPE standards, and off from the frequency specified in ti_vdis_timings.h (74.176MHz)

With the driver as is from TI, we get the following when setting the display

obtained from /opt/dvr_rdk/ti810x/bin/pll_print.out:

VIDEO_1 Freq : 74.2 MHz ( M x 20 ) / ( (N+1) x M2 )
        VIDEO_1_M   : 594
        VIDEO_1_N   : 19
        VIDEO_1_M2 : 8

HDMI Freq : 74.2 MHz ( M x 20 ) / ( (N+1) x M2 )
        HDMI_M   : 742
        HDMI_N   : 19
        HDMI_M2 : 10

For either of the above PLLs, the calculated value is exactly 74.2MHz, which is too far out of spec for some of our monitors to consistently lock to 1080p29. In one case, the monitor will reset and switch between 29.9 and 30 every few seconds. We have measured this in the lab and confirmed the pixel clock to be exactly 74.2MHz with these settings.

The video at this setting does however otherwise look fine.

I was able to modify the vpss module to set the PLLs as follows for 1080p29 and resolutions with the same clock rate:

VIDEO_1 Freq : 74.2 MHz ( M x 20 ) / ( (N+1) x M2 )
        VIDEO_1_M   : 1350
        VIDEO_1_N   : 25
        VIDEO_1_M2 : 14

HDMI Freq : 74.2 MHz ( M x 20 ) / ( (N+1) x M2 )
        HDMI_M   : 1350
        HDMI_N   : 25
        HDMI_M2 : 14

The more precise calculated frequency with these values is 74.175824, which is the correct clock rate for the SMPTE spec. As with the previous settings, we've measured this in our lab and confirmed that the outgoing pixel clock does in fact match the calculated frequency. Also, all of our monitors will lock to 29.9 with this setting, but we must be missing something in the pipeline, as the video frame is not properly synchronized - the result looks like scrolling as you might see in improperly synchronized analog video. This issue also exists for 1080p59.9 (148.5/1.001 MHz) and 720p59.

Aside from the pixel clock frequency, all other settings remain the same. I'm guessing it's something internal to the HDVPSS subsystem or maybe more specifically within the HDVENC setup, but after some time digging I haven't been able to find a solution. We've exhausted any ideas on our side as to how to get this working, and are now hoping for some support from the TI side.

Any help would be greatly appreciated.

over 8 years ago

0 Pavel Botev over 8 years ago

TI__Guru**** 170625 points

Shawn Rainey1 said:
VIDEO_1 Freq : 74.2 MHz ( M x 20 ) / ( (N+1) x M2 )
        VIDEO_1_M   : 594
        VIDEO_1_N   : 19
        VIDEO_1_M2 : 8

For this configuration, M is 593, Multiplier Fractional Frac M is 157286, SigmaDelta Divider (SD) is 3, HS2 mode

Shawn Rainey1 said:
HDMI Freq : 74.2 MHz ( M x 20 ) / ( (N+1) x M2 )
        HDMI_M   : 742
        HDMI_N   : 19
        HDMI_M2 : 10

For this configuration, M is 742, Multiplier Fractional Frac M is 0, SigmaDelta Divider (SD) is 3, HS2 mode

Shawn Rainey1 said:
VIDEO_1 Freq : 74.2 MHz ( M x 20 ) / ( (N+1) x M2 )
        VIDEO_1_M   : 1350
        VIDEO_1_N   : 25
        VIDEO_1_M2 : 14

For this configuration, M is 1350, Multiplier Fractional Frac M is 115343, SigmaDelta Divider (SD) is 5, HS1 mode

Shawn Rainey1 said:
HDMI Freq : 74.2 MHz ( M x 20 ) / ( (N+1) x M2 )
        HDMI_M   : 1350
        HDMI_N   : 25
        HDMI_M2 : 14

For this configuration, M is 1350, Multiplier Fractional Frac M is 115343, SigmaDelta Divider (SD) is 5, HS1 mode

See also if the below pointers will be in help:

BR
Pavel

0 Pavel Botev over 8 years ago

TI__Guru**** 170625 points

Shawn Rainey1 said:
(74.176MHz)

Shawn Rainey1 said:
VIDEO_1 Freq : 74.2 MHz ( M x 20 ) / ( (N+1) x M2 )
        VIDEO_1_M   : 594
        VIDEO_1_N   : 19
        VIDEO_1_M2 : 8

For 74.176MHz, M is 593, Multiplier Fractional Frac M is 106955, SigmaDelta Divider (SD) is 3, HS2 mode

Shawn Rainey1 said:
HDMI Freq : 74.2 MHz ( M x 20 ) / ( (N+1) x M2 )
        HDMI_M   : 742
        HDMI_N   : 19
        HDMI_M2 : 10

For 74.176MHz, M is 741, Multiplier Fractional Frac M is 199229, SigmaDelta Divider (SD) is 3, HS2 mode

Shawn Rainey1 said:
74.175824

Shawn Rainey1 said:
VIDEO_1 Freq : 74.2 MHz ( M x 20 ) / ( (N+1) x M2 )
        VIDEO_1_M   : 1350
        VIDEO_1_N   : 25
        VIDEO_1_M2 : 14

For 74.175824MHz, M is 1349, Multiplier Fractional Frac M is 262143, SigmaDelta Divider (SD) is 5, HS1 mode

Shawn Rainey1 said:
HDMI Freq : 74.2 MHz ( M x 20 ) / ( (N+1) x M2 )
        HDMI_M   : 1350
        HDMI_N   : 25
        HDMI_M2 : 14

For 74.175824MHz, M is 1349, Multiplier Fractional Frac M is 262143, SigmaDelta Divider (SD) is 5, HS1 mode

Regards,
Pavel

0 Shawn Rainey1 over 8 years ago in reply to Pavel Botev

Prodigy 230 points

I think our clock settings as is are OK. 1350,25,14 as M,N,M2 work well for matching the SMPTE standard of 74.25/1.001 MHz - but I must be missing something else.

This is how the video looks when the clock is set to 74.25/1.001 MHz. This is with our own timings, not any from TI. The PLL settings are superimposed to the right of the screen:

Another shot of the same, for reference:

In this mode, our reference monitor does lock to and stay stable at 720p59.9. It's difficult to see with static images, but the video itself is not stable. Because the monitor itself is staying in sync, I'm assuming the VENC timings are mostly OK.

Here's a shot with clock at 74.2 MHz. This is the way the driver released from TI sets the clock when the resolution is set to 720p59 or any other format where 74176 khz in ti_vdis_timings.h. As with the previous picture, PLL settings are superimposed to the right of the monitor.

The image is stable in this shot, but the reference monitor detects 720p60 when it should be 720p59.9. This happens because the pixel clock is too far away from 74.25/1.001 MHz, at 74.2MHz. The reference monitor will actually reset and switch between 720p59 and 720p60 at irregular intervals every few seconds.

So, the video is broken in the unmodified code because the pixel clock is too far from the specified 74.25/1.001 Mhz, causing confusion in our reference monitor and some of our other products. The video is broken in our code because changing the clock somehow causes the image to become unstable. The PLL values are the only things that change between versions, so I'm a bit stumped as to where the problem might be.

0 Pavel Botev over 8 years ago in reply to Shawn Rainey1

TI__Guru**** 170625 points

Looking at HDVPSS driver (linux-kernel/drivers/video/ti81xx/vpss/sysfs.h) I do not see this mode (74.25/1.001, 720p59.9) to be supported. The nearest is 74250,720p60 FVID2_STD_720P_60. So beside changing the pixel clock to 74.25/1.001 you should also change the output timings (VPSS/VENC registers, hsync/vsync config).

See if the below pointers will be in help:
e2e.ti.com/.../298263
e2e.ti.com/.../268949
e2e.ti.com/.../333561

Regards,
Pavel

0 Shawn Rainey1 over 8 years ago in reply to Pavel Botev

Prodigy 230 points

So it turns out there was something that didn't like the values I had chosen for the 74.25/1.001, even though the pixel clock was measured to be correct.

None of the posted settings worked, but it did get me on the right track. I was able to solve the problem by using settings close to the 720p60 PLL settings chosen by the driver algorithm and using the fractional portions to bring them to the correct frequency.

VIDEO_1 Freq  :  74.1 MHz ( M x 20 ) / ( (N+1) x M2 )
        VIDEO_1_M   : 593
        VIDEO_1_N   : 7
        VIDEO_1_M2  : 20

HDMI Freq  :  74.0 MHz ( M x 20 ) / ( (N+1) x M2 )
        HDMI_M   : 296
        HDMI_N   : 7
        HDMI_M2  : 10

Fractional M for Video1 and HDMI are 106586 and 184365 , respectively. Thanks for the suggestions.

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DM8107 Pixel Clock issue with n/1.001 Hz Display formats