i2c2 issue on ipnc rdk v 3.8.0

Akash Gajjar

Other Parts Discussed in Thread: TVP5158

hi,

i am using dm8127 processor on my custom camera board with ipnc rdk v 3.8.0, there is 4 i2c instance used on it.

i am able to access all peripherals connected to i2cs and is working fine when camera firmware is not running on system board.

but when i start camera firmware, i lose access of devices connected on i2c bus 2, when i access devices, it shows "i2c 2 controller timed out".

fyi, we are using i2c-2 instance on ball no AE21, AA20 with PINCNTL135,136 respectively.

on my board image sensor is connected on I2C bus 0 and we have modified the hdvpss and iss code, and system is

able to capture image from it. we've disabled some of pin muxing functionality of iss and hdvpss code which was over writing the i2c 2 pin mux.

i am using below source code:

Source/ti_tools/iss_03_80_00_00/packages/ti/psp/platforms/ti814x/src/iss_platformTI814x.c

Source/ti_tools/hdvpss_01_00_01_37/packages/ti/psp/platforms/ti814x/src/vps_platformTI814x.c

but result is still same.

Please let me know what is causing problem here on I2C bus 2.

Awaiting for your prompt response.

regards,

Akash

over 8 years ago

0 Pavel Botev over 8 years ago

TI__Guru**** 170625 points

Akash,

I am not familiar with IPNC, but in EZSDK we have an option to control the i2c when loading/starting firmware:

$firmware_loader <Cortex-M3 firmware> start -i2c 0/1
If we pass "-i2c 0", then the I2C access is from the Linux/Cortex-A8 side. If we pass "-i2c 1", then the I2C access is from the Cortex-M3 side.

We have similar option for vpss module:

$modprobe vpss i2c_mode=0/1

We choose the control source for the external i2c-based video devices, by default it is A8. When i2c_mode is set to 1, M3 controls external i2c-based video devices and it requires a special M3 firmware.

You might search for similar option at your side, to control i2c bus access when start/load your camera firmware.

Regards,
Pavel

0 Akash Gajjar over 8 years ago in reply to Pavel Botev

Intellectual 510 points

Pavel,

i am not familiar with EZSDK, and i have checked inside ipnc source code as you've suggested.
but there is not any functionality like that.

Regards,
Akash

0 Pavel Botev over 8 years ago in reply to Akash Gajjar

TI__Guru**** 170625 points

Note that i2c_mode=0/1 is not specific for EZSDK, but is valid for PSP package that comes with EZSDK, DVR RDK, IPNC RDK:
processors.wiki.ti.com/.../TI81XX_PSP_VPSS_Video_Driver_User_Guide

I will notify the IPNC RDK team for help.

Regards,
Pavel

0 Cesar over 8 years ago in reply to Pavel Botev

TI__Guru*** 138349 points

Akash,

Which software package are you using? The release notes should mention the PSP version used in that release.

thanks!
Cesar

0 Cesar over 8 years ago in reply to Cesar

TI__Guru*** 138349 points

HI

I see that you are using rdk v 3.8.0

The sw manifest for this release mentions "2.6.37-psp04.01.00.02"

Here are the release notes for this release

processors.wiki.ti.com/.../DM814x_C6A814x_AM387x_PSP_04.01.00.02_Release_Notes

Thanks
Cesar

0 Akash Gajjar over 8 years ago in reply to Cesar

Intellectual 510 points

Hi Cesar,

In This release note it's shows I2c is supported.

Regards,

Akash

0 Dwarakesh Radhakrishnan over 8 years ago

Guru 13620 points

Hi Akash,

Have you made sure both VPSS and ISS are not initializing the I2C2 in their code ?

VPSS:
In file:
Source/ti_tools/hdvpss_01_00_01_37/packages/ti/psp/platforms/ti814x/src/vps_platformTI814x.c
In function:
Vps_platformTI814xDeviceInit()

Around line no 344, comment these lines:

// deviceInitPrm.i2cRegs[VPS_PLATFORM_EVM_I2C_INST_ID]
// = (Ptr)CSL_TI814x_I2C2_BASE;
//deviceInitPrm.i2cIntNum[VPS_PLATFORM_EVM_I2C_INST_ID]
// = CSL_INTC_EVENTID_I2CINT2;
//deviceInitPrm.i2cClkKHz[VPS_PLATFORM_EVM_I2C_INST_ID]
// = 400;

ISS:
In file:
Source/ti_tools/iss_03_80_00_00/packages/ti/psp/platforms/ti814x/src/iss_platformTI814x.c
In function:
Iss_platformTI814xDeviceInit()

Around line no 379, comment these lines:

//deviceInitPrm.i2cRegs[ISS_PLATFORM_EVM_I2C_INST_ID]
// = (Ptr) CSL_TI814x_I2C2_BASE;
//deviceInitPrm.i2cIntNum[ISS_PLATFORM_EVM_I2C_INST_ID]
// = CSL_INTC_EVENTID_I2CINT2;
//deviceInitPrm.i2cClkKHz[ISS_PLATFORM_EVM_I2C_INST_ID] = 400;

And the above are made such that it uses i2c0.

example changes in ISS:

#define ISS_PLATFORM_EVM_I2C_INST_ID (ISS_DEVICE_I2C_INST_ID_0)

In function: Iss_platformTI814xDeviceInit()

deviceInitPrm.i2cRegs[VPS_PLATFORM_EVM_I2C_INST_ID]
= (Ptr)CSL_TI814x_I2C0_BASE;
deviceInitPrm.i2cIntNum[VPS_PLATFORM_EVM_I2C_INST_ID]
= CSL_INTC_EVENTID_I2CINT0;
deviceInitPrm.i2cClkKHz[VPS_PLATFORM_EVM_I2C_INST_ID]
= 400;

Thanks,
Dwarakesh R

0 Akash Gajjar over 8 years ago in reply to Dwarakesh Radhakrishnan

Intellectual 510 points

Hi Dwarakesh,

i have already did this in iss and vpss code, still i am getting controller timed out on i2c bus 2.

Regards,
Akash

0 Dwarakesh Radhakrishnan over 8 years ago in reply to Akash Gajjar

Guru 13620 points

Hi Akash,

Have you tried in the Board shell ?
$ devmem2 0x48140A18
and
$ devmem2 0x48140A1C

Try this before and after the Vpss M3 firmware is loaded. This should be same and have LSByte to be 0x40 for proper muxing in both the registers.

Can you share the output ?

0 Akash Gajjar over 8 years ago in reply to Dwarakesh Radhakrishnan

Intellectual 510 points

Hi Dwarkesh,

We have checked pinmuxing using devmem2 on board before camera firmware is running, it is 0xE0040 and i2c2 device is accessible.

after running firmware we noticed that pinmuxing is reverted by iss and vpss code pinmuxing.

now we've disabled pinmuxing as you have suggested and checking pinmuxing using devmem2 it is 0xE0040.

Regards,

Akash

0 Dwarakesh Radhakrishnan over 8 years ago in reply to Dwarakesh Radhakrishnan

Guru 13620 points

Hi Akash,

Also make sure,
In file : Source/ti_tools/iss_03_80_00_00/packages/ti/psp/platforms/ti814x/src/iss_platformTI814x.c

Around line no 700, the following lines are commented out. They are capable of overriding the pinmuxing.

//REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A18) = 0xE0001; /* vin0_de0_mux0 -
* DeSelect input */
//REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A1C) = 0xE0001; /* vin0_fld0_mux0 */

Similarly in hdvpss source,

In file : Source/ti_tools/hdvpss_01_00_01_37/packages/ti/psp/platforms/ti814x/src/vps_platformTI814x.c

Around line no 756, the following lines are commented.

//REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A18) = 0x0; /* vin0_de0_mux0 - DeSelect input */ //REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A1C) = 0x50001; /* vin0_fld0_mux0 */

0 Dwarakesh Radhakrishnan over 8 years ago in reply to Akash Gajjar

Guru 13620 points

Hi Akash,

Now after making sure pinmuxing is not changing before and after the Camera firmware load, are you still facing Controller timeout issue for I2C2 ?

0 Akash Gajjar over 8 years ago in reply to Dwarakesh Radhakrishnan

Intellectual 510 points

Hi Dwarakesh,

Yes, now pinmuxing as well as clock frequency is not overwritten by firmware.
i am facing controller time out issue for i2c2.

Regards,
Akash

0 Dwarakesh Radhakrishnan over 8 years ago in reply to Akash Gajjar

Guru 13620 points

Hi Akash,

Can you probe the I2C lines (clock and Data), before and after the firmware load and see any changes ?

Please do share your observations. Also it would be helpful if you can share your Board output(so that I can get a feel of what is happening) and the changes you have done so far. You can email me the logs.

0 Akash Gajjar over 8 years ago in reply to Dwarakesh Radhakrishnan

Intellectual 510 points

Hi Dwarakesh,

PFA attached file of my camera fiwmare log, iss and vpss code.

camera_firmware_log.txt

 [c6xdsp ] Remote Debug Shared Memory @ 0xbff00000
 [m3video] Remote Debug Shared Memory @ 0xbff05020
 [m3vpss ] Remote Debug Shared Memory @ 0xbff0a040
[  658.330000] SysLink version : 2.21.02.10
[  658.330000] SysLink module created on Date:Mar 18 2016 Time:17:46:00
[  658.340000] Trace enabled
[  658.340000] Trace SetFailureReason enabled
/dev/mem opened.
             Phy Addr : 0x48181560 Data : 0x00000002
secss put in low power state
             Phy Addr : 0x48180f10 Data : 0x00000000
             Phy Addr : 0x48180508 Data : 0x00000302
             Phy Addr : 0x48180520 Data : 0x00000002
             Phy Addr : 0x48180524 Data : 0x00000002
             Phy Addr : 0x48180528 Data : 0x00000002
             Phy Addr : 0x4c0000e4 Data : 0x0017020a
             Phy Addr : 0x4d0000e4 Data : 0x00000000
             Phy Addr : 0x4c0000e4 Data : 0x0017020a
             Phy Addr : 0x4d0000e4 Data : 0x00100000
DDR IOs RX is shutdown 

 [host]  Setting DMM priority for [HDVICP0 ] to [1] ( 0x4e000634 = 0x00000009 )

 [host]  Setting DMM priority for [ISS     ] to [0] ( 0x4e000634 = 0x00080000 )

 [host]  Setting L3 bandwidth regulator for [ISS     ] to [press=[3,3] BW=400, WM Cycles=2500]

 [host]  Setting L3 bandwidth regulator for [HDVICP0 ] to [press=[0,0] BW=900, WM Cycles=2500]
SafeSystem Init Success

SAFE_SYSTEM : Message To Safe-System Info: g_i32_MsgToSafeSysID - 0
SAFE_SYSTEM : Message From Safe-System Info: g_i32_MsgToSafeSysID - 32769
System Server interface Success
Config Manager Init Success

MAC address read : d4:f5:13:99:49:fe
NETWORK_MANAGER:IP mode 0
<NETWORK_MANAGER>UpdateManagementQos

<UPNPCLIENT> InitUpnpClient

<UPNP_Client>UpdateUpnpConfig 

NETWORK_MANAGER:Killing Inadyn(DDNS) Process
Message to Safe System Queue Open Success!!!
Message From Safe System Queue Open Success!!!
Waiting Reply for command :/etc/init.d/S70inadyn stop&
<UPNP_Client>updateUpnpThread
SAFE_SYSTEM : Waiting for reply!!!!
Stopping inadyn: 

NETWORK_MANAGER:Return l_i32_Ret 2bc
Message to Safe System Queue Open Success!!!
Message From Safe System Queue Open Success!!!
SAFE_SYSTEM : Waiting for reply!!!!
FAIL
Waiting Reply for command :./scripts/load_modules.sh&
Message to Safe System Queue Open Success!!!
Message From Safe System Queue Open Success!!!
SAFE_SYSTEM : Waiting for reply!!!!
Waiting Reply for command :./scripts/load_vpss.sh&
Message to Safe System Queue Open Success!!!
Message From Safe System Queue Open Success!!!
SAFE_SYSTEM : Waiting for reply!!!!
Waiting Reply for command :./scripts/load_video.sh&
Message to Safe System Queue Open Success!!!
Message From Safe System Queue Open Success!!!
SAFE_SYSTEM : Waiting for reply!!!!
Waiting Reply for command :./scripts/load_c6xdsp.sh&
Message to Safe System Queue Open Success!!!
Message From Safe System Queue Open Success!!!
SAFE_SYSTEM : Waiting for reply!!!!

 [host] Attached to slave procId 1.

 [host] Attached to slave procId 2.

 [host] Loaded file ./firmware/ipnc_rdk_fw_m3video.xem3 on slave procId 1.


 [host] Started slave procId 1.
 [host] Attached to slave procId 0.

 [host] Loaded file ./firmware/ipnc_rdk_fw_c6xdsp.xe674 on slave procId 0.

 [host] Started slave procId 0.

 [host] After Ipc_loadcallback status [0x00000000]
 [c6xdsp ] ***** SYSTEM  : Frequency <ORG> - 500000000, <NEW> - 500000000
 [c6xdsp ]  
 [c6xdsp ]  *** UTILS: CPU KHz = 500000 Khz ***
 [c6xdsp ]  
 [c6xdsp ]  7: SYSTEM  : System Common Init in progress !!!
 [c6xdsp ]  9: SYSTEM: IPC init in progress !!!

 [host] Loaded file ./firmware/ipnc_rdk_fw_m3vpss.xem3 on slave procId 2.

 [host] Started slave procId 2.

 [host] After Ipc_loadcallback status [0x00000000]
 [c6xdsp ]  11: SYSTEM: Attaching to [HOST] ... 
 [c6xdsp ]  63: SYSTEM: Attaching to [HOST] ... 

 [host] After Ipc_startcallback status [0x00000000]

 [host] After Ipc_loadcallback status [0x00000000]

 [host] After Ipc_startcallback status [0x00000000]
 [m3video] ***** SYSTEM  : Frequency <ORG> - 200000000, <NEW> - 200000000
 [m3vpss ] ***** SYSTEM  : Frequency <ORG> - 200000000, <NEW> - 200000000
 [c6xdsp ]  86: SYSTEM: Attaching to [HOST] ... SUCCESS !!!
 [m3video]  
 [m3vpss ] notify_attach  rtnVal  0
 [c6xdsp ]  88: SYSTEM: Attaching to [VIDEO-M3] ... 
 [m3video]  *** UTILS: CPU KHz = 400000 Khz ***
 [m3vpss ] initProxyServer  rtnVal  0
 [c6xdsp ]  140: SYSTEM: Attaching to [VIDEO-M3] ... 
 [m3video]  
 [m3vpss ]  
 [c6xdsp ]  191: SYSTEM: Attaching to [VIDEO-M3] ... 
 [m3video]  80: SYSTEM  : System Common Init in pr[  660.230000] asoc: tlv320aic3x-hifi <-> davinci-mcasp.0 mapping ok
ogress !!!
 [m3vpss ]  *** UTILS: CPU KHz = 400000 Khz ***
 [c6xdsp ]  242: SYSTEM: Attaching to [VIDEO-M3] ... 
 [m3video]  86: SYSTEM: IPC init in progress !!!
 [m3vpss ]  
 [c6xdsp ]  256: SYSTEM: Attaching to [VIDEO-M3] ... SUCCESS !!!
 [m3video]  90: SYSTEM: Attaching to [HOST] ... 
 [m3vpss ]  198: SYSTEM  : System Common Init in progress !!!
 [c6xdsp ]  258: SYSTEM: Attaching to [VPSS-M3] ... 
 [m3video]  144: SYSTEM: Attaching to [HOST] ... 
 [m3vpss ]  198: SYSTEM: IPC init in progress !!!
 [m3video]  157: SYSTEM: Attaching to [HOST] ... SUCCESS !!!
 [m3vpss ]  199: SYSTEM: Attaching to [HOST] ... 
 [m3video]  162: SYSTEM: Attaching to [DSP] ... 
 [m3vpss ]  248: SYSTEM: Attaching to [HOST] ... 
 [m3video]  212: SYSTEM: Attaching to [DSP] ... 
 [m3vpss ]  251: SYSTEM: Attaching to [HOST] ... SUCCESS !!!
 [m3video]  213: SYSTEM: Attaching to [DSP] ... SUCCESS !!!
 [m3vpss ]  251: SYSTEM: Attaching to [DSP] ... 
 [m3video]  213: SYSTEM: Attaching to [VPSS-M3] ... 
 [m3video]  262: SYSTEM: Attaching to [VPSS-M3] ... 
 [c6xdsp ]  310: SYSTEM: Attaching to [VPSS-M3] ... 

 [host] After Ipc_startcallback status [0x00000000]
 [c6xdsp ]  344: SYSTEM: Attaching to [VPSS-M3] ... SUCCESS !!!
 [m3vpss ]  300: SYSTEM: Attaching to [DSP] ... 
 [c6xdsp ]  346: SYSTEM: Opening MsgQ Heap [IPC_MSGQ_MSG_HEAP] ...
 [m3video]  312: SYSTEM: Attaching to [VPSS-M3] ... 
 [m3vpss ]  301: SYSTEM: Attaching to [DSP] ... SUCCESS !!!
 [m3vpss ]  301: SYSTEM: Attaching to [VIDEO-M3] ... 
numid=32,iface=MIXER,name='Line Playback Switch'
  ; type=BOOLEAN,access=rw------,values=2
  : values=on,on
 [m3video]  351: SYSTEM: Attaching to [VPSS-M3] ... SUCCESS !!!
 [m3vpss ]  350: SYSTEM: Attaching to [VIDEO-M3] ... 
 [m3video]  351: SYSTEM: Opening MsgQ Heap [IPC_MSGQ_MSG_HEAP] ...
 [m3vpss ]  351: SYSTEM: Attaching to [VIDEO-M3] ... SUCCESS !!!
 [m3video]  352: SYSTEM: Creating MsgQ [VIDEO-M3_MSGQ] ...
 [m3vpss ]  351: SYSTEM: Creating MsgQ Heap [IPC_MSGQ_MSG_HEAP] ...
 [m3video]  353: SYSTEM: Creating MsgQ [VIDEO-M3_ACK_MSGQ] ...
 [m3vpss ]  352: SYSTEM: Creating MsgQ [VPSS-M3_MSGQ] ...
 [m3vpss ]  352: SYSTEM: Creating MsgQ [VPSS-M3_ACK_MSGQ] ...
numid=78,iface=MIXER,name='Left Line Mixer DACL1 Switch'
  ; type=BOOLEAN,access=rw------,values=1
  : values=on
 [m3video]  354: SYSTEM: Notify register to [HOST] line 0, event 12 ... 
 [m3vpss ]  354: SYSTEM: Notify register to [HOST] line 0, event 12 ... 
 [m3video]  355: SYSTEM: Notify register to [DSP] line 0, event 12 ... 
 [m3vpss ]  354: SYSTEM: Notify register to [DSP] line 0, event 12 ... 
 [m3video]  355: SYSTEM: Notify register to [VPSS-M3] line 0, event 12 ... 
 [m3vpss ]  355: SYSTEM: Notify register to [VIDEO-M3] line 0, event 12 ... 
 [m3video]  355: SYSTEM: IPC init DONE !!!
 [m3vpss ]  355: SYSTEM: IPC init DONE !!!
numid=81,iface=MIXER,name='Left Line Mixer DACR1 Switch'
  ; type=BOOLEAN,access=rw------,values=1
  : values=on
Waiting Reply for command :./scripts/wait_cmd.sh s m3vpss
Message to Safe System Queue Open Success!!!
Message From Safe System Queue Open Success!!!
 [m3video]  366: MEM: Shared Region 2: Base = 0xb0000000, Length = 0x0f500000 (245 MB) 
 [m3vpss ]  365: MEM: Shared Region 2: Base = 0xb0000000, Length = 0x0f500000 (245 MB) 
 [m3video]  366: MEM: Shared Region 1: Base = 0x95400000, Length = 0x07600000 (118 MB) 
 [m3vpss ]  366: MEM: Shared Region 1: Base = 0x95400000, Length = 0x07600000 (118 MB) 
 [m3video]  368: SYSTEM  : System Common Init Done !!!
 [m3vpss ]  368: SYSTEM  : System Common Init Done !!!
SAFE_SYSTEM : Waiting for reply!!!!
Waiting Reply for command :./scripts/wait_cmd.sh s m3video
Message to Safe System Queue Open Success!!!
Message From Safe System Queue Open Success!!!
SAFE_SYSTEM : Waiting for reply!!!!
numid=72,iface=MIXER,name='Right Line Mixer DACL1 Switch'
  ; type=BOOLEAN,access=rw------,values=1
  : values=off
 [c6xdsp ]  456: SYSTEM: Opening MsgQ Heap [IPC_MSGQ_MSG_HEAP] ...
numid=75,iface=MIXER,name='Right Line Mixer DACR1 Switch'
  ; type=BOOLEAN,access=rw------,values=1
  : values=off
 [c6xdsp ]  459: SYSTEM: Creating MsgQ [DSP_MSGQ] ...
 [c6xdsp ]  461: SYSTEM: Creating MsgQ [DSP_ACK_MSGQ] ...
 [c6xdsp ]  466: SYSTEM: Notify register to [HOST] line 0, event 12 ... 
 [c6xdsp ]  469: SYSTEM: Notify register to [VIDEO-M3] line 0, event 12 ... 
 [c6xdsp ]  472: SYSTEM: Notify register to [VPSS-M3] line 0, event 12 ... 
 [c6xdsp ]  475: SYSTEM: IPC init DONE !!!
Simple mixer control 'PCM',0
  Capabilities: pvolume
  Playback channels: Front Left - Front Right
  Limits: Playback 0 - 127
  Mono:
  Front Left: Playback 127 [100%] [0.00dB]
  Front Right: Playback 127 [100%] [0.00dB]
Simple mixer control 'Line DAC',0
  Capabilities: pvolume
  Playback channels: Front Left - Front Right
  Limits: Playback 0 - 118
  Mono:
  Front Left: Playback 118 [100%] [0.00dB]
  Front Right: Playback 118 [100%] [0.00dB]
Simple mixer control 'HP DAC',0
  Capabilities: pvolume
  Playback channels: Front Left - Front Right
  Limits: Playback 0 - 118
  Mono:
  Front Left: Playback 118 [100%] [0.00dB]
  Front Right: Playback 118 [100%] [0.00dB]
numid=87,iface=MIXER,name='Right PGA Mixer Line2R Switch'
  ; type=BOOLEAN,access=rw------,values=1
  : values=on
numid=37,iface=MIXER,name='PGA Capture Volume'
  ; type=INTEGER,access=rw---R--,values=2,min=0,max=119,step=0
  : values=119,119
  | dBscale-min=0.00dB,step=0.50dB,mute=0
 [c6xdsp ]  554: MEM: Shared Region 2: Base = 0xb0000000, Length = 0x0f500000 (245 MB) 
 [c6xdsp ]  557: MEM: Shared Region 1: Base = 0x95400000, Length = 0x07600000 (118 MB) 
 [c6xdsp ]  564: SYSTEM  : System Common Init Done !!!
Waiting Reply for command :./scripts/wait_cmd.sh s c6xdsp
Message to Safe System Queue Open Success!!!
Message From Safe System Queue Open Success!!!
SAFE_SYSTEM : Waiting for reply!!!!
Waiting Reply for command :./bin/ipnc_rdk_mcfw.out 0 1 &Demo Application Run Success
SysRecvHandler Create Success
./bin/ipnc_rdk_mcfw.out: /usr/lib/libasound.so.2: no version information available (required by ./bin/ipnc_rdk_mcfw.out)
./bin/ipnc_rdk_mcfw.out: /usr/lib/libasound.so.2: no version information available (required by ./bin/ipnc_rdk_mcfw.out)
 init_Msg_Func 

Message to Safe System Queue Open Success!!!
SAFE_SYSTEM : Waiting for reply!!!!
Message From Safe System Queue Open Success!!!
Waiting Reply for command :./scripts/send_cmd.sh T m3vpss
Message to Safe System Queue Open Success!!!
Message From Safe System Queue Open Success!!!
SAFE_SYSTEM : Waiting for reply!!!!
Waiting Reply for command :./scripts/send_cmd.sh T m3video
Message to Safe System Queue Open Success!!!
Message From Safe System Queue Open Success!!!
SAFE_SYSTEM : Waiting for reply!!!!
Waiting Reply for command :./scripts/send_cmd.sh T c6xdsp
Message to Safe System Queue Open Success!!!
Message From Safe System Queue Open Success!!!
SAFE_SYSTEM : Waiting for reply!!!!
 [m3video]  568: SYSTEM  : System Video Init in progress !!!
 [m3vpss ]  567: SYSTEM  : System VPSS Init in progress !!!
 [m3video]  569: SYSTEM: Creating ListMP [VIDEO-M3_IPC_OUT_0] in region 0 ...
 [m3vpss ] === I2C0/2 Clk is active ===
 [c6xdsp ]  661: SYSTEM  : System DSP Init in progress !!!
 [m3video]  569: SYSTEM: Creating ListMP [VIDEO-M3_IPC_IN_0] in region 0 ...
 [m3vpss ] PLATFORM: UNKNOWN CPU detected, defaulting to VPS_PLATFORM_CPU_REV_2_1
 [c6xdsp ]  679: SYSTEM: Creating ListMP [DSP_IPC_OUT_24] in region 0 ...
 [m3video]  570: SYSTEM: ListElem Shared Addr = 0xbf58b680
 [m3vpss ]  PLATFORM: UNKNOWN CPU detected, defaulting to ISS_PLATFORM_CPU_REV_2_1
 [c6xdsp ]  682: SYSTEM: Creating ListMP [DSP_IPC_IN_24] in region 0 ...
 [m3video]  572: SYSTEM: Creating ListMP [VIDEO-M3_IPC_OUT_1] in region 0 ...
 [m3vpss ]  587: SYSTEM: Creating ListMP [VPSS-M3_IPC_OUT_0] in region 0 ...
 [c6xdsp ]  685: SYSTEM: ListElem Shared Addr = 0xbf65ea80
 [m3video]  572: SYSTEM: Creating ListMP [VIDEO-M3_IPC_IN_1] in region 0 ...
 [m3vpss ]  587: SYSTEM: Creating ListMP [VPSS-M3_IPC_IN_0] in region 0 ...
 [c6xdsp ]  692: SYSTEM: Creating ListMP [DSP_IPC_OUT_25] in region 0 ...
 [m3video]  573: SYSTEM: ListElem Shared Addr = 0xbf58eb80
 [m3vpss ]  587: SYSTEM: ListElem Shared Addr = 0xbf5c5980
 [c6xdsp ]  695: SYSTEM: Creating ListMP [DSP_IPC_IN_25] in region 0 ...
 [m3video]  582: SYSTEM: Creating ListMP [VIDEO-M3_IPC_OUT_29] in region 0 ...
 [m3vpss ]  590: SYSTEM: Creating ListMP [VPSS-M3_IPC_OUT_1] in region 0 ...
 [c6xdsp ]  698: SYSTEM: ListElem Shared Addr = 0xbf67e480
 [m3video]  583: SYSTEM: Creating ListMP [VIDEO-M3_IPC_IN_29] in region 0 ...
 [m3vpss ]  590: SYSTEM: Creating ListMP [VPSS-M3_IPC_IN_1] in region 0 ...
 [c6xdsp ]  704: SYSTEM: Creating ListMP [DSP_IPC_OUT_26] in region 0 ...
 [m3video]  583: SYSTEM: ListElem Shared Addr = 0xbf592080
 [m3vpss ]  590: SYSTEM: ListElem Shared Addr = 0xbf5c8e80
 [c6xdsp ]  708: SYSTEM: Creating ListMP [DSP_IPC_IN_26] in region 0 ...
 [m3video]  585: SYSTEM: Creating ListMP [VIDEO-M3_IPC_OUT_30] in region 0 ...
 [m3vpss ]  604: SYSTEM: Creating ListMP [VPSS-M3_IPC_OUT_24] in region 0 ...
 [c6xdsp ]  711: SYSTEM: ListElem Shared Addr = 0xbf69de80
 [m3video]  586: SYSTEM: Creating ListMP [VIDEO-M3_IPC_IN_30] in region 0 ...
 [m3vpss ]  605: SYSTEM: Creating ListMP [VPSS-M3_IPC_IN_24] in region 0 ...
 [c6xdsp ]  717: SYSTEM: Creating ListMP [DSP_IPC_OUT_29] in region 0 ...
 [m3video]  586: SYSTEM: ListElem Shared Addr = 0xbf5abd00
 [m3vpss ]  605: SYSTEM: ListElem Shared Addr = 0xbf5cc380
 [c6xdsp ]  721: SYSTEM: Creating ListMP [DSP_IPC_IN_29] in region 0 ...
 [m3video]  588: HDVICP: Doing PRCM for IVAHD[0] ... 
 [m3vpss ]  608: SYSTEM: Creating ListMP [VPSS-M3_IPC_OUT_25] in region 0 ...
 [c6xdsp ]  724: SYSTEM: ListElem Shared Addr = 0xbf6bd880
 [m3video]  588: HDVICP: PRCM for IVAHD[0] ... DONE.
 [m3vpss ]  608: SYSTEM: Creating ListMP [VPSS-M3_IPC_IN_25] in region 0 ...
 [c6xdsp ]  730: SYSTEM: Creating ListMP [DSP_IPC_OUT_30] in region 0 ...
 [m3video]  589: SYSTEM  : Initializing Links !!! 
 [m3vpss ]  608: SYSTEM: ListElem Shared Addr = 0xbf5ebd80
 [c6xdsp ]  733: SYSTEM: Creating ListMP [DSP_IPC_IN_30] in region 0 ...
 [m3vpss ]  611: SYSTEM: Creating ListMP [VPSS-M3_IPC_OUT_26] in region 0 ...
 [c6xdsp ]  736: SYSTEM: ListElem Shared Addr = 0xbf6d7500
 [m3video]  589: SYSTEM  : FREE SPACE : System Heap      = 6282072 B, Mbx = 10240 msgs) 
 [m3vpss ]  611: SYSTEM: Creating ListMP [VPSS-M3_IPC_IN_26] in region 0 ...
 [c6xdsp ] !!WARNING.Resource already registered:2
 [c6xdsp ]  742: SYSTEM  : Initializing Links !!! 
 [m3vpss ]  612: SYSTEM: ListElem Shared Addr = 0xbf60b780
 [m3video]  590: SYSTEM  : FREE SPACE : SR0 Heap         = 3372928 B (3 MB) 
 [m3vpss ]  618: SYSTEM: Creating ListMP [VPSS-M3_IPC_OUT_29] in region 0 ...
 [c6xdsp ]  748: SYSTEM  : FREE SPACE : System Heap      = 6282440 B, Mbx = 10240 msgs) 
 [m3vpss ]  618: SYSTEM: Creating ListMP [VPSS-M3_IPC_IN_29] in region 0 ...
 [m3video]  590: SYSTEM  : FREE SPACE : Frame Buffer     = 256900992 B (244 MB) 
 [m3vpss ]  619: SYSTEM: ListElem Shared Addr = 0xbf62b180
 [c6xdsp ]  797: SYSTEM  : Initializing Links ... DONE !!! 
 [m3vpss ]  621: SYSTEM: Creating ListMP [VPSS-M3_IPC_OUT_30] in region 0 ...
 [m3video]  590: SYSTEM  : FREE SPACE : Bitstream Buffer = 123731840 B (117 MB) 
 [m3vpss ]  621: SYSTEM: Creating ListMP [VPSS-M3_IPC_IN_30] in region 0 ...
 [c6xdsp ]  799: SYSTEM  : System DSP Init Done !!!
 [m3vpss ]  622: SYSTEM: ListElem Shared Addr = 0xbf644e00
 [m3video]  591: SYSTEM: Opening MsgQ [VPSS-M3_MSGQ] ...
 [m3vpss ]  624: SYSTEM : HDVPSS Drivers Version: HDVPSS_01_00_01_37
 [m3video]  592: SYSTEM  : FREE SPACE : Tiler Buffer     = 256 B (0 MB)  - TILER OFF 
 [m3vpss ]  624: SYSTEM  : FVID2 Init in progress !!!
 [m3vpss ] PLATFORM: UNKNOWN CPU detected, defaulting to VPS_PLATFORM_CPU_REV_2_1
 [m3video] Entered the MctnfLink_init() 
 [m3vpss ]  693: SYSTEM  : FVID2 Init in progress DONE !!!
 [m3video]  651: SYSTEM  : Initializing Links ... DONE !!! 
 [m3vpss ]  694: SYSTEM  : Device Init in progress !!!
 [m3vpss ]  Iss_init called !!!!!! 
 [m3video]  652: SYSTEM  : System Video Init Done !!!
 [m3vpss ]  CPIS_init DONE !!!!!! 
 [m3vpss ] initPrms.isI2cInitReq = 1
 [m3vpss ] initPrms.isI2cInitReq = 1
 [m3vpss ]  Vps_deviceInit Daughter card not detected/connected! 
 [m3vpss ]  I2C0: Passed for address 0x10 !!! 

NETWORK_MANAGER:STATIC IP
NETWORK_MANAGER:setIp set IP calling
NETWORK_MANAGER:Failed IOCTL to Delete Default Route Entry
Lan status is UP now<UPNPCLIENT>Signaling port mapping thread 
 [m3vpss ]  I2C0: Passed for address 0x2d !!! 
 [m3vpss ]  I2C0: Passed for address 0x34 !!! 
<UPNPCLIENT>Signaling port mapping thread 
 [m3vpss ] Vps_platformTI814xDeviceInit: deviceInitPrm.i2cClkKHz[ISS_DEVICE_I2C_INST_ID_2] : 65535
 [m3vpss ] ###### ISS_DEVICE_I2C_INST_ID_2 : 2
 [m3vpss ] Vps_platformTI814xDeviceInit: deviceInitPrm.i2cClkKHz[ISS_DEVICE_I2C_INST_ID_2] : 100
 [m3vpss ] ###### ISS_DEVICE_I2C_INST_ID_2 : 2
 [m3vpss ]  3418: SYSTEM  : Device Init in progress DONE !!!
 [m3vpss ] Iss_platformTI814xDeviceInit: deviceInitPrm.i2cClkKHz[ISS_PLATFORM_EVM_I2C_INST_ID] : -1648108868
 [m3vpss ] ###### ISS_PLATFORM_EVM_I2C_INST_ID : 0
 [m3vpss ] Iss_platformTI814xDeviceInit: deviceInitPrm.i2cClkKHz[ISS_DEVICE_I2C_INST_ID_2] : 100
 [m3vpss ] ###### ISS_DEVICE_I2C_INST_ID_2 : 2
 [m3vpss ]  3448: SYSTEM  : System VPSS Init Done !!!
 [m3vpss ]  3448: UTILS: DMA: HWI Create for INT62 !!!
 [m3vpss ]  3448: SYSTEM  : Initializing Links !!! 
 [m3vpss ]  3449: SYSTEM  : FREE SPACE : System Heap      = 1677496 B, Mbx = 10240 msgs) 
 [m3vpss ]  3449: SYSTEM  : FREE SPACE : SR0 Heap         = 2159744 B (2 MB) 
 [m3vpss ]  3449: SYSTEM  : FREE SPACE : Frame Buffer     = 252590976 B (240 MB) 
 [m3vpss ]  3450: SYSTEM  : FREE SPACE : Bitstream Buffer = 123731840 B (117 MB) 
 [m3vpss ]  3450: SYSTEM  : FREE SPACE : Tiler Buffer     = 256 B (0 MB)  - TILER OFF 

 [m3vpss ]  3583: SYSTEM  : Initializing Links ... DONE !!! 
Waiting Reply for command :./scripts/wait_cmd.sh t m3vpss
Message to Safe System Queue Open Success!!!
Message From Safe System Queue Open Success!!!
SAFE_SYSTEM : Waiting for reply!!!!
Waiting Reply for command :./scripts/wait_cmd.sh t m3video
Message to Safe System Queue Open Success!!!
Message From Safe System Queue Open Success!!!
SAFE_SYSTEM : Waiting for reply!!!!
Waiti[  663.550000] DMA: Module install successful, device major num = 247 
ng Reply for com[  663.560000] DRV: Module install successful
mand :./scripts/[  663.560000] DRV: Module built on Mar 18 2016 17:52:41 
wait_cmd.sh t c6xdsp
Message to Safe System Queue Open Success!!!
Message From Safe System Queue Open Success!!!
SAFE_SYSTEM : Waiting for reply!!!!
Waiting Reply for command :./scripts/osa_kermod_load.sh &
 [host] Application Start Completed

 [host]  0: SYSTEM: System Common Init in progress !!!

 [host]  0: SYSTEM: IPC init in progress !!!

 [host]  22: SYSTEM: CPU [DSP] syslink proc ID is [0] !!!

 [host]  22: SYSTEM: CPU [VIDEO-M3] syslink proc ID is [1] !!!

 [host]  22: SYSTEM: CPU [VPSS-M3] syslink proc ID is [2] !!!

 [host]  22: SYSTEM: CPU [HOST] syslink proc ID is [3] !!!

 [host]  22: SYSTEM: Opening MsgQ Heap [IPC_MSGQ_MSG_HEAP] ...

 [host]  24: SYSTEM: Creating MsgQ [HOST_MSGQ] ...

 [h[  663.690000] DMA: ChannelID allocated:4
ost]  25: SYSTEM: Creating MsgQ [HOST_ACK_MSGQ] ...

 [host]  26: SYSTEM: Opening MsgQ [DSP_MSGQ] ...

 [host]  26: SYSTEM: Opening MsgQ [VIDEO-M3_MSGQ] ...

 [host]  27: SYSTEM: Opening MsgQ [VPSS-M3_MSGQ] ...

 [host]  29: SYSTEM: Notify register to [DSP] line 0, event 12 ... 

 [host]  29: SYSTEM: Notify register to [VIDEO-M3] line 0, event 12 ... 

 [host]  30: SYSTEM: Notify register to [VPSS-M3] line 0, event 12 ... 

 [host]  30: SYSTEM: IPC init DONE !!!

 [host]  34: SYSTEM: Creating ListMP [HOST_IPC_OUT_29] in region 0 ...

 [host]  36: SYSTEM: Creating ListMP [HOST_IPC_IN_29] in region 0 ...

 [host]  37: SYSTEM: ListElem Shared Addr = 0x40df2180

 [host]  37: SYSTEM: Creating ListMP [HOST_IPC_OUT_30] in region 0 ...

 [host]  38: SYSTEM: Creating ListMP [HOST_IPC_IN_30] in region 0 ...

 [host]  39: SYSTEM: ListElem Shared Addr = 0x40e0be00

 [host]  42: SYSTEM: Creating ListMP [HOST_IPC_OUT_24] in region 0 ...

 [host]  43: SYSTEM: Creating ListMP [HOST_IPC_IN_24] in region 0 ...

 [host]  44: SYSTEM: ListElem Shared Addr = 0x40e25a80

 [host]  45: SYSTEM: Creating ListMP [HOST_IPC_OUT_25] in region 0 ...

 [host]  46: SYSTEM: Creating ListMP [HOST_IPC_IN_25] in region 0 ...

 [host]  47: SYSTEM: ListElem Shared Addr = 0x40e45480

 [host]  47: SYSTEM: Creating ListMP [HOST_IPC_OUT_26] in region 0 ...

 [host]  49: SYSTEM: Creating ListMP [HOST_IPC_IN_26] in region 0 ...

 [host]  50: SYSTEM: ListElem Shared Addr = 0x40e64e80

 [host]  50: SYSTEM: System Common Init Done !!!

 [host] Vsys_allocBuf - addr = 0x4f5bc000,size = 65011712
cirBufBasePhy : [8d400000] 
cirBufBaseVirt : [4f5bc000] 
##########pInfo->totalsize 63373696 
##########pInfo->start_phyAddr 8d400000 
MEM Info : Total Size :  63373696MEM Info : Total channel :  4
 [host] MEM Info : Channel : 0 Start Add : 1331412992 Size : 31457152 

 [host] MEM Info : Channel : 1 Start Add : 1362870400 Size : 15728512 

 [host] MEM Info : Channel : 2 Start Add : 1378599168 Size : 15728512 

 [host] MEM Info : Channel : 3 Start Add : 1394327936 Size : 458752 
MEM Info : Free Size :  0 MEM_INIT Success 
memMng_memcpy_open:OSA_dmaOpen passed with ch id = 4

 [host] MCFW_IPCFRAMES:app_ipcFramesSendRecvFxn:Entered...
 [host] Vsys_allocBuf - addr = 0x55029000,size = 33603

 [host] DCC buffer allocated for size 33603

 [host] DCC Default File Intialization Done

 [host] 
********** FULL FEATURE USECASE ********

 [host] 
********* Entered Tri Streaming usecase - H264 1080p @60fps + H264 D1 @30fps + MJPEG 1080p @5fps ********

 [host] 
*************2MP without WDR Use-Case *************************

 [host]  69: MCFW  : CPU Revision [ES2.1] !!! 

 [host]  69: MCFW  : Detected [UNKNOWN] Board !!! 

 [host]  69: MCFW  : Base Board Revision [REV A] !!! 

 [host] 
********** SYSTEM_DF_YUV422I_UYVY ********

 [host] 
********** NSF LINK CREATION ********

 [host] 
********** NSF --> 1:1 strength:0*******
 [m3vpss ]  3587: CAMERA: Create in progress !!!
 [m3vpss ]  Channel Num Stream 0 Ch 0 ChannelNum 0
 [m3vpss ]  Channel Num Stream 1 Ch 0 ChannelNum 1
 [m3vpss ]  3588: CAMERA: VIP0 PortA camera mode is [ 8-bit, Non-mux Embedded Sync] !!! 
 [m3vpss ] <links_m3vpss/camera/cameraLink_drv.c>:FVID2_create:0:0
 [m3vpss ] <ar0331/src/issdrv_ar0331Api.c>:usecase:0 & wdr:0 Current usecaseId:1
 [m3vpss ] <Iss_SetUsecaseMode>:2MP without WDR!!
 [m3vpss ] <Iss_Ar0331Create>:Changing Sensor setting New usecaseId:1
 [m3vpss ]  I2C0: DEV 0x2d: RD 0x00 = 0x20 
 [m3vpss ]  I2C0: DEV 0x2d: WR 0x09 = 0x24 
 [m3vpss ]  I2C0: DEV 0x2d: WR 0x0a = 0x22 
 [m3vpss ]  I2C0: DEV 0x2d: WR 0x0b = 0x07 
 [m3vpss ]  I2C0: DEV 0x2d: WR 0x0c = 0x80 
 [m3vpss ]  I2C0: DEV 0x2d: WR 0x0d = 0x04 
 [m3vpss ]  I2C0: DEV 0x2d: WR 0x0e = 0x38 
 [m3vpss ]  I2C0: DEV 0x2d: RD 0x09 = 0x24 
 [m3vpss ] ########################################  IMGS_MICRON_AR0331_NO_WDR linear case :1##################
 [m3vpss ] ########  Linear 2MP60FPS #########
 [m3vpss ] started Demo Init with AR0331#207
 [m3vpss ]  I2C0: DEV 0x10: WR 0x301a = 0x01 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x301a = 0x10d8 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3088 = 0x8000 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x4a03 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x4316 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x443 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x1645 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x4045 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x6017 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x5045 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x404b 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x1244 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x6134 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x4a31 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x4342 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x4560 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x2714 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x3dff 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x3dff 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x3dea 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x2704 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x3d10 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x2705 ... ERROR !!! 
 [m3vpss ] I2C write Error,index:22
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x3d10 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x2715 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x3527 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x53d 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x1045 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x4027 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x427 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x143d 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0xff3d 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0xff3d 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0xea62 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x2728 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x3627 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x83d ... ERROR !!! 
 [m3vpss ] I2C write Error,index:36
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x6444 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x2c2c 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x2c2c 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x4b01 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x432d 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x4643 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x1647 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x435f 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x4f50 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x2604 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x2694 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x2027 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0xfc53 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0xd5c 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0xd57 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x5417 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x955 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x5649 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x5307 
 [m3vpss ]  I2C0[  664.310000] DMA: ChannelID allocated:5
: DEV 0x10: WR 0x3086 = 0x5303 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x4d28 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x6c4c 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x928 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x2c28 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x294e 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x5c09 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x4500 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x4580 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x26b6 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x27f8 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x1702 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x27fa 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x5c0b 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x1718 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x26b2 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x5c03 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x1744 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x27f2 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x1702 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x2809 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x1710 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x1628 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x84d 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x1a26 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x9316 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x1627 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0xfa45 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0xa017 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x727 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0xfb17 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x2945 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x8017 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x827 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0xfa17 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x285d 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x170e 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x2691 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x5301 
 [m3vpss ]  I[  664.480000] DMA: ChannelID allocated:6
2C0: DEV 0x10: WR 0x3086 = 0x1740 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x5302 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x1710 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x2693 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x2692 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x484d 

 [host] Vsys_eventHandler:OSA_dmaOpen passed with ch id = 5
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x4e28 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x94c 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0xb17 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x5f27 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0xf217 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x1428 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x816 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x4d1a 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x1616 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x27fa 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x2603 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x5c01 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x4540 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x2798 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x172a 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x4a0a 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x4316 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0xb43 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x279c 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x4560 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x1707 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x279d 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x1725 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x4540 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x1708 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x2798 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x5d53 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0xd26 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x455c 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x14b 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x1244 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x5251 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x1702 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x6018 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x4a03 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x4316 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x443 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x1658 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x4316 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x5943 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x165a 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x4316 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x5b43 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x4540 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x279c 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x4560 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x1707 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x279d 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x1725 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x4540 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x1710 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x2798 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x1720 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x224b 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x1244 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x2c2c 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3086 = 0x2c2c 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x301a = 0x58 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x30b0 = 0x00 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x30ba = 0x6ec 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x31ac = 0xc0c 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x302a = 0x06 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x302c = 0x01 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x302e = 0x0b 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3030 = 0xc4 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3036 = 0x0c 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3038 = 0x01 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x31ae = 0x304 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x31c6 = 0x8404 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3002 = 0xe6 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3004 = 0x42 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3006 = 0x521 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3008 = 0x7c9 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x300a = 0x461 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x300c = 0x44c 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x30a2 = 0x01 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x30a6 = 0x01 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3040 = 0x00 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3082 = 0x0d 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3012 = 0x464 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x305e = 0x80 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x318c = 0x00 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3190 = 0x00 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x301e = 0xa8 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x30fe = 0x80 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x320a = 0x80 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x301a = 0x58 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x2400 = 0x03 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x2450 = 0x00 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x301e = 0xa8 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x301a = 0x5c 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3200 = 0x00 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x31d0 = 0x00 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x31e0 = 0x200 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3060 = 0x06 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3064 = 0x1802 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x301a = 0x5e 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3180 = 0x8089 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x30f4 = 0x4000 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3ed4 = 0x8f6c 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3ed6 = 0x66cc 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3eda = 0x8899 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3ee6 = 0xf0 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3ed2 = 0x106 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x3ed8 = 0x8c42 
 [m3vpss ]  I2C0: DEV 0x10: WR 0x301a = 0x5c 
NETWORK_MANAGER:Updating Static IP change to UPNP and RTSP<UPNPCLIENT>Signaling port mapping thread 

 [host] Vsys_eventHandler:OSA_dmaOpen passed with ch id = 6
 [m3vpss ] Finished Demo Init with AR0331
 [m3vpss ]  3657: CAMERA: VIP 0: VID DEC 268436737 (0x10): 0002:20202020:20202020, AUD_STATUS 538976288
 [m3vpss ] <CameraLink_drvCreateInst>:FVID2_create:0
 [m3video]  4922: IPC_IN_M3   : Create in progress !!!
 [m3vpss ] Iss_captCreate:1661
 [m3video]  4923: SYSTEM: Opening ListMP [VPSS-M3_IPC_OUT_0] ...
 [m3video]  4923: SYSTEM: Opening ListMP [VPSS-M3_IPC_IN_0] ...
 [m3vpss ] <CameraLink_drvCreateInst>:FVID2_create:standard:d
 [m3video]  4927: IPC_IN_M3   : Create Done !!!
 [m3vpss ] 2MP standard:13
 [m3video]  4927: ENCODE: Create in progress ... !!!
 [m3vpss ]  3871: CAMERA: Create Done !!!
 [m3vpss ]  3871: CAMERA: Detect video in progress !!!
 [m3vpss ]  3871: CAMERA: Detect video Done !!!
 [m3vpss ]  4068: NSF: Create in progress !!!
 [m3vpss ] NSF::HEAPID:0        USED:128
 [m3vpss ] NSF::HEAPID:1        USED:4928
 [m3vpss ]  4235: NSF: Create Done !!!
 [m3vpss ]  4241: DUP   : Create Done !!!
 [m3vpss ]  4245: SCLR: Create in progress !!!
 [m3vpss ]  4369: SCLR    : Loading Up-scaling Co-effs ... 
 [m3vpss ]  4369: SCLR    : Co-effs Loading ... DONE !!!
 [m3vpss ] SCLR:HEAPID:0        USED:64
 [m3vpss ] SCLR:HEAPID:1        USED:5952
 [m3vpss ]  4370: SCLR: Create Done !!!
 [m3vpss ]  4370: Mux   : Creating... !!!
 [m3vpss ]  4372: Mux   : Create Done !!!
 [m3vpss ] <SwosdLink_create>strId 0 swOsdEnable 1
 [m3vpss ] <SwosdLink_create>strId pChInfo->pitch[0] 1920 pChInfo->pitch[1] 1920
 [m3vpss ] <SwosdLink_create>pChInfo->width 1920 pChInfo->height 1080
 [m3vpss ] {SWOSD} edma3Handle->tccVal = 36 
 [m3vpss ] {SWOSD} edma3Handle->chId   = 36 
 [m3vpss ] <SwosdLink_create>strId 1 swOsdEnable 1
 [m3vpss ] <SwosdLink_create>strId pChInfo->pitch[0] 704 pChInfo->pitch[1] 704
 [m3vpss ] <SwosdLink_create>pChInfo->width 704 pChInfo->height 480
 [m3vpss ] {SWOSD} edma3Handle->tccVal = 37 
 [m3vpss ] {SWOSD} edma3Handle->chId   = 37 
 [m3video]  5044: ENCODE: Creating CH0 of 1920 x 1080, pitch = (1920, 1920) [PROGRESSIVE] [NON-TILED  ], bitrate = 8000 Kbps ... 
 [m3vpss ] <SwosdLink_create>strId 2 swOsdEnable 1
 [m3vpss ] <SwosdLink_create>strId pChInfo->pitch[0] 1920 pChInfo->pitch[1] 1920
 [m3vpss ] <SwosdLink_create>pChInfo->width 1920 pChInfo->height 1080
 [m3vpss ] {SWOSD} edma3Handle->tccVal = 38 
 [m3vpss ] {SWOSD} edma3Handle->chId   = 38 
 [m3vpss ]  4384: SYSTEM: Opening MsgQ [HOST_MSGQ] ...
 [m3vpss ] @<ti_swosd.c>SWOSD_DBG:Default Icon TI Logo 80x32
 [m3vpss ] @<ti_swosd.c>SWOSD_DBG:Default Icon TI Logo 160x64
 [m3vpss ] SWOSD_CREATE:<0>higth:1080 Width:1920
 [m3vpss ]  width 1920
 [m3vpss ] SWOSD_CREATE:<1>higth:480 Width:704
 [m3video] ENCLINK_H264:HEAPID:0        USED:13272
 [m3video]  5093: ENCODE: Creating CH1 of 704 x 480, pitch = (704, 704) [PROGRESSIVE] [NON-TILED  ], bitrate = 8000 Kbps ... 
 [m3vpss ]  width 704
 [m3vpss ] @770SWOSD_WINDOW_ONE:bmpWinPrm.width :772
 [m3vpss ] @770SWOSD_WINDOW_TWO:bmpWinPrm.width :770
 [m3vpss ] SWOSD_CREATE:<2>higth:1080 Width:1920
 [m3vpss ]  width 1920
 [m3vpss ] ==>VPS_link Create successfully 0
 [m3vpss ]  4723: SWOSD   : Create Done !!!
 [m3vpss ]  4921: IPC_OUT_M3   : Create in progress !!!
 [m3vpss ]  4922: IPC_OUT_M3   : Create Done !!!
 [m3video] ENCLINK:H264Enc !!WARNING!!!Allocated MV data size (31680) is less than calculated by codec (85836)

 [host] IpcBitsInLink_tskMain:Entered
 [host]  1435: IPC_BITS_IN   : Create in progress !!!

 [host]  1435: IPC_BITS_IN   : ListMPOpen start !!!

 [host]  1435: SYSTEM: Opening ListMP [VIDEO-M3_IPC_OUT_29] ...

 [host]  1436: SYSTEM: Opening ListMP [VIDEO-M3_IPC_IN_29] ...

 [host]  1438: IPC_BITS_IN   : ListMPOpen done !!!

 [host]  1439: IPC_BITS_IN   : System_linkGetInfo done !!!

 [host]  1439: IPC_BITS_IN   : Create Done !!!

 [host] 
 2MP WITH OUT WDR USECASE SETUP DONE
 [m3vpss ]  4958: CAMERA: Start in progress !!!
 [m3video] ENCLINK_H264:HEAPID:0        USED:11720
 [m3vpss ]  4958: CAMERA: Start Done !!!
 [m3video]  5141: ENCODE: Creating CH2 of 1920 x 1080, pitch = (1920, 1920) [PROGRESSIVE] [NON-TILED  ], bitrate = 100 Kbps ... 
 [m3video] ENCLINK_JPEG:HEAPID:0        USED:4368
 [m3video]  5142: ENCODE: All CH Create ... DONE !!!
 [m3video] ENCLINK:HEAPID:0     USED:29688
 [m3video]  5145: ENCODE: Create ... DONE !!!
 [m3video]  5070: VSTAB   : Alg Create Done !!!
 [m3video]  5071: VSTAB   : Create Done !!!
 [m3video]  5146: IPC_BITS_OUT   : Create in progress !!!
 [m3video]  5148: IPC_BITS_OUT   : Create Done !!!

 [host] 
 Audio capture task created [m3vpss ] CT: 1000, 3dlut index:0 
 [m3vpss ]  5088: CAMERA: Fields = 2 (fps = 0), Total Resets = 0 (Avg 0 ms per reset)
 [m3video]  Channel:1 inputframerate:30 targetfps:60
 [m3video]  Channel:2 inputframerate:60 targetfps:5
 [m3video]  Channel:0 inputframerate:60 targetfps:60

 [host] AUDIO : period size = 500 frames, dir = 0

 [host] AUDIO : period time = 62500 us, dir = 0

 [host] 
Application Run Completed
MSG_CMD_GET_PHY_MEM case 
Updated DST if any [DST Normal]Avserver Initialized
AV server Time Update Success 
Brightness Updated Successfully
Sharpness Updated Successfully
Contrast Updated Successfully
Saturation Updated Successfully
Gain Updated Successfully
Shutter Updated Successfully 
Flicker Updated Successfully 
Orientation Type Updated Successfully 

Enable Channel: 0
 [host] 
Disable Channel: 0 [m3video]  6411: ENCODE: CH0: 
 [m3video] Queueing codec switch reqObj into IVA [0]
 [m3video] MemoryLeak:STAGE:0   HEAPNUM:0       ALLOC=13272     FREED=11720

 [host] 
Enable Channel: 0Profile 0 Updated 
Profile 0 fps Updated 
Profile 0 codec Updated 
Profile 0 fps Updated 
Profile 0 fps Updated 

 [host] 
 Channel Selected: 0,rate control = 0Profile 0 bitrate type Updated 

 [host] 
 Channel Selected: 52Profile 0 image quality Updated 

 [host] 
 Channel Selected: 0Profile 0 GOP Updated 
Profile 0 ROI disabled

 [host] 
 Channel Selected: 0,enable = 2
 [host] 
 Channel Selected: 0,0,0,0,0  

 [host] 
 Channel Selected: 1,0,0,0,0  
[root@root ~]#  [m3vpss ]  6555: SCLR: Roi Command Received !!!
 [m3video] ENCLINK_H264:HEAPID:0        USED:11720
 [m3vpss ]  6556: SCLR  : Channel Out put Roi change is ... DONE !!!
Profile 0 Smart Stream Updated 
Channel 0 Profile Param Update Success

Enable Channel: 1
 [host] 
Disable Channel: 1/etc/init.d/finish_ubifs.sh: line 13: ./autorun_ipnc.sh: not found
 [m3video]  6546: ENCODE: CH0: 
 [m3video] Codec Switch: Complete [0] 
 [m3video]  Channel:0 inputframerate:60 targetfps:30
 [m3video] ******** Roi priority : [0] **********
 [m3video] ******** Roi priority : [0] **********
 [m3video] ******** Roi priority : [536870969] **********
 [m3video]  6560: ENCODE: CH1: 
 [m3video] Queueing codec switch reqObj into IVA [0]
 [m3video]  ENCLINK: new targetframerate to set:30000 
 [m3video]  ENCLINK: new intraFrameInterval to set:30,new maxPicSizeRatioI to set = 960 
 [m3video]  ===> ENCLINK: new ROI Param to set priority:0 
 [m3video]  ===> ENCLINK: new ROI Param to set priority:0 
 [m3video]  ENCLINK: new rate control algorithm  to set:0 

 [host] 
Enable Channel: 1Profile 1 Updated 
Profile 1 fps Updated 
Profile 1 codec Updated 
Profile 1 fps Updated 
Profile 1 fps Updated 

 [host] 
 Channel Selected: 1,rate control = 0Profile 1 bitrate type Updated 

 [host] 
 Channel Selected: 52 [m3video] ENCLINK:H264Enc !!WARNING!!!Allocated MV data size (31680) is less than calculated by codec (85836)
Profile 1 image quality Updated 

 [host] 
 Channel Selected: 1Profile 1 GOP Updated 
Channel 1 Profile Param Update Success

 [host] 
 Channel Selected: 0Profile 2 image quality Updated 

<PROFILE_MANAGER>OSD logo Enable!!! 

SetOsdParams called with L:0 D:1 T:1 

Update Privacy Mask Block:0

Update Privacy Mask enable:0

Update Privacy Mask Block:1

Update Privacy Mask enable:0

Update Privacy Mask Block:2

Update Privacy Mask enable:0

<PROFILE_MANAGER>OSD_update Logo 
<PROFILE_MANAGER>Logo File logo.jpeg not found!!!
<PROFILE_MANAGER>Selecting Default Logo File defaultlogo.jpeg!!!
Message to Safe System Queue Open Success!!!
Message From Safe System Queue Open Success!!!
SAFE_SYSTEM : Waiting for reply!!!!
 [m3vpss ] ##########################################################
 [m3video] ENCLINK_H264:HEAPID:0        USED:11720
 [m3vpss ] <swosdLink_task.c> date format:2
 [m3vpss ] <swosdLink_task.c> time format:0
 [m3video]  6645: ENCODE: CH1: 
 [m3video] Codec Switch: Complete [0] 
 [m3vpss ] <swosdLink_task.c> datetime enable:1
 [m3vpss ] <swosdLink_task.c> datetime Pos:3
 [m3video]  Channel:1 inputframerate:30 targetfps:30
 [m3vpss ] <swosdLink_task.c> Logo enable:0
 [m3vpss ] <swosdLink_task.c> Logo Pos :0
 [m3vpss ] <swosdLink_task.c> text enable:1
 [m3vpss ] <swosdLink_task.c> text Pos:3
 [m3vpss ] <swosdLink_task.c> text string:root
 [m3vpss ] <swosdLink_task.c>  Stream ID Count:3
 [m3vpss ] ##########################################################
 [m3vpss ] <swosdLink_task.c>  Stream ID:0
 [m3vpss ] <swosdLink_task.c>  Stream ID:1
 [m3vpss ] <swosdLink_task.c>  Stream ID:2
 [m3video]  ENCLINK: new targetbitrate to set:2048000 
 [m3video]  ENCLINK: new targetframerate to set:30000 
 [m3video]  ENCLINK: new intraFrameInterval to set:30,new maxPicSizeRatioI to set = 960 
 [m3video]  ENCLINK: new rate control algorithm  to set:0 
Waiting Reply for command :ffmpeg -i /opt/ipnc/Image/defaultlogo.jpeg -s 80x32 -pix_fmt yuv420p /opt/ipnc/Image/logo_1_p.yuv -y > /dev/null 2>&1
<SetLogoYUVPtoSP>Input File:/opt/ipnc/Image/logo_1_p.yuv
<SetLogoYUVPtoSP>Output File:/opt/ipnc/Image/logo_1.yuv
<SetLogoYUVPtoSP>remove File:/opt/ipnc/Image/logo_1_p.yuv
<SetLogoYUVPtoSP>Return :12c
Message to Safe System Queue Open Success!!!
Message From Safe System Queue Open Success!!!
SAFE_SYSTEM : Waiting for reply!!!!
Waiting Reply for command :ffmpeg -i /opt/ipnc/Image/defaultlogo.jpeg -s 160x64 -pix_fmt yuv420p /opt/ipnc/Image/logo_2_p.yuv -y > /dev/null 2>&1
<SetLogoYUVPtoSP>Input File:/opt/ipnc/Image/logo_2_p.yuv
<SetLogoYUVPtoSP>Output File:/opt/ipnc/Image/logo_2.yuv
<SetLogoYUVPtoSP>remove File:/opt/ipnc/Image/logo_2_p.yuv

<stream.c>Logo_1 File name:/opt/ipnc/Image/logo_1.yuv
LOGO Allocating Vsys_buffer of Size 1:3840
 [host] Vsys_allocBuf - addr = 0x40205000,size = 3840

Logo buffer allocated for size 3840

<stream.c>Logo_2 File name:/opt/ipnc/Image/logo_2.yuv
LOGO Allocating Vsys_buffer of Size 2:15360
 [host] Vsys_allocBuf - addr = 0x400dd000,size = 15360

Logo buffer allocated for size 15360

 [host] Vsys_freeBuf - addr = 0x400dd000

 [host] Vsys_freeBuf - addr = 0x40205000

Logo Default File Intialization Done
<SetLogoYUVPtoSP>Return :12c
<UpdateOsdSetting>:Return SetOsdNewLogo:12c
Motion detection enable state : [0] 
Motion detection enable re detection time : [5] 
sens : [5] thrld :[5] 

 [host] 
 Set VENC_MDPARAM
Tamper config state:[0] sensitivity :[5] redetection : [5] 
TAMPER PARAM : enable [0] sensitivity :[5] re-detection time : [5]

 [host] 
 Set VENC_TAMPERPARAM
Profile Manager Init Success
 [m3video] Final Data Received state : [0] sensitivity : [5] 

Message to Safe System Queue Open Success!!!
SAFE_SYSTEM : Waiting for reply!!!!
Message From Safe System Queue Open Success!!!
Waiting Reply for command :mkdir -p /tmp/lighttpd
Message to Safe System Queue Open Success!!!
Message From Safe System Queue Open Success!!!
SAFE_SYSTEM : Waiting for reply!!!!
Waiting Reply for command :mkdir -p /opt/ipnc/install/WEB_SERVER : Updating Lighttpd Configuration
WEB_SERVER : Starting Lighttpd

Message to Safe System Queue Open Success!!!
Message From Safe System Queue Open Success!!!
SAFE_SYSTEM : Waiting for reply!!!!
Waiting Reply for command :/usr/sbin/lighttpd -D -f /tmp/lighttpd/lighttpd.conf &WEB_SERVER : Lighttpd Started.

Message to Safe System Queue Open Success!!!
Message From Safe System Queue Open Success!!!
SAFE_SYSTEM : Waiting for reply!!!!
Waiting Reply for command :/opt/ipnc/RTSP_streamer &RTSP Server Interface Init Success 
Event Manager Init Success
 [m3vpss ] CT: 5408, 3dlut index:2 
MSG_CMD_GET_PHY_MEM case 
AVServer Interface Init Success IN RTSP
Init-SysInterface Success IN RTSP
Receive Handle-SysServerData Success IN RTSP
Stream0 CODEC GET FROM HANDLE_SYS_SER : 0
Stream0 AUDIO GET FROM HANDLE_SYS_SER : 0
Stream1 CODEC GET FROM HANDLE_SYS_SER : 0
Stream1 AUDIO GET FROM HANDLE_SYS_SER : 0
Stream2 CODEC GET FROM HANDLE_SYS_SER : 1
Stream2 AUDIO GET FROM HANDLE_SYS_SER : 0
SERVER PORT NUMBER GET FROM HANDLE_SYS_SER : 554
Init RTSP Handler.. ..
Initializing Streaming Server.. ..
 
CURRENT CHANNEL ID INFO :: STREAM_MAIN
CURRENT CODEC INFO ::0
CURRENT CHANNEL ID INFO :: STREAM_SUB
CURRENT CODEC INFO ::0
CURRENT CHANNEL ID INFO :: STREAM_SNAPSHOT 
CURRENT CODEC INFO ::1
Success Receive Handle-SysServerData before RTSP Start
Creating Media Sessions and Add it to RTSP server
STREAM_MAIN Media sessions Added Successfully
STREAM_SUB Media sessions Added Successfully
STREAM_SNAPSHOT Media sessions Added Successfully
IN H264UniCastMediaSubsession 
In H264UniCastMediaSubsession Class

**************************************************
# Stream Name : Stream0
# URL         : rtsp://10.99.8.18/Stream0
**************************************************

IN H264UniCastMediaSubsession 
In H264UniCastMediaSubsession Class

**************************************************
# Stream Name : Stream1
# URL         : rtsp://10.99.8.18/Stream1
**************************************************

IN JPEGUniCastMediaSubsession 
In JPEGUniCastMediaSubsession Class

**************************************************
# Stream Name : Stream2
# URL         : rtsp://10.99.8.18/Stream2
**************************************************

2016-03-25 13:42:14: (log.c.164) server started 

[root@root ~]# 
[root@root ~]# hwclock -w
[  680.240000] omap_i2c omap_i2c.3: controller timed out
[  680.240000] rtc-ds1307 3-0068: write error -110
hwclock: RTC_SET_TIME: Connection timed out
[root@root ~]# 
[root@root ~]# 
[root@root ~]# 
[root@root ~]# devmem 0x48140A18
0x000E0040
[root@root ~]# devmem 0x48140A1C
0x000E0040
[root@root ~]# 
[root@root ~]#

vps_platformTI814x.c

/*******************************************************************************
 *                                                                             *
 * Copyright (c) 2009 Texas Instruments Incorporated - http://www.ti.com/      *
 *                        ALL RIGHTS RESERVED                                  *
 *                                                                             *
 ******************************************************************************/

/**
 *  \file vps_platformTI814x.c
 *
 *  \brief Implements the TI814x platform specific functions.
 *
 */

/* ========================================================================== */
/*                             Include Files                                  */
/* ========================================================================== */


#include <string.h>
#include <xdc/std.h>
#include <xdc/runtime/System.h>
#include <ti/sysbios/knl/Task.h>
#include <ti/sysbios/knl/Semaphore.h>
#include <ti/psp/vps/common/trace.h>
#include <ti/psp/vps/vps.h>
#include <ti/psp/vps/vps_displayCtrl.h>
#include <ti/psp/platforms/vps_platform.h>
#include <ti/psp/cslr/soc_TI814x.h>
#include <ti/psp/cslr/cslr_TI814xprcm.h>
#include <ti/psp/cslr/cslr_TI814xpll.h>
#include <ti/psp/vps/hal/vpshal_vip.h>
#include <ti/psp/vps/hal/vpshal_vps.h>
#include <ti/psp/devices/vps_videoDecoder.h>
#include <ti/psp/platforms/ti814x/vps_platformTI814x.h>


/* ========================================================================== */
/*                           Macros & Typedefs                                */
/* ========================================================================== */
#ifndef PLATFORM_ZEBU

#define ENABLE_HDVPSS_CLK

/* Enable I2C control to configure ecn/dec */
#define ENABLE_I2C_CLK

/* Set the pin mux */
#define CONFIG_PIN_MUX

/* Set the interrupt mux */
#define CONFIG_INT_MUX

/* Set the PLLs */
#define CONFIG_PLL

#endif /* PLATFORM_ZEBU */

#define ENABLE_I2C_PROBE_ON_INIT

#define VPS_VS_BOARD_IO_EXP_I2C_ADDR    (0x21u)

#define VPS_VC_BOARD_A1_IO_EXP_I2C_ADDR (0x27u)
#define VPS_VC_BOARD_A2_IO_EXP_I2C_ADDR (0x21u)

#define VPS_CA_BOARD_A1_IO_EXP_I2C_ADDR (0x21u)

/* THS7353 filter I2C address present in VC daughter card */
#define VPS_VC_BOARD_THS7353_I2C_ADDR   (0x2Cu)

#define VPS_PLATFORM_EVM_I2C_INST_ID    (VPS_DEVICE_I2C_INST_ID_0)

/** \brief PLL Control Module Base Address*/
#define VPS_CONTROL_MODULE_PLL_CTRL_BASE_ADDR   (CSL_TI814x_PLL_BASE)

/** \brief Control Module Device Configuration Base Address */
#define VPS_CTRL_MODULE_DEV_CFG_BASE_ADDR       (CSL_TI814x_CTRL_MODULE_BASE + \
                                                    0x0600u)

/* Default Values for DDR PLL configuration to get clock for I2C and CEC */
#define VPS_DDR_INT_FREQ2               (0x8u)
#define VPS_DDR_FRACT_FREQ2             (0xD99999u)
#define VPS_DDR_MDIV2                   (0x1Eu)
#define VPS_DDR_SYCCLK10_DIV            (0x0u)

/* gpio base addresses  */
#define REG32                           *(volatile unsigned int*)

#define VPS_PRCM_CLKTRCTRL_NO_SLEEP     (0u)
#define VPS_PRCM_CLKTRCTRL_SW_SLEEP     (1u)
#define VPS_PRCM_CLKTRCTRL_SW_WKUP      (2u)
#define VPS_PRCM_CLKTRCTRL_HW_AUTO      (3u)

#define VPS_PRCM_MODULE_DISABLE         (0u)
#define VPS_PRCM_MODULE_ENABLE          (2u)

#define VPS_PRCM_MAX_REP_CNT            (100u)

/* ADPLLJ_CLKCRTL_Register Value Configurations
ADPLLJ_CLKCRTL_Register SPEC bug  bit 19,bit29 -- CLKLDOEN,CLKDCOEN */
#define ADPLLJ_CLKCRTL_HS2              (0x00000801u)
/*HS2 Mode,TINTZ =1  --used by all PLL's except HDMI */
#define ADPLLJ_CLKCRTL_HS1              (0x00001001u)
/* HS1 Mode,TINTZ =1  --used only for HDMI  */
#define ADPLLJ_CLKCRTL_CLKDCO           (0x200a0000u)
/* Enable CLKDCOEN,CLKLDOEN,CLKDCOPWDNZ -- used for HDMI,USB */
#define VPS_TI814X_KHz                  (1000u)
#define VPS_TI814X_MHz                  (VPS_TI814X_KHz * VPS_TI814X_KHz)
#define VPS_TI814X_EVM_OSC_FREQ         (20u * VPS_TI814X_MHz)

/* Defines specific to on-board peripherals */
#define VPS_PCF8575_P0_7_P0_MASK       (0x01u)
#define VPS_PCF8575_P0_7_P4_MASK       (0x10u)
#define VPS_PCF8575_P0_7_P5_MASK       (0x20u)
#define VPS_PCF8575_P0_7_P6_MASK       (0x40u)
#define VPS_PCF8575_P0_7_P7_MASK       (0x80u)

#define VPS_PCF8575_P10_17_P16_MASK    (0x40u)
#define VPS_PCF8575_P10_17_P17_MASK    (0x80u)


/*  VC A2
 *  PCF8575 - mappings
 *  P7 - THS73861_FILTER2
 *  P6 - THS73861_FILTER1
 *  P5 - THS73861_BYPASS
 *  P4 - THS73861_DISABLE
 *  P0 - TVP7002_RSTN
 */
#define VPS_VC_A2_PCF8575_TVP_RESETn_MASK       (VPS_PCF8575_P0_7_P0_MASK)
#define VPS_VC_A2_PCF8575_THS73861_DISABLE_MASK (VPS_PCF8575_P0_7_P4_MASK)
#define VPS_VC_A2_PCF8575_THS73861_BYPASS_MASK  (VPS_PCF8575_P0_7_P5_MASK)
#define VPS_VC_A2_PCF8575_THS73861_FILTER1_MASK (VPS_PCF8575_P0_7_P6_MASK)
#define VPS_VC_A2_PCF8575_THS73861_FILTER2_MASK (VPS_PCF8575_P0_7_P7_MASK)

/*  Catalog A1
 *  PCF8575 - mappings
 *  P17 - THS7368_S1
 *  P16 - THS7368_S0
 *  P7 - THS7368_FILTER2
 *  P6 - THS7368_FILTER1
 *  P5 - THS7368_BYPASS
 *  P4 - THS7368_DISABLE
 *  P0 - TVP7002_RSTN
 */
#define VPS_CA_A1_PCF8575_TVP_RESETn_MASK       (VPS_PCF8575_P0_7_P0_MASK)
#define VPS_CA_A1_PCF8575_THS7368_DISABLE_MASK  (VPS_PCF8575_P0_7_P4_MASK)
#define VPS_CA_A1_PCF8575_THS7368_BYPASS_MASK   (VPS_PCF8575_P0_7_P5_MASK)
#define VPS_CA_A1_PCF8575_THS7368_FILTER1_MASK  (VPS_PCF8575_P0_7_P6_MASK)
#define VPS_CA_A1_PCF8575_THS7368_FILTER2_MASK  (VPS_PCF8575_P0_7_P7_MASK)

#define VPS_CA_A1_PCF8575_SEL_TVP_S0_MASK       (VPS_PCF8575_P10_17_P16_MASK)
#define VPS_CA_A1_PCF8575_SEL_TVP_S1_MASK       (VPS_PCF8575_P10_17_P17_MASK)

/* ========================================================================== */
/*                         Structure Declarations                             */
/* ========================================================================== */


/* \brief structure to keep track of pll configurations for a video mode */
typedef struct
{
    UInt32                  __n;
    /**< Divider N for the PLL.*/
    UInt32                  __m;
    /**< Multiplier M for the PLL.*/
    UInt32                  __m2;
    /**< Divider M2 for the PLL.*/
    UInt32                  clkCtrlValue;
    /**< For comparison based on the clkOut used */
} Vps_VideoPllCtrl;

/* Structure to track the versions of boards */
typedef struct
{
    Vps_PlatformBoardRev    vcCard;
    UInt32                  vcIoExpAddr;
    Semaphore_Handle        ioExpLock;
    Vps_PlatformBoardRev    vsCard_notused;         /* Not used as of now */
    Vps_PlatformBoardRev    baseBoard_notused;      /* Not used as of now */
    Vps_PlatformBoardRev    caCard;
    UInt32                  caIoExpAddr;
}Vps_BoardVersion;

/* ========================================================================== */
/*                          Function Declarations                             */
/* ========================================================================== */
#ifdef CONFIG_PIN_MUX
static Int32 Vps_platformTI814xSetPinMux(void);
#endif

#ifdef CONFIG_INT_MUX
static Int32 Vps_platformTI814xSetIntMux(void);
#endif

#ifdef ENABLE_HDVPSS_CLK
static Int32 Vps_platformTI814xEnableHdVpssClk(void);
#endif

#ifdef ENABLE_I2C_CLK
static Int32 Vps_platformTI814xEnableI2c(void);
#endif

#if  defined(CONFIG_PLL) || defined(ENABLE_HDVPSS_CLK) || defined(ENABLE_I2C_CLK)
static void udelay(int delay_usec);
#endif

#if  defined(CONFIG_PLL) || defined(ENABLE_HDVPSS_CLK)
Int32 Vps_platformPllCfg(UInt32 baseAddr,
                  UInt32 N,
                  UInt32 M,
                  UInt32 M2,
                  UInt32 clkCtrlValue);
static Int32 Vps_platformTI814xConfigHdVpssPll(void);
static Int32 Vps_getDividers(Vps_VideoPllCtrl *config, UInt32 reqOutClk,
                            UInt32 vencClk);
#endif

static Int32 Vps_getVcCardVersion(Vps_BoardVersion *boardVer);
static Int32 Vps_platformTi814xEnableThs73681(FVID2_Standard standard,
                                              UInt32 i2cInst,
                                              UInt32 ioExpAddr);

/* ========================================================================== */
/*                            Global Variables                                */
/* ========================================================================== */

#if defined (ENABLE_HDVPSS_CLK) || defined (ENABLE_I2C_CLK)
static CSL_PrcmRegs gVpsPrcmRegs = (CSL_PrcmRegs) CSL_TI814x_PRCM_BASE;
#endif

#if defined (CONFIG_PLL) || defined (ENABLE_HDVPSS_CLK)
static CSL_PllCtrlRegs gVpsPllCtrlRegs =
            (CSL_PllCtrlRegs) VPS_CONTROL_MODULE_PLL_CTRL_BASE_ADDR;
#endif

/**< Variable to track the version of daughter card, we have Aplha 1 and
     Alpha 2, designated as REV A and REV B */
static Vps_BoardVersion gTi814xBoardVer = {VPS_PLATFORM_BOARD_REV_UNKNOWN,  \
                                           VPS_VC_BOARD_A1_IO_EXP_I2C_ADDR, \
                                           VPS_PLATFORM_BOARD_REV_UNKNOWN,  \
                                           VPS_PLATFORM_BOARD_REV_UNKNOWN};
/* ========================================================================== */
/*                          Function Definitions                              */
/* ========================================================================== */

Int32 Vps_platformTI814xInit(Vps_PlatformInitParams *initParams)
{
    Int32 status = FVID2_SOK;

#ifdef CONFIG_PIN_MUX
    if (TRUE == initParams->isPinMuxSettingReq)
    {
        Vps_platformTI814xSetPinMux();
    }
#endif

#ifdef CONFIG_INT_MUX
        Vps_platformTI814xSetIntMux();
#endif

#ifdef ENABLE_HDVPSS_CLK
    /* Initialize Pixel Clock */
    status |= Vps_platformTI814xConfigHdVpssPll();
    status |= Vps_platformTI814xEnableHdVpssClk();
#endif

#ifdef ENABLE_I2C_CLK
#ifndef PLATFORM_ZEBU
    status |= Vps_platformTI814xEnableI2c();
#endif
#endif

    return (status);
}

Int32 Vps_platformTI814xDeInit(void)
{
    Int32 status = FVID2_SOK;

    return (status);
}

/* Init EVM related sub-systems like I2C instance */
Int32 Vps_platformTI814xDeviceInit(Vps_PlatformDeviceInitParams *initPrms)
{
    Int32 status = FVID2_SOK;
#ifdef PLATFORM_EVM_SI
    UInt8 i2cCnt = 0;
    Semaphore_Params semParams;
    /* TI814x has 4 I2C instances. */
    UInt32 i2cRegs[VPS_DEVICE_I2C_INST_ID_MAX] = {CSL_TI814x_I2C0_BASE,
                                                  CSL_TI814x_I2C1_BASE,
                                                  CSL_TI814x_I2C2_BASE,
                                                  CSL_TI814x_I2C3_BASE};
    UInt32 i2cInt[VPS_DEVICE_I2C_INST_ID_MAX] = {CSL_INTC_EVENTID_I2CINT0,
                                                 CSL_INTC_EVENTID_I2CINT1,
                                                 CSL_INTC_EVENTID_I2CINT2,
                                                 CSL_INTC_EVENTID_I2CINT3};

    Vps_DeviceInitParams deviceInitPrm;

#ifdef PLATFORM_ZEBU
    return status;
#endif
    /*
     * External video device subsystem init
     */
    memset ( &deviceInitPrm, 0, sizeof ( deviceInitPrm ) );

    /* Initialize file locals */
    Semaphore_Params_init(&semParams);
    semParams.mode = Semaphore_Mode_BINARY;
    gTi814xBoardVer.ioExpLock = Semaphore_create(1u, &semParams, NULL);
    if (NULL == gTi814xBoardVer.ioExpLock)
    {
        status = FVID2_EALLOC;
        return (status);
    }
    Semaphore_pend(gTi814xBoardVer.ioExpLock, BIOS_WAIT_FOREVER);

    gTi814xBoardVer.vcCard              = VPS_PLATFORM_BOARD_REV_UNKNOWN;
    gTi814xBoardVer.vcIoExpAddr         = VPS_VC_BOARD_A1_IO_EXP_I2C_ADDR;
    gTi814xBoardVer.vsCard_notused      = VPS_PLATFORM_BOARD_REV_UNKNOWN;
    gTi814xBoardVer.baseBoard_notused   = VPS_PLATFORM_BOARD_REV_UNKNOWN;
    gTi814xBoardVer.caCard              = VPS_PLATFORM_BOARD_REV_UNKNOWN;
    gTi814xBoardVer.caIoExpAddr         = VPS_CA_BOARD_A1_IO_EXP_I2C_ADDR;


    Semaphore_post(gTi814xBoardVer.ioExpLock);

    /*
     * Initialize I2C instances
     */
    for (i2cCnt = 0; i2cCnt < VPS_DEVICE_I2C_INST_ID_MAX; i2cCnt++)
    {
        deviceInitPrm.i2cRegs[i2cCnt] = (Ptr)(i2cRegs[i2cCnt]);
        deviceInitPrm.i2cIntNum[i2cCnt] = i2cInt[i2cCnt];
        deviceInitPrm.i2cClkKHz[i2cCnt] = VPS_DEVICE_I2C_INST_NOT_USED;
    }
    deviceInitPrm.isI2cInitReq = initPrms->isI2cInitReq;

    /* TI814x uses only I2C[2], so modify the sampling frequency */
   deviceInitPrm.i2cRegs[VPS_PLATFORM_EVM_I2C_INST_ID]
       = (Ptr)CSL_TI814x_I2C0_BASE;
   deviceInitPrm.i2cIntNum[VPS_PLATFORM_EVM_I2C_INST_ID]
       = CSL_INTC_EVENTID_I2CINT0;
   deviceInitPrm.i2cClkKHz[VPS_PLATFORM_EVM_I2C_INST_ID]
       = 400;

    status = Vps_deviceInit ( &deviceInitPrm );
    
#ifdef ENABLE_I2C_PROBE_ON_INIT
    if (TRUE == initPrms->isI2cInitReq &&
        TRUE == initPrms->isI2cProbingReq)
    {
        Vps_deviceI2cProbeAll(Vps_platformGetI2cInstId());
    }
#endif
#endif

    if (status == FVID2_SOK)
    {
        /* Right now, VC daughter card has different versions,
           Base board versions - does not require any special operations
           VS - we do not have multiple versions */
        if(Vps_platformGetBoardId() == VPS_PLATFORM_BOARD_VC)
        {
            status = Vps_getVcCardVersion(&gTi814xBoardVer);
            /* Two versions of VC cards */
            GT_assert( GT_DEFAULT_MASK, (gTi814xBoardVer.vcCard == VPS_PLATFORM_BOARD_REV_B) ||
                    (gTi814xBoardVer.vcCard == VPS_PLATFORM_BOARD_REV_A));
        }
    }

    Vps_printf("%s: deviceInitPrm.i2cClkKHz[ISS_DEVICE_I2C_INST_ID_2] : %d\n", __func__, deviceInitPrm.i2cClkKHz[2]);
    Vps_printf ("###### ISS_DEVICE_I2C_INST_ID_2 : %d\n", 2);
    
    deviceInitPrm.i2cRegs[2] = (Ptr) CSL_TI814x_I2C2_BASE;
    deviceInitPrm.i2cIntNum[2] = 2;
    deviceInitPrm.i2cClkKHz[2]  = 100;
    
    Vps_printf("%s: deviceInitPrm.i2cClkKHz[ISS_DEVICE_I2C_INST_ID_2] : %d\n", __func__, deviceInitPrm.i2cClkKHz[2]);
    Vps_printf ("###### ISS_DEVICE_I2C_INST_ID_2 : %d\n", 2);

    
    return (status);
}

/* De-Init EVM related sub-systems */
Int32 Vps_platformTI814xDeviceDeInit(void)
{
#ifdef PLATFORM_ZEBU
    return 0;
#endif


#ifdef PLATFORM_EVM_SI
    /*
     * Extern video device de-init
     */
    Vps_deviceDeInit (  );

#endif

    return (FVID2_SOK);
}

UInt32 Vps_platformTI814xGetI2cInstId(void)
{
    return (VPS_PLATFORM_EVM_I2C_INST_ID);
}

UInt8 Vps_platformTI814xGetVidDecI2cAddr(UInt32 vidDecId, UInt32 vipInstId)
{
    UInt8 devAddr = 0x00u;
    UInt8 devAddrTvp5158[VPS_CAPT_INST_MAX] = { 0x58, 0x5c, 0x5a, 0x5e };

    //TODO
    UInt8 devAddrSii9135[VPS_CAPT_INST_MAX] = { 0x00, 0x00, 0x30, 0x00 };
    UInt8 devAddrTvp7002[VPS_CAPT_INST_MAX] = { 0x5d, 0x00, 0x00, 0x00 };

    GT_assert( GT_DEFAULT_MASK, vipInstId<VPS_CAPT_INST_MAX);

    switch (vidDecId)
    {
        case FVID2_VPS_VID_DEC_TVP5158_DRV:

            devAddr = devAddrTvp5158[vipInstId];
            break;

        case FVID2_VPS_VID_DEC_SII9135_DRV:
            devAddr = devAddrSii9135[vipInstId];
            break;

        case FVID2_VPS_VID_DEC_TVP7002_DRV:
            devAddr = devAddrTvp7002[vipInstId];
            break;

        default:
            GT_0trace(GT_DEFAULT_MASK, GT_ERR, "Invalid decoder ID\n");
            break;
    }

    return (devAddr);
}

UInt8 Vps_platformTI814xGetVidEncI2cAddr(UInt32 vidEncId)
{
    UInt8 devAddr = 0x00u;
    Vps_PlatformBoardId boardId;
    /* There can be two Sii9022 instances, one on VS and other on VC board.
     * devAddrSii9022[0] -> VS Sii9022
     * devAddrSii9022[1] -> VC Sii9022
     */
    UInt8 devAddrSii9022[2u] = { 0x39, 0x39 };

    if (vidEncId == FVID2_VPS_VID_ENC_SII9022A_DRV)
    {
        boardId = Vps_platformGetBoardId();
        switch (boardId)
        {
            case VPS_PLATFORM_BOARD_VS:
                devAddr = devAddrSii9022[0];
                break;

            case VPS_PLATFORM_BOARD_VC:
                devAddr = devAddrSii9022[1];
                break;

            default:
                GT_0trace(GT_DEFAULT_MASK, GT_ERR, "Invalid Board ID\n");
                break;
        }
    }

    return (devAddr);
}

Int32 Vps_platformTI814xSimVideoInputSelect(UInt32 vipInstId,
                                            UInt32 fileId,
                                            UInt32 pixelClk)
{
    volatile UInt32 *pRegs[2];
    UInt32 instId, portId;

    pRegs[0] = (UInt32 *)(CSL_TI814x_VPS_BASE+0xE100);
    pRegs[1] = (UInt32 *)(CSL_TI814x_VPS_BASE+0xE200);

    instId = vipInstId/VPSHAL_VIP_INST_MAX;
    portId = vipInstId%VPSHAL_VIP_INST_MAX;

    /*
     * VIP reset is done so that switch from single channel to
     * multi-channel case is proper in simulator
     */
    if (0 == instId)
    {
        VpsHal_vpsClkcModuleReset(VPSHAL_VPS_CLKC_VIP0, TRUE);
        VpsHal_vpsClkcModuleReset(VPSHAL_VPS_CLKC_VIP0, FALSE);
    }
    else
    {
        VpsHal_vpsClkcModuleReset(VPSHAL_VPS_CLKC_VIP1, TRUE);
        VpsHal_vpsClkcModuleReset(VPSHAL_VPS_CLKC_VIP1, FALSE);
    }

    pRegs[instId][0+portId] = fileId;
    pRegs[instId][2+portId] = pixelClk;

    return (FVID2_SOK);
}

#if defined(CONFIG_PLL) || defined(ENABLE_HDVPSS_CLK)
static Int32 Vps_platformTI814xConfigHdVpssPll(void)
{
    UInt32 baseAddr;
    baseAddr = (UInt32)&gVpsPllCtrlRegs->DSSPLL_PWRCTRL;

    /* set for 220Mhz HDVPSS Clock, 220MHz is max clock for HDVPSS */
    Vps_platformPllCfg(baseAddr, 19, 880, 4, ADPLLJ_CLKCRTL_HS2);

    return (FVID2_SOK);
}
#endif

Int32 Vps_platformTI814xSetVencPixClk(Vps_SystemVPllClk *vpllCfg)
{
#ifdef ENABLE_HDVPSS_CLK
    Vps_VideoPllCtrl pllDividers;
    Int32 rtnValue = FVID2_SOK;
    Vps_VPllOutputClk  pllOutputClk;
    GT_assert( GT_DEFAULT_MASK, NULL != gVpsPllCtrlRegs);
    GT_assert( GT_DEFAULT_MASK, NULL != gVpsPrcmRegs);
    GT_assert( GT_DEFAULT_MASK, NULL != vpllCfg);

    if (VPS_SYSTEM_VPLL_OUTPUT_VENC_RF == vpllCfg->outputVenc)
    {
        GT_assert( GT_DEFAULT_MASK, 54000u  == vpllCfg->outputClk);
    }
    else if ((VPS_SYSTEM_VPLL_OUTPUT_VENC_A == vpllCfg->outputVenc) ||
            (VPS_SYSTEM_VPLL_OUTPUT_VENC_D == vpllCfg->outputVenc))
    {
        GT_assert( GT_DEFAULT_MASK, 54000u != vpllCfg->outputClk);
    }

    if (rtnValue == FVID2_SOK)
    {
        rtnValue = Vps_getDividers(&pllDividers, vpllCfg->outputClk, vpllCfg->outputVenc);

        if (rtnValue == FVID2_SOK)
        {
            /*HDMI shares the same PLL as VENC_A*/
            if (vpllCfg->outputVenc == VPS_SYSTEM_VPLL_OUTPUT_HDMI)
                pllOutputClk = VPS_SYSTEM_VPLL_OUTPUT_VENC_A;
            else
                pllOutputClk = (Vps_VPllOutputClk)vpllCfg->outputVenc;

                rtnValue = Vps_platformPllCfg((UInt32)
                &gVpsPllCtrlRegs->VideoPll_Factors[pllOutputClk].PWRCTRL,
                pllDividers.__n,
                pllDividers.__m,
                pllDividers.__m2,
                pllDividers.clkCtrlValue);
        }
    }
    return (rtnValue);
#else
    return (FVID2_SOK);
#endif /* ENABLE_HDVPSS_CLK */
}

#if  defined(CONFIG_PLL) || defined(ENABLE_HDVPSS_CLK)
/*******************************************************************************
****
****                                   ********* RANGE ************
****   REF_CLK       = (OSC_FREQ)/N+1  [  REF_CLK < 2.5MHz      ]
****   DCOCLK_HS2    = (REF_CLK)*M     [500  < DCOCLK < 1000MHz ]
****   DCOCLK_HS1    = (REF_CLK)*M     [1000 < DCOCLK < 2000MHz ]--used for HDMI CLKDCO
****   CLKOUT        =  DCOCLK/M2      [10   < CLKOUT < 2000MHz ]--used for DVO2, SD
****   N+1                             [1..256]
****   M                               [2..4095]
****   M2                              [1..127]
****
****
*******************************************************************************/
/* Get the divider value for video PLL for the specified frequency.
   N requires to start with 19 - TODO check with 0x0 */
static Int32 Vps_getDividers(Vps_VideoPllCtrl *config, UInt32 reqOutClk,
                            UInt32 vencClk)
{
    Int32   rtnValue = FVID2_EFAIL;
    Int32   n, m, m2;
    float   refClk, dcoClk, clkOut;
    UInt8   hsMode = 1; /* 1: HS2, 2:HS1*/
    UInt8   factor = 1;
    UInt32   padding;
    /* The input clock is specified in terms of KiloHertz, require MHz to work
       with */
    if (vencClk == VPS_SYSTEM_VPLL_OUTPUT_HDMI)
    {
        padding = reqOutClk % 500;
        if (padding)
        {
            if (padding >= 250)
                reqOutClk += 500 - padding;
            else
                reqOutClk -=padding;
        }
        /*if Freq is less than 50MHz, post-M2 clock is used to drive
        HDMI, therefore factor should b1. the other case factor is 10 since
        pre-M2 clock is to driver the HDMI
        check HDMI wrapper spec and TI814X Clock Arch document to
        further understand this*/
        if (reqOutClk >= 50000)
                factor = 10;
        /*CLK must be 10x if it is for HDMI*/
        reqOutClk *= 1000u * 10;
    }
    else
    {
        factor = 1;
        reqOutClk *= 1000u;
    }
    if (reqOutClk > 1000 * VPS_TI814X_MHz)
        /*must use HS1 mode*/
        hsMode = 2;

    for (n = 19; ((n < 256u) && (rtnValue != FVID2_SOK)); n++)
    {
        refClk = VPS_TI814X_EVM_OSC_FREQ / (n + 1);
        if ( refClk < (2.5 * VPS_TI814X_MHz))
        {
            for (m = 2; ((m < 4095) && (rtnValue != FVID2_SOK)); m++)
            {
                dcoClk = (refClk) * m;
                if ((dcoClk > (500 * VPS_TI814X_MHz * hsMode)) &&
                    (dcoClk < (1000 * VPS_TI814X_MHz * hsMode)))
                {
                    for (m2 = 1; m2 <= 127; m2++)
                    {
                        clkOut = dcoClk / m2;
                        if (clkOut  == reqOutClk)
                        {
                            config->__n     = n;
                            config->__m     = m;
                            config->__m2    = m2 * factor;
                            if (hsMode == 1)
                                config->clkCtrlValue = ADPLLJ_CLKCRTL_HS2;
                            else
                                config->clkCtrlValue = ADPLLJ_CLKCRTL_HS1;
                            /*enable the CLKDCOLDO and CLKOUTLDO for HDMI*/
                            if (vencClk == VPS_SYSTEM_VPLL_OUTPUT_HDMI)
                                config->clkCtrlValue |= ADPLLJ_CLKCRTL_CLKDCO;
                            rtnValue = FVID2_SOK;
                            break;
                        }
                    }
                }
            }
            /* Work around for the hardware bug where it failed to set
               54k frequency with generated with the values generated by
               getdivider function - Essentially m = 540 and M2 == 10 will not
               work */
            if(reqOutClk == (54000u * 1000u))
            {
                config->__n     = 19;
                config->__m     = 1080;
                config->__m2    = 20;
                break;
            }
        }
    }
    return (rtnValue);
}
#endif

/*
    Setup pinmux in for capture/display

    Pinmux setup is as shown below,

    VIP0
    - YCC 16-bit        - Always ENABLED
    - YCC 24-bit        - ENABLED
    - CLK0              - Always ENABLED
    - CLK1              - Always ENABLED
    - HD/VD/DE/FLD0     - ENABLED
    - HD/VD/DE/FLD1     - DISABLED

    VIP1
    - YCC 16-bit        - ENABLED
    - CLK0              - ENABLED
    - CLK1              - ENABLED
    - HD/VD/DE/FLD0     - DISABLED
    - HD/VD/DE/FLD1     - DISABLED

    VOUT0 (DVO2)
    - CLK               - Always ENABLED
    - HD/VD/DE/FLD      - ENABLED
    - YCC 16-bit        - Always ENABLED
    - YCC 20-bit        - ENABLED
    - RGB/YCC 24-bit    - ENABLED
    - RGB/YCC 30-bit    - ENABLED

    VOUT1 (DVO1)
    - CLK               - DISABLED
    - HD/VD/DE/FLD      - DISABLED
    - YCC 16-bit        - DISABLED
    - YCC 20-bit        - DISABLED
    - RGB/YCC 24-bit    - DISABLED
    - RGB/YCC 30-bit    - DISABLED

    I2C2
    - SDA               - ENABLED
    - SCL               - ENABLED

    HDMI I2C0
    - SDA               - ENABLED
    - SCL               - ENABLED
*/
#ifdef CONFIG_PIN_MUX
static Int32 Vps_platformTI814xSetPinMux(void)
{
    /* Vout 0 configuration DVO2 Function 1*/
    /* TODO There are two pins for the fid. Need to see whichone is used */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0AB8) = 0x1;   /* vout0_fid_mux1 */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0ABC) = 0x1;   /* vout0_clk */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0AC0) = 0x1;   /* vout0_hsync */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0AC4) = 0x1;   /* vout0_vsync */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0AC8) = 0x1;   /* vout0_avid */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0ACC) = 0x1;   /* vout0_b_cb_c[2] */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0AD0) = 0x1;   /* vout0_b_cb_c[3] */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0AD4) = 0x1;   /* vout0_b_cb_c[4] */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0AD8) = 0x1;   /* vout0_b_cb_c[5] */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0ADC) = 0x1;   /* vout0_b_cb_c[6] */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0AE0) = 0x1;   /* vout0_b_cb_c[7] */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0AE4) = 0x1;   /* vout0_b_cb_c[8] */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0AE8) = 0x1;   /* vout0_b_cb_c[9] */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0AEC) = 0x1;   /* vout0_g_y_yc[2] */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0AF0) = 0x1;   /* vout0_g_y_yc[3] */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0AF4) = 0x1;   /* vout0_g_y_yc[4] */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0AF8) = 0x1;   /* vout0_g_y_yc[5] */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0AFC) = 0x1;   /* vout0_g_y_yc[6] */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0B00) = 0x1;   /* vout0_g_y_yc[7] */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0B04) = 0x1;   /* vout0_g_y_yc[8] */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0B08) = 0x1;   /* vout0_g_y_yc[9] */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0B0C) = 0x1;   /* vout0_r_cr[2] */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0B10) = 0x1;   /* vout0_r_cr[3] */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0B14) = 0x1;   /* vout0_r_cr[4] */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0B18) = 0x1;   /* vout0_r_cr[5] */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0B1C) = 0x1;   /* vout0_r_cr[6] */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0B20) = 0x1;   /* vout0_r_cr[7] */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0B24) = 0x1;   /* vout0_r_cr[8] */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0B28) = 0x1;   /* vout0_r_cr[9] */

#if 0
    /* HDMI I2C_scl and I2C_sda Function 2*/
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0934) = 0x60002;   /* hdmi_ddc_scl_mux0 */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0938) = 0x60002;   /* hdmi_ddc_sda_mux0 */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x09BC) = 0x40010;  /*hdmi_hpd_mux0 pinmmr112[4]*/
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x09B8) = 0x60010;  /*hdmi_cec_mux0 pinmmr111[4] */
    /* TODO HDMI CEC and HPD to be added in pinmux */
    /* Currently its shared with GPMC. */
#endif

    /* VIN0 TODO Do we need to enable RXACTIVE Bit in pinmux for input pins? */
    /* Vin0 hsync1 and vin0 vsync1 */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A14) = 0x50001;   /* vin0_clk1 */
//     REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A18) = 0x0;       /* vin0_de0_mux0 - DeSelect input */
//     REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A1C) = 0x50001;   /* vin0_fld0_mux0 */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A20) = 0x50001;   /* vin0_clk0 */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A24) = 0x50001;   /* vin0_hsync0 */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A28) = 0x50001;   /* vin0_vsync0 */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A2C) = 0x50001;   /* vin0_d0 */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A30) = 0x50001;   /* vin0_d1 */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A34) = 0x50001;   /* vin0_d2 */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A38) = 0x50001;   /* vin0_d3 */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A3c) = 0x50001;   /* vin0_d4 */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A40) = 0x50001;   /* vin0_d5 */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A44) = 0x50001;   /* vin0_d6 */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A48) = 0x50001;   /* vin0_d7 */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A4c) = 0x50001;   /* vin0_d8 */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A50) = 0x50001;   /* vin0_d9 */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A54) = 0x50001;   /* vin0_d10 */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A58) = 0x50001;   /* vin0_d11 */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A5C) = 0x50001;   /* vin0_d12 */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A60) = 0x50001;   /* vin0_d13 */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A64) = 0x50001;   /* vin0_d14 */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A68) = 0x50001;   /* vin0_d15 */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A6C) = 0x50001;   /* vin0_d16 */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A70) = 0x50001;   /* vin0_d17 */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A74) = 0x50001;   /* vin0_d18 */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A78) = 0x50001;   /* vin0_d19 */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A7C) = 0x50001;   /* vin0_d20 */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A80) = 0x50001;   /* vin0_d21 */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A84) = 0x50001;   /* vin0_d22 */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A88) = 0x50001;   /* vin0_d23 */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A8C) = 0x50001;   /* vin0_de0_mux1 */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A90) = 0x50001;  /* vin0_de1 */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A94) = 0x50001;   /* vin0_fld0_mux1 */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A98) = 0x50001;   /* vin0_fld1 */


    /* VIN1 Configuration Function 3*/
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0B2C) = 0x50004;   /* vin1_hsync0 */
    /* this is function 2 */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x09F0) = 0x50002;   /* vin1_clk1 */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0B30) = 0x50004;   /* vin1_vsync0 */
#ifdef ORIGIAL_PORT
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0B34) = 0x50004;   /* vin1_fid0 */
#endif /* ORIGIAL_PORT */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0B34) = 0x50008;   /* vin1_de0 */

    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0B38) = 0x50004;   /* vin1_clk0 */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0B3C) = 0x50004;   /* vin1a_d[0] */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0B40) = 0x50004;   /* vin1a_d[1] */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0B44) = 0x50004;   /* vin1a_d[2] */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0B48) = 0x50004;   /* vin1a_d[3] */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0B4C) = 0x50004;   /* vin1a_d[4] */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0B50) = 0x50004;   /* vin1a_d[5] */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0B54) = 0x50004;   /* vin1a_d[6] */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0B58) = 0x50004;   /* vin1a_d[8] */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0B5C) = 0x50004;   /* vin1a_d[9] */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0B60) = 0x50004;   /* vin1a_d[10] */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0B64) = 0x50004;   /* vin1a_d[11] */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0B68) = 0x50004;   /* vin1a_d[12] */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0B6C) = 0x50004;   /* vin1a_d[13] */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0B70) = 0x50004;   /* vin1a_d[14] */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0B74) = 0x50004;   /* vin1a_d[15] */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0B78) = 0x50004;   /* vin1a_d[16] */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0B7C) = 0x50004;   /* vin1a_d[17] */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0B80) = 0x50004;   /* vin1a_d[18] */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0B84) = 0x50004;   /* vin1a_d[19] */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0B88) = 0x50004;   /* vin1a_d[20] */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0B8C) = 0x50004;   /* vin1a_d[21] */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0B90) = 0x50004;   /* vin1a_d[22] */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0B94) = 0x50004;   /* vin1a_d[23] */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0B98) = 0x50004;   /* vin1a_d[7] */

#ifdef ORIGIAL_PORT
    /* Function 2 */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0BA8) = 0x50002;   /* vin1a_d[0] */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0BAC) = 0x50002;   /* vin1a_d[1] */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0BB0) = 0x50002;   /* vin1a_d[2] */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0BB4) = 0x50002;   /* vin1a_d[3] */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0BB8) = 0x50002;   /* vin1a_d[4] */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0BBC) = 0x50002;   /* vin1a_d[5] */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0BC0) = 0x50002;   /* vin1a_d[6] */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0BC4) = 0x50002;   /* vin1a_d[7] */
#endif /* ORIGIAL_PORT */

#if 0
    /* I2c2  configuration Function 6*/
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0924) = 0x60020;   /* i2c2_scl_mux0 */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0928) = 0x60020;   /* i2c2_sda_mux0 */
#endif

    /* TODO Find proper place for this Set the divider for the SYSCLK10 */
    *(UInt32 *)0x48180324 = 3;


#if 0 /* Idea was to make VIP 1 vSync hSync and clkc as input and watch GPIO */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0B2C) = 0x50080;   /* vin1_hsync0 */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x09F0) = 0x50080;   /* vin1_clk1 */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0B30) = 0x50080;   /* vin1_vsync0 */
#endif

    return (FVID2_SOK);
}
#endif

#ifdef CONFIG_INT_MUX
static Int32 Vps_platformTI814xSetIntMux(void)
{
    volatile unsigned int int_mux;

    /* I2C2 interrupt is routed through I2C1 interrupt through the
     * crossbar. For this, INT_MUX_[#int_number] register in the
     * Chip Control Module needs to be programmed.
     * INT_MUX_[#int_number] registers start from 0xF54
     * offset and one register is used to program 4 interrupt
     * muxes (6 bits for each mux, 2 bits reserved).
     * After reset INT_MUX_[#int_number] defaults to 000000, which
     * maps the interrupt from default mapping to interrupt_[#int_number].
     *
     * I2C_INT1 is mapped to interrupt line 19 and
     * INTMUX 16 to 19 --> 0x0f64. So read it first,
     * modify the respective bit field and write is back.
     */
    int_mux = REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0f64);
    /* I2CINT2 value = 4, INT_MUX_19_SHIFT = 24*/
    int_mux |= (4 << 24);
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0f64) = int_mux;

    return (FVID2_SOK);
}
#endif

Int32 Vps_platformTI814xResetVideoDevices(void)
{
    UInt32 i2cInst = Vps_platformTI814xGetI2cInstId();
    UInt32 ioExpI2cAddr = 0xFF;
    UInt8 regValue[2];
    Int32 status;
    Vps_PlatformBoardId boardId;

    boardId = Vps_platformGetBoardId();
    switch (boardId)
    {
        case VPS_PLATFORM_BOARD_VC:
            ioExpI2cAddr = gTi814xBoardVer.vcIoExpAddr;
            break;

        case VPS_PLATFORM_BOARD_VS:
            ioExpI2cAddr = VPS_VS_BOARD_IO_EXP_I2C_ADDR;
            break;

        case VPS_PLATFORM_BOARD_CATALOG:
            ioExpI2cAddr = gTi814xBoardVer.caIoExpAddr;
            break;
        default:
            break;
    }

    regValue[0] = 0x00;
    regValue[1] = 0x00;
    /* 2 versions of VC card - IO expander and filters are different between
       them */
    if ((boardId == VPS_PLATFORM_BOARD_VC) &&
        (gTi814xBoardVer.vcCard == VPS_PLATFORM_BOARD_REV_B))
    {
        status = Vps_deviceRawRead8(i2cInst, ioExpI2cAddr, regValue, 2u);
        GT_assert( GT_DEFAULT_MASK, status==FVID2_SOK);
        /* Reset TVP and disable THS73681 filter */
        regValue[0] &= (UInt8)~(VPS_VC_A2_PCF8575_TVP_RESETn_MASK);
        regValue[0] |= (UInt8)(VPS_VC_A2_PCF8575_THS73861_DISABLE_MASK);
    }

    /* Catalog Card */
    if (boardId == VPS_PLATFORM_BOARD_CATALOG)
    {
        status = Vps_deviceRawRead8(i2cInst, ioExpI2cAddr, regValue, 2u);
        GT_assert( GT_DEFAULT_MASK, status==FVID2_SOK);
        /* Reset TVP and disable THS7368 filter */
        regValue[0] &= (UInt8)~(VPS_CA_A1_PCF8575_TVP_RESETn_MASK);
        regValue[0] |= (UInt8)(VPS_CA_A1_PCF8575_THS7368_DISABLE_MASK);
    }

    status = Vps_deviceRawWrite8(i2cInst, ioExpI2cAddr, regValue, 2u);
    GT_assert( GT_DEFAULT_MASK, status==FVID2_SOK);

    Task_sleep(1000);

    if (boardId == VPS_PLATFORM_BOARD_VS)
    {
        regValue[0] = 0xFF;
        regValue[1] = 0xFE;
    }
    else
    {
        if (boardId == VPS_PLATFORM_BOARD_VC)
        {
            if (gTi814xBoardVer.vcCard == VPS_PLATFORM_BOARD_REV_A)
            {
                regValue[0] = 0xEF;
                regValue[1] = 0xFE;
            }
            else
            {
                /* Bring TVP outof reset and enable THS73681 filter */
                regValue[0] |= (UInt8)(VPS_VC_A2_PCF8575_TVP_RESETn_MASK);
                regValue[0] &= (UInt8)~(VPS_VC_A2_PCF8575_THS73861_DISABLE_MASK);
            }
        }

        if (boardId == VPS_PLATFORM_BOARD_CATALOG)
        {
                /* Bring TVP outof reset and enable THS73681 filter */
                regValue[0] |= (UInt8)(VPS_CA_A1_PCF8575_TVP_RESETn_MASK);
                regValue[0] &= (UInt8)~(VPS_CA_A1_PCF8575_THS7368_DISABLE_MASK);
        }

    }
    status = Vps_deviceRawWrite8(i2cInst, ioExpI2cAddr, regValue, 2);
    GT_assert( GT_DEFAULT_MASK, status==FVID2_SOK);

    return (status);
}

Vps_PlatformCpuRev Vps_platformTI814xGetCpuRev(void)
{
#ifdef PLATFORM_ZEBU
    return (VPS_PLATFORM_CPU_REV_2_1);
#else
    UInt32                  cpuId, cpuRev;
    Vps_PlatformCpuRev      cpuRevEnum;

    /* Read CPU ID */
    cpuId = REG32(VPS_CTRL_MODULE_DEV_CFG_BASE_ADDR + 0x0000u);

    cpuRev = ((cpuId >> 28u) & 0x0Fu);
    switch (cpuRev)
    {
        case 0x0u:
            cpuRevEnum = VPS_PLATFORM_CPU_REV_1_0;
            break;

        case 0xCu:  /* Certain intial sample of PG 2.1 has C but the production
                       samples should read out 3 */
        case 0x3u:
            cpuRevEnum = VPS_PLATFORM_CPU_REV_2_1;
            break;

       default:
            /* Default to last known version */
            Vps_printf("PLATFORM: UNKNOWN CPU detected, defaulting to VPS_PLATFORM_CPU_REV_2_1\n");
            cpuRevEnum = VPS_PLATFORM_CPU_REV_2_1;
            break;
    }

    return (cpuRevEnum);
#endif /* PLATFORM_ZEBU */
}

Vps_PlatformBoardRev Vps_platformTI814xGetBaseBoardRev(void)
{
    /* Only one revision of board till date */
    return (VPS_PLATFORM_BOARD_REV_A);
}

Vps_PlatformBoardRev Vps_platformTI814xGetDcBoardRev(void)
{
    /* Only one revision of board till date */
    return (VPS_PLATFORM_BOARD_REV_A);
}

Int32 Vps_platformTI814xEnableTvp7002Filter(FVID2_Standard standard)
{
    Int32       status = FVID2_SOK;
    UInt32      i2cInstId, i2cDevAddr;
    Vps_PlatformBoardId boardId;

    boardId = Vps_platformGetBoardId();
    i2cInstId = Vps_platformTI814xGetI2cInstId();

    if (boardId == VPS_PLATFORM_BOARD_VC)
    {
        if (gTi814xBoardVer.vcCard == VPS_PLATFORM_BOARD_REV_A)
        {
            i2cDevAddr = VPS_VC_BOARD_THS7353_I2C_ADDR;
            status = Vps_platformEnableThs7353(standard, i2cInstId, i2cDevAddr);
        }
        else if(gTi814xBoardVer.vcCard == VPS_PLATFORM_BOARD_REV_B)
        {
            status = Vps_platformTi814xEnableThs73681(standard,
                                            i2cInstId,
                                            gTi814xBoardVer.vcIoExpAddr);
        }
        else
        {
            status = FVID2_EFAIL;
        }
    }

    if (boardId == VPS_PLATFORM_BOARD_CATALOG)
    {
        status = Vps_platformTi814xEnableThs73681(standard,
                                                i2cInstId,
                                                gTi814xBoardVer.caIoExpAddr);
    }

    return (status);
}

#ifdef ENABLE_HDVPSS_CLK
/** \brief Function to enable HDVPSS clock */
static Int32 Vps_platformTI814xEnableHdVpssClk(void)
{
    volatile UInt32 repeatCnt;
    volatile UInt32 regValue;

    GT_assert( GT_DEFAULT_MASK, NULL != gVpsPrcmRegs);
    /* Bring the HDVPSS and HDMI out of reset */
    gVpsPrcmRegs->RM_HDVPSS_RSTCTRL = 0x0;

    /* Start a software forced  wakeup transition on the domain.*/
    regValue = 0x2;
    gVpsPrcmRegs->CM_HDVPSS_CLKSTCTRL = regValue;
    /* Wait for 1000 cycles before checking for power update */
    udelay(1000);

    /* Enable HDVPSS Clocks */
    regValue = 0x2;
    gVpsPrcmRegs->CM_HDVPSS_HDVPSS_CLK_CTRL = regValue;
    /* Enable HDMI Clocks */
    regValue = 0x2;
    gVpsPrcmRegs->CM_HDVPSS_HDMI_CLKCTRL = regValue;

    repeatCnt = 0;
    while (repeatCnt < VPS_PRCM_MAX_REP_CNT)
    {
        /* Check for
         * Current Power State Status
         * HDVPSS memory state status
         * Logic state status */
        regValue = gVpsPrcmRegs->CM_HDVPSS_CLKSTCTRL;
        if ((regValue & 0x100) == 0x100)
        {
            break;
        }
        udelay(1000);
        repeatCnt++;
    }
    if ((regValue & 0x100) != 0x100)
    {
        Vps_printf("HDVPSS Clocks not enabled\n");
    }
    repeatCnt = 0;
    while (repeatCnt < VPS_PRCM_MAX_REP_CNT)
    {
        /* Check for
         * Current Power State Status
         * HDVPSS memory state status
         * Logic state status */
        regValue = gVpsPrcmRegs->CM_HDVPSS_HDVPSS_CLK_CTRL;
        if ((regValue & 0x2) == 0x2)
        {
            break;
        }
        udelay(1000);
        repeatCnt++;
    }
    if ((regValue & 0x2) != 0x2)
    {
        Vps_printf("HDVPSS Clocks not enabled\n");
    }
    /* Bring the HDVPSS and HDMI out of reset */
    gVpsPrcmRegs->RM_HDVPSS_RSTCTRL = 0x0;
    return (FVID2_SOK);
}
#endif

#ifdef ENABLE_I2C_CLK
/** \brief Function sets the SYSCLK10 to 48MHz. SysClk10 is used for CEC
     and I2C */
static Int32 Vps_platformTI814xEnableI2c(void)
{
    volatile UInt32 repeatCnt;

    GT_assert( GT_DEFAULT_MASK, NULL != gVpsPrcmRegs);

    /* Enable Power Domain Transition */
    gVpsPrcmRegs->CM_ALWON_I2C_02_CLKCTRL = 0x2;

    repeatCnt = 0u;
    while (repeatCnt < VPS_PRCM_MAX_REP_CNT)
    {
        if (((gVpsPrcmRegs->CM_ALWON_I2C_02_CLKCTRL &
                    CM_ALWON_I2C_02_CLKCTRL_IDLEST_MASK) >>
                    CM_ALWON_I2C_02_CLKCTRL_IDLEST_SHIFT) == 0u)
        {
            break;
        }

        /* Wait for the 100 cycles */
        udelay(1000);

        repeatCnt++;
    }

    if (((gVpsPrcmRegs->CM_ALWON_I2C_02_CLKCTRL &
            CM_ALWON_I2C_02_CLKCTRL_IDLEST_MASK) >>
            CM_ALWON_I2C_02_CLKCTRL_IDLEST_SHIFT) != 0u)
    {
        Vps_printf("=== I2C0/2 Clk is Non active ===\n");
        return (FVID2_ETIMEOUT);
    }
    else
    {
        Vps_printf("=== I2C0/2 Clk is active ===\n");
    }
    /* Change it to #if 1 to enable I2C1 clk */
#if 0
    /* Enable Power Domain Transition */
    gVpsPrcmRegs->CM_ALWON_I2C_13_CLKCTRL = 0x2;

    repeatCnt = 0u;
    while (repeatCnt < VPS_PRCM_MAX_REP_CNT)
    {
        if (((gVpsPrcmRegs->CM_ALWON_I2C_13_CLKCTRL &
                    CM_ALWON_I2C_13_CLKCTRL_IDLEST_MASK) >>
                    CM_ALWON_I2C_13_CLKCTRL_IDLEST_SHIFT) == 0u)
        {
            break;
        }

        /* Wait for the 100 cycles */
        udelay(1000);

        repeatCnt++;
    }

    if (((gVpsPrcmRegs->CM_ALWON_I2C_13_CLKCTRL &
            CM_ALWON_I2C_13_CLKCTRL_IDLEST_MASK) >>
            CM_ALWON_I2C_13_CLKCTRL_IDLEST_SHIFT) != 0u)
    {
        Vps_printf("=== I2C1/3 Interface Clk is Non active ===\n");
        return (FVID2_ETIMEOUT);
    }
    else
    {
        Vps_printf("=== I2C1/3 Interface Clk is active ===\n");
    }
#endif
    return FVID2_SOK;

}
#endif

Int32 Vps_platformTI814xSelectVideoDecoder(UInt32 vidDecId, UInt32 vipInstId)
{
    UInt32 i2cInstId = Vps_platformTI814xGetI2cInstId();
    UInt32 i2cDevAddr;
    UInt8  regValue[2];
    Vps_PlatformBoardId boardId;
    Int32  status = FVID2_SOK;

    boardId = Vps_platformGetBoardId();

    /* In TI814X, GMII1 and SiL9135A are muxed on the VC board. */
    if(boardId == VPS_PLATFORM_BOARD_VC)
    {
        i2cDevAddr = gTi814xBoardVer.vcIoExpAddr;
        regValue[0] = 0xEF;
        regValue[1] = 0xFF;
    }
    /* DVI Input and TVP input are muxed, select TVP input */
    else if (boardId == VPS_PLATFORM_BOARD_CATALOG)
    {
        i2cDevAddr = gTi814xBoardVer.caIoExpAddr;

        status = Vps_deviceRawRead8(i2cInstId, i2cDevAddr, regValue, 2u);
        GT_assert( GT_DEFAULT_MASK, status==FVID2_SOK);
        /* Configure muxes to select TVP */
        regValue[1] |= (UInt8)(VPS_CA_A1_PCF8575_SEL_TVP_S0_MASK);
        regValue[1] &= (UInt8)~(VPS_PCF8575_P10_17_P17_MASK);
    }
    else
    {
        Vps_printf("Invalid board ID!!!\n");
        status = FVID2_EFAIL;
    }

    if (FVID2_SOK == status)
    {
        status = Vps_deviceRawWrite8(i2cInstId, i2cDevAddr, regValue, 2);
    }

    return status;
}

#if  defined(CONFIG_PLL) || defined(ENABLE_HDVPSS_CLK) || defined (ENABLE_I2C_CLK)
static void udelay(int delay_usec)
{
    Int32 delay_msec;

    delay_msec = delay_usec/1000;
    if(delay_msec==0)
        delay_msec = 1;
    Task_sleep(delay_msec);
}
#endif


#if defined (CONFIG_PLL) || defined(ENABLE_HDVPSS_CLK)
static Int32 Vps_platformPllCfg( volatile UInt32 Base_Address,
                UInt32 N,UInt32 M,UInt32 M2,UInt32 CLKCTRL_VAL)
{
    Int32 rtnValue;
    UInt32 m2nval, mn2val, read_clkctrl;
    volatile UInt32 repeatCnt = 0;
    volatile UInt32 clkCtrlVal;

    /* Put the PLL in bypass mode */
    clkCtrlVal = RD_MEM_32(Base_Address+CLKCTRL);
    clkCtrlVal |= 0x1 << 23;
    WR_MEM_32((Base_Address+CLKCTRL), clkCtrlVal);

    repeatCnt = 0u;
    while (repeatCnt < VPS_PRCM_MAX_REP_CNT)
    {
        if (((RD_MEM_32(Base_Address+STATUS)) & 0x00000101) == 0x00000101)
        {
            break;
        }
        /* Wait for the 100 cycles */
        udelay(10000);
        repeatCnt++;
    }
    if (((RD_MEM_32(Base_Address+STATUS)) & 0x00000101) == 0x00000101)
    {
    ;
    }
    else
    {
    Vps_printf("Not able to put PLL in idle!!!\n");
    }

    /* we would require a soft reset before we program the dividers */
    WR_MEM_32(Base_Address+CLKCTRL, RD_MEM_32(Base_Address+CLKCTRL)& 0xfffffffe);
    udelay(3);

    /* Program the PLL for required frequency */
    m2nval = (M2 << 16) | N;
    mn2val =  M;
    /*ref_clk     = OSC_FREQ/(N+1);
    clkout_dco  = ref_clk*M;
    clk_out     = clkout_dco/M2;
    */
    WR_MEM_32((Base_Address+M2NDIV    ),m2nval);
    WR_MEM_32((Base_Address+MN2DIV    ),mn2val);
    udelay(3);
    WR_MEM_32((Base_Address+TENABLEDIV),0x1);
    udelay(3);
    WR_MEM_32((Base_Address+TENABLEDIV),0x0);
    udelay(3);
    WR_MEM_32((Base_Address+TENABLE   ),0x1);
    udelay(3);
    WR_MEM_32((Base_Address+TENABLE   ),0x0);
    udelay(3);
    read_clkctrl = RD_MEM_32(Base_Address+CLKCTRL);
    /*configure the TINITZ(bit0) and CLKDCO bits if required */
    WR_MEM_32(Base_Address+CLKCTRL,(read_clkctrl & 0xff7fe3ff) | CLKCTRL_VAL);
    read_clkctrl = RD_MEM_32(Base_Address+CLKCTRL);

    /* poll for the freq,phase lock to occur */
    repeatCnt = 0u;
    while (repeatCnt < VPS_PRCM_MAX_REP_CNT)
    {
        if (((RD_MEM_32(Base_Address+STATUS)) & 0x00000600) == 0x00000600)
        {
            break;
        }
        /* Wait for the 100 cycles */
        udelay(10000);
        repeatCnt++;
    }
    if (((RD_MEM_32(Base_Address+STATUS)) & 0x00000600) == 0x00000600)
    {
        //Vps_printf("PLL Locked\n");
        rtnValue = FVID2_SOK;
    }
    else
    {
        Vps_printf("PLL Not Getting Locked!!!\n");
        rtnValue = FVID2_EFAIL;
    }
    /*wait fot the clocks to get stabized */
    udelay(1000);
    return (rtnValue);
}
#endif

/* Relies on I2C Address of IO Expander.
   Alpha 1 IO Expander is at 0x27 and Alpha 2 IO Expander at 0x21 */

static Int32 Vps_getVcCardVersion (Vps_BoardVersion *boardVer)
{
    Int32  status;
    Vps_PlatformBoardRev version;
    UInt8  regValue[2];
    UInt32 expAddr;

    version = boardVer->vcCard;
    status = FVID2_SOK;

    if (version == VPS_PLATFORM_BOARD_REV_UNKNOWN)
    {
        Semaphore_pend(boardVer->ioExpLock, BIOS_WAIT_FOREVER);

        /* Check if its Alpha 1 - REV A */
        status = Vps_deviceRawRead8(Vps_platformTI814xGetI2cInstId(),
                        VPS_VC_BOARD_A1_IO_EXP_I2C_ADDR, regValue, 2u);
        if (status == FVID2_SOK)
        {
            version = VPS_PLATFORM_BOARD_REV_A;
            expAddr = VPS_VC_BOARD_A1_IO_EXP_I2C_ADDR;
        }
        else
        {   /* Otherwise shoule be Alpha 2 - check to ensure */
            status = Vps_deviceRawRead8(Vps_platformTI814xGetI2cInstId(),
                            VPS_VC_BOARD_A2_IO_EXP_I2C_ADDR, regValue, 2u);
            if (status == FVID2_SOK)
            {
                version = VPS_PLATFORM_BOARD_REV_B;
                expAddr = VPS_VC_BOARD_A2_IO_EXP_I2C_ADDR;
            }
        }

        if (status == FVID2_SOK)
        {
            boardVer->vcCard      = version;
            boardVer->vcIoExpAddr = expAddr;
        }

        Semaphore_post(boardVer->ioExpLock);
    }
    return (status);
}

/* Used for VC - Aplha 2 card only */
static Int32 Vps_platformTi814xEnableThs73681(FVID2_Standard standard,
                                              UInt32 i2cInst,
                                              UInt32 ioExpAddr)
{
    Int32       status = FVID2_SOK;
    UInt8       regValue[2];

    status = Vps_deviceRawRead8(i2cInst, ioExpAddr, regValue, 2u);
    GT_assert( GT_DEFAULT_MASK, status==FVID2_SOK);

    /*  PCF8575 - mappings
        P7 - THS73861_FILTER2
        P6 - THS73861_FILTER1
        P5 - THS73861_BYPASS
        P4 - THS73861_DISABLE
        P0 - TVP7002_RSTN */
            /* Enable filter, disable bypass, clear filter select bits */
    regValue[0] &= ~( VPS_VC_A2_PCF8575_THS73861_DISABLE_MASK
                    | VPS_VC_A2_PCF8575_THS73861_BYPASS_MASK
                    | VPS_VC_A2_PCF8575_THS73861_FILTER1_MASK
                    | VPS_VC_A2_PCF8575_THS73861_FILTER2_MASK);

    switch (standard)
    {
        case FVID2_STD_1080P_60:
        case FVID2_STD_1080P_50:
        case FVID2_STD_SXGA_60:
        case FVID2_STD_SXGA_75:
        case FVID2_STD_SXGAP_60:
        case FVID2_STD_SXGAP_75:
        case FVID2_STD_UXGA_60:
            /* Filter2: 1, Filter1: 1 */
            regValue[0] |=  (UInt8)
                            (VPS_VC_A2_PCF8575_THS73861_FILTER1_MASK |
                             VPS_VC_A2_PCF8575_THS73861_FILTER2_MASK);
            break;

        case FVID2_STD_1080I_60:
        case FVID2_STD_1080I_50:
        case FVID2_STD_1080P_24:
        case FVID2_STD_1080P_30:
        case FVID2_STD_720P_60:
        case FVID2_STD_720P_50:
        case FVID2_STD_SVGA_60:
        case FVID2_STD_SVGA_72:
        case FVID2_STD_SVGA_75:
        case FVID2_STD_SVGA_85:
        case FVID2_STD_XGA_60:
        case FVID2_STD_XGA_70:
        case FVID2_STD_XGA_75:
        case FVID2_STD_XGA_85:
        case FVID2_STD_WXGA_60:
        case FVID2_STD_WXGA_75:
        case FVID2_STD_WXGA_85:
            /* Filter2: 0, Filter1: 1 */
            regValue[0] &= (UInt8)
                           ~(VPS_VC_A2_PCF8575_THS73861_FILTER2_MASK);
            regValue[0] |= (UInt8)
                            (VPS_VC_A2_PCF8575_THS73861_FILTER1_MASK);
            break;

        case FVID2_STD_480P:
        case FVID2_STD_576P:
        case FVID2_STD_VGA_60:
        case FVID2_STD_VGA_72:
        case FVID2_STD_VGA_75:
        case FVID2_STD_VGA_85:
            /* Filter2: 1, Filter1: 0 */
            regValue[0] &= (UInt8)
                           ~(VPS_VC_A2_PCF8575_THS73861_FILTER1_MASK);
            regValue[0] |= (UInt8)
                            (VPS_VC_A2_PCF8575_THS73861_FILTER2_MASK);
            break;

        case FVID2_STD_NTSC:
        case FVID2_STD_PAL:
        case FVID2_STD_480I:
        case FVID2_STD_576I:
        case FVID2_STD_D1:
            /* Filter2: 0, Filter1: 0 */
            regValue[0] &=  (UInt8)
                            ~(VPS_VC_A2_PCF8575_THS73861_FILTER1_MASK |
                             VPS_VC_A2_PCF8575_THS73861_FILTER2_MASK);
            break;

        default:
            /* Filter2: 0, Filter1: 1 */
            regValue[0] &= (UInt8)
                           ~(VPS_VC_A2_PCF8575_THS73861_FILTER2_MASK);
            regValue[0] |= (UInt8)
                            (VPS_VC_A2_PCF8575_THS73861_FILTER1_MASK);
            break;
    }

    Vps_deviceRawWrite8(i2cInst, ioExpAddr, regValue, 2u);
    Task_sleep(500);

    return (status);
}

iss_platformTI814x.c

/** ==================================================================
 *  @file   iss_platformTI814x.c                                                  
 *                                                                    
 *  @path   /ti/psp/platforms/ti814x/src/                                                  
 *                                                                    
 *  @desc   This  File contains.                                      
 * ===================================================================
 *  Copyright (c) Texas Instruments Inc 2011, 2012                    
 *                                                                    
 *  Use of this software is controlled by the terms and conditions found
 *  in the license agreement under which this software has been supplied
 * ===================================================================*/

/**
 *  \file iss_platformTI814x.c
 *
 *  \brief Implements the TI814x platform specific functions.
 *
 */

/* ========================================================================== 
 */
/* Include Files */
/* ========================================================================== 
 */

#include <string.h>
#include <xdc/std.h>
#include <xdc/runtime/System.h>
#include <ti/sysbios/knl/Task.h>
#include <ti/sysbios/knl/Semaphore.h>
#include <ti/psp/vps/common/trace.h>
#include <ti/psp/iss/iss.h>
#include <ti/psp/platforms/iss_platform.h>
#include <ti/psp/cslr/soc_TI814x.h>
#include <ti/psp/cslr/cslr_TI814xprcm.h>
#include <ti/psp/cslr/cslr_TI814xpll.h>
#include <ti/psp/devices/iss_sensorDriver.h>
#include <ti/psp/platforms/ti814x/iss_platformTI814x.h>

/* ========================================================================== 
 */
/* Macros & Typedefs */
/* ========================================================================== 
 */

#define ENABLE_HDVPSS_CLK

/* Enable I2C control to configure ecn/dec */
#define ENABLE_I2C_CLK

/* Set the PLLs */
#define CONFIG_PLL

#define ISS_VS_BOARD_IO_EXP_I2C_ADDR    (0x21u)

#define ISS_VC_BOARD_A1_IO_EXP_I2C_ADDR (0x27u)
#define ISS_VC_BOARD_A2_IO_EXP_I2C_ADDR (0x21u)

#define ISS_CA_BOARD_A1_IO_EXP_I2C_ADDR (0x21u)

#define ISS_PLATFORM_EVM_I2C_INST_ID    (ISS_DEVICE_I2C_INST_ID_0)

/** \brief PLL Control Module Base Address*/
#define ISS_CONTROL_MODULE_PLL_CTRL_BASE_ADDR   (CSL_TI814x_PLL_BASE)

/** \brief Control Module Device Configuration Base Address */
#define ISS_CTRL_MODULE_DEV_CFG_BASE_ADDR       (CSL_TI814x_CTRL_MODULE_BASE + \
                                                    0x0600u)

/* Default Values for DDR PLL configuration to get clock for I2C and CEC */
#define ISS_DDR_INT_FREQ2               (0x8u)
#define ISS_DDR_FRACT_FREQ2             (0xD99999u)
#define ISS_DDR_MDIV2                   (0x1Eu)
#define ISS_DDR_SYCCLK10_DIV            (0x0u)

/* gpio base addresses */
#define REG32                           *(volatile unsigned int*)

#define ISS_PRCM_CLKTRCTRL_NO_SLEEP     (0u)
#define ISS_PRCM_CLKTRCTRL_SW_SLEEP     (1u)
#define ISS_PRCM_CLKTRCTRL_SW_WKUP      (2u)
#define ISS_PRCM_CLKTRCTRL_HW_AUTO      (3u)

#define ISS_PRCM_MODULE_DISABLE         (0u)
#define ISS_PRCM_MODULE_ENABLE          (2u)

#define ISS_PRCM_MAX_REP_CNT            (100u)

/* ADPLLJ_CLKCRTL_Register Value Configurations ADPLLJ_CLKCRTL_Register SPEC
 * bug bit 19,bit29 -- CLKLDOEN,CLKDCOEN */
#define ADPLLJ_CLKCRTL_HS2              (0x00000801u)
/* HS2 Mode,TINTZ =1 --used by all PLL's except HDMI */
#define ADPLLJ_CLKCRTL_HS1              (0x00001001u)
/* HS1 Mode,TINTZ =1 --used only for HDMI */
#define ADPLLJ_CLKCRTL_CLKDCO           (0x200a0000u)
/* Enable CLKDCOEN,CLKLDOEN,CLKDCOPWDNZ -- used for HDMI,USB */
#define ISS_TI814X_KHz                  (1000u)
#define ISS_TI814X_MHz                  (ISS_TI814X_KHz * ISS_TI814X_KHz)
#define ISS_TI814X_EVM_OSC_FREQ         (20u * ISS_TI814X_MHz)


#ifndef BOARD_AP_IPNC
#define BOARD_AP_IPNC
#endif

#ifdef BOARD_TI_EVM
#undef BOARD_TI_EVM
#endif
/* ========================================================================== 
 */
/* Structure Declarations */
/* ========================================================================== 
 */

/* \brief structure to keep track of pll configurations for a video mode */
typedef struct {
    UInt32 __n;
    /**< Divider N for the PLL.*/
    UInt32 __m;
    /**< Multiplier M for the PLL.*/
    UInt32 __m2;
    /**< Divider M2 for the PLL.*/
    UInt32 clkCtrlValue;
    /**< For comparison based on the clkOut used */
} Iss_VideoPllCtrl;

/* Structure to track the versions of boards */
typedef struct {
    Iss_PlatformBoardRev vcCard;
    UInt32 vcIoExpAddr;
    Semaphore_Handle ioExpLock;
    Iss_PlatformBoardRev vsCard_notused;                   /* Not used as of
                                                            * now */
    Iss_PlatformBoardRev baseBoard_notused;                /* Not used as of
                                                            * now */
    Iss_PlatformBoardRev caCard;
    UInt32 caIoExpAddr;
} Iss_BoardVersion;

/* ========================================================================== 
 */
/* Function Declarations */
/* ========================================================================== 
 */

/* ===================================================================
 *  @func     Iss_platformTI814xSetPinMux                                               
 *                                                                    
 *  @desc     Function does the following                             
 *                                                                    
 *  @modif    This function modifies the following structures         
 *                                                                    
 *  @inputs   This function takes the following inputs                
 *            <argument name>                                         
 *            Description of usage                                    
 *            <argument name>                                         
 *            Description of usage                                    
 *                                                                    
 *  @outputs  <argument name>                                         
 *            Description of usage                                    
 *                                                                    
 *  @return   Return value of this function if any                    
 *  ==================================================================
 */                                                                   
static Int32 Iss_platformTI814xSetPinMux(void);

#ifdef POWER_OPT_DSS_OFF
/* ===================================================================
 *  @func     Iss_platformTI814xSetIntMux                                               
 *                                                                    
 *  @desc     Function does the following                             
 *                                                                    
 *  @modif    This function modifies the following structures         
 *                                                                    
 *  @inputs   This function takes the following inputs                
 *            <argument name>                                         
 *            Description of usage                                    
 *            <argument name>                                         
 *            Description of usage                                    
 *                                                                    
 *  @outputs  <argument name>                                         
 *            Description of usage                                    
 *                                                                    
 *  @return   Return value of this function if any                    
 *  ==================================================================
 */                                                                   
static Int32 Iss_platformTI814xSetIntMux(void);
#endif

/* ========================================================================== 
 */
/* Global Variables */
/* ========================================================================== 
 */

/**< Variable to track the version of daughter card, we have Aplha 1 and
     Alpha 2, designated as REV A and REV B */
static Iss_BoardVersion gTi814xBoardVer = { ISS_PLATFORM_BOARD_REV_UNKNOWN,
    ISS_VC_BOARD_A1_IO_EXP_I2C_ADDR,
    ISS_PLATFORM_BOARD_REV_UNKNOWN,
    ISS_PLATFORM_BOARD_REV_UNKNOWN
};

/* ========================================================================== 
 */
/* Function Definitions */
/* ========================================================================== 
 */

/* ===================================================================
 *  @func     Iss_platformTI814xInit                                               
 *                                                                    
 *  @desc     Function does the following                             
 *                                                                    
 *  @modif    This function modifies the following structures         
 *                                                                    
 *  @inputs   This function takes the following inputs                
 *            <argument name>                                         
 *            Description of usage                                    
 *            <argument name>                                         
 *            Description of usage                                    
 *                                                                    
 *  @outputs  <argument name>                                         
 *            Description of usage                                    
 *                                                                    
 *  @return   Return value of this function if any                    
 *  ==================================================================
 */                                                                   
Int32 Iss_platformTI814xInit(Iss_PlatformInitParams * initParams)
{
    Int32 status = FVID2_SOK;

    Iss_platformTI814xSetPinMux();

#ifdef POWER_OPT_DSS_OFF
    Iss_platformTI814xSetIntMux();
#endif

#ifdef ENABLE_HDVPSS_CLK
    /* Initialize Pixel Clock */
    // status |= Iss_platformTI814xConfigHdIsssPll();
    // status |= Iss_platformTI814xEnableHdIsssClk();
#endif

#ifdef ENABLE_I2C_CLK
    // status |= Iss_platformTI814xEnableI2c();
#endif

    return (status);
}

#ifdef POWER_OPT_DSS_OFF

/* ===================================================================
 *  @func     Iss_platformTI814xSetIntMux                                               
 *                                                                    
 *  @desc     Function does the following                             
 *                                                                    
 *  @modif    This function modifies the following structures         
 *                                                                    
 *  @inputs   This function takes the following inputs                
 *            <argument name>                                         
 *            Description of usage                                    
 *            <argument name>                                         
 *            Description of usage                                    
 *                                                                    
 *  @outputs  <argument name>                                         
 *            Description of usage                                    
 *                                                                    
 *  @return   Return value of this function if any                    
 *  ==================================================================
 */                                                                   
static Int32 Iss_platformTI814xSetIntMux(void)
{
    volatile unsigned int int_mux;

    /* I2C2 interrupt is routed through I2C1 interrupt through the crossbar.
     * For this, INT_MUX_[#int_number] register in the Chip Control Module
     * needs to be programmed. INT_MUX_[#int_number] registers start from
     * 0xF54 offset and one register is used to program 4 interrupt muxes (6
     * bits for each mux, 2 bits reserved). After reset INT_MUX_[#int_number] 
     * defaults to 000000, which maps the interrupt from default mapping to
     * interrupt_[#int_number]. I2C_INT1 is mapped to interrupt line 19 and
     * INTMUX 16 to 19 --> 0x0f64. So read it first, modify the respective
     * bit field and write is back. */
    int_mux = REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0f64);
    /* I2CINT2 value = 4, INT_MUX_19_SHIFT = 24 */
    int_mux |= (4 << 24);
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0f64) = int_mux;

    return (FVID2_SOK);
}
#endif

/* ===================================================================
 *  @func     Iss_platformTI814xDeInit                                               
 *                                                                    
 *  @desc     Function does the following                             
 *                                                                    
 *  @modif    This function modifies the following structures         
 *                                                                    
 *  @inputs   This function takes the following inputs                
 *            <argument name>                                         
 *            Description of usage                                    
 *            <argument name>                                         
 *            Description of usage                                    
 *                                                                    
 *  @outputs  <argument name>                                         
 *            Description of usage                                    
 *                                                                    
 *  @return   Return value of this function if any                    
 *  ==================================================================
 */                                                                   
Int32 Iss_platformTI814xDeInit(void)
{
    Int32 status = FVID2_SOK;

    return (status);
}

/* Init EVM related sub-systems like I2C instance */
/* ===================================================================
 *  @func     Iss_platformTI814xDeviceInit                                               
 *                                                                    
 *  @desc     Function does the following                             
 *                                                                    
 *  @modif    This function modifies the following structures         
 *                                                                    
 *  @inputs   This function takes the following inputs                
 *            <argument name>                                         
 *            Description of usage                                    
 *            <argument name>                                         
 *            Description of usage                                    
 *                                                                    
 *  @outputs  <argument name>                                         
 *            Description of usage                                    
 *                                                                    
 *  @return   Return value of this function if any                    
 *  ==================================================================
 */                                                                   
Int32 Iss_platformTI814xDeviceInit(Iss_PlatformDeviceInitParams * initPrms)
{
    Int32 status = FVID2_SOK;

    Vps_DeviceInitParams deviceInitPrm;

#ifdef POWER_OPT_DSS_OFF
    UInt8 i2cCnt = 0;

    /* TI814x has 4 I2C instances. */
    UInt32 i2cRegs[ISS_DEVICE_I2C_INST_ID_MAX] = { CSL_TI814x_I2C0_BASE,
        CSL_TI814x_I2C1_BASE,
        CSL_TI814x_I2C2_BASE,
        CSL_TI814x_I2C3_BASE
    };
    UInt32 i2cInt[ISS_DEVICE_I2C_INST_ID_MAX] = { CSL_INTC_EVENTID_I2CINT0,
        CSL_INTC_EVENTID_I2CINT1,
        CSL_INTC_EVENTID_I2CINT2,
        CSL_INTC_EVENTID_I2CINT3
    };
    /* 
     * External video device subsystem init
     */
    memset(&deviceInitPrm, 0, sizeof(deviceInitPrm));

    /* 
     * Initialize I2C instances
     */
    for (i2cCnt = 0; i2cCnt < ISS_DEVICE_I2C_INST_ID_MAX; i2cCnt++)
    {
        deviceInitPrm.i2cRegs[i2cCnt] = (Ptr) (i2cRegs[i2cCnt]);
        deviceInitPrm.i2cIntNum[i2cCnt] = i2cInt[i2cCnt];
        deviceInitPrm.i2cClkKHz[i2cCnt] = VPS_DEVICE_I2C_INST_NOT_USED;
    }
    deviceInitPrm.isI2cInitReq = initPrms->isI2cInitReq;

    /* TI814x uses only I2C[2], so modify the sampling frequency */
    deviceInitPrm.i2cRegs[ISS_PLATFORM_EVM_I2C_INST_ID]
        = (Ptr) CSL_TI814x_I2C0_BASE;
    deviceInitPrm.i2cIntNum[ISS_PLATFORM_EVM_I2C_INST_ID]
        = CSL_INTC_EVENTID_I2CINT0;
    deviceInitPrm.i2cClkKHz[ISS_PLATFORM_EVM_I2C_INST_ID] = 100;
#ifdef TI_8107_BUILD
#ifdef _IPNC_HW_PLATFORM_EVM_		
    deviceInitPrm.i2cClkKHz[ISS_PLATFORM_EVM_I2C_INST_ID]
        = 50;
#endif		
#endif		
#endif


    deviceInitPrm.i2cRegs[0] = (Ptr) CSL_TI814x_I2C0_BASE;
    deviceInitPrm.i2cIntNum[0] = CSL_INTC_EVENTID_I2CINT0;
    
    deviceInitPrm.i2cRegs[ISS_DEVICE_I2C_INST_ID_2] = (Ptr) CSL_TI814x_I2C2_BASE;
    deviceInitPrm.i2cIntNum[ISS_DEVICE_I2C_INST_ID_2] = CSL_INTC_EVENTID_I2CINT2;
    deviceInitPrm.i2cClkKHz[ISS_DEVICE_I2C_INST_ID_2]  = 100;
 
    Vps_printf("%s: deviceInitPrm.i2cClkKHz[ISS_PLATFORM_EVM_I2C_INST_ID] : %d\n", __func__, deviceInitPrm.i2cClkKHz[ISS_PLATFORM_EVM_I2C_INST_ID]);
    Vps_printf ("###### ISS_PLATFORM_EVM_I2C_INST_ID : %d\n",ISS_PLATFORM_EVM_I2C_INST_ID);

    Vps_printf("%s: deviceInitPrm.i2cClkKHz[ISS_DEVICE_I2C_INST_ID_2] : %d\n", __func__, deviceInitPrm.i2cClkKHz[ISS_DEVICE_I2C_INST_ID_2]);
    Vps_printf ("###### ISS_DEVICE_I2C_INST_ID_2 : %d\n", ISS_DEVICE_I2C_INST_ID_2);

    status = Iss_deviceInit(&deviceInitPrm);

    return (status);
}

/* De-Init EVM related sub-systems */
/* ===================================================================
 *  @func     Iss_platformTI814xDeviceDeInit                                               
 *                                                                    
 *  @desc     Function does the following                             
 *                                                                    
 *  @modif    This function modifies the following structures         
 *                                                                    
 *  @inputs   This function takes the following inputs                
 *            <argument name>                                         
 *            Description of usage                                    
 *            <argument name>                                         
 *            Description of usage                                    
 *                                                                    
 *  @outputs  <argument name>                                         
 *            Description of usage                                    
 *                                                                    
 *  @return   Return value of this function if any                    
 *  ==================================================================
 */                                                                   
Int32 Iss_platformTI814xDeviceDeInit(void)
{
    /* 
     * Extern video device de-init
     */
    Iss_deviceDeInit();

    return (FVID2_SOK);
}

/* ===================================================================
 *  @func     Iss_platformTI814xGetI2cInstId                                               
 *                                                                    
 *  @desc     Function does the following                             
 *                                                                    
 *  @modif    This function modifies the following structures         
 *                                                                    
 *  @inputs   This function takes the following inputs                
 *            <argument name>                                         
 *            Description of usage                                    
 *            <argument name>                                         
 *            Description of usage                                    
 *                                                                    
 *  @outputs  <argument name>                                         
 *            Description of usage                                    
 *                                                                    
 *  @return   Return value of this function if any                    
 *  ==================================================================
 */                                                                   
UInt32 Iss_platformTI814xGetI2cInstId(void)
{
    return (ISS_PLATFORM_EVM_I2C_INST_ID);
}

/* ===================================================================
 *  @func     Iss_platformTI814xGetSensorI2cAddr                                               
 *                                                                    
 *  @desc     Function does the following                             
 *                                                                    
 *  @modif    This function modifies the following structures         
 *                                                                    
 *  @inputs   This function takes the following inputs                
 *            <argument name>                                         
 *            Description of usage                                    
 *            <argument name>                                         
 *            Description of usage                                    
 *                                                                    
 *  @outputs  <argument name>                                         
 *            Description of usage                                    
 *                                                                    
 *  @return   Return value of this function if any                    
 *  ==================================================================
 */                                                                   
UInt8 Iss_platformTI814xGetSensorI2cAddr(UInt32 vidDecId, UInt32 vipInstId)
{
    UInt8 devAddr = 0x0;

#ifdef BOARD_AP_IPNC
    UInt8 devAddrAr0331[ISS_CAPT_INST_MAX] = { 0x10 };
    UInt8 devAddrMn34041[ISS_CAPT_INST_MAX] = { 0x10 };
    UInt8 devAddrImx035[ISS_CAPT_INST_MAX] = { 0x10 };
    UInt8 devAddrOv2715[ISS_CAPT_INST_MAX] = { 0x36 };
    UInt8 devAddrImx036[ISS_CAPT_INST_MAX] = { 0x30 };
    UInt8 devAddrOv9712[ISS_CAPT_INST_MAX] = { 0x30 };
    UInt8 devAddrOv10630[ISS_CAPT_INST_MAX] = { 0x30 };
    UInt8 devAddrMt9p031[ISS_CAPT_INST_MAX] = { 0x48 };
    UInt8 devAddrMt9d131[ISS_CAPT_INST_MAX] = { 0x5D };
    UInt8 devAddrMt9m034[ISS_CAPT_INST_MAX] = { 0x10 };
    UInt8 devAddrTvp514x[ISS_CAPT_INST_MAX] = { 0x48 };
    UInt8 devAddrMt9j003[ISS_CAPT_INST_MAX] = { 0x36 };
    UInt8 devAddrAr0330[ISS_CAPT_INST_MAX] = { 0x10 };
    UInt8 devAddrMt9m034dbl[ISS_CAPT_INST_MAX] = { 0x10 };
    UInt8 devAddrImx136[ISS_CAPT_INST_MAX] = {0x2d};	//lvds324
	UInt8 devAddrImx122[ISS_CAPT_INST_MAX] = { 0xFF };	/* IMX-122 use SPI interface so it has no meaning */
    UInt8 devAddrOv7740[ISS_CAPT_INST_MAX] = { 0x21 };
    UInt8 devAddrOv2710[ISS_CAPT_INST_MAX] = { 0x36 };
    UInt8 devAddrImx104[ISS_CAPT_INST_MAX] = { 0x21 };
    UInt8 devAddrAl30210[ISS_CAPT_INST_MAX] = { 0x21 };
#endif
#ifdef BOARD_TI_EVM
    UInt8 devAddrAr0331[ISS_CAPT_INST_MAX] = { 0x10 };
    UInt8 devAddrMn34041[ISS_CAPT_INST_MAX] = { 0x10 };
    UInt8 devAddrImx035[ISS_CAPT_INST_MAX] = { 0x10 };
    UInt8 devAddrOv2715[ISS_CAPT_INST_MAX] = { 0x36 };
    UInt8 devAddrImx036[ISS_CAPT_INST_MAX] = { 0x30 };
    UInt8 devAddrOv9712[ISS_CAPT_INST_MAX] = { 0x48 };
    UInt8 devAddrOv10630[ISS_CAPT_INST_MAX] = { 0x30 };
    UInt8 devAddrMt9p031[ISS_CAPT_INST_MAX] = { 0x5D };
    UInt8 devAddrMt9d131[ISS_CAPT_INST_MAX] = { 0x5D };
    UInt8 devAddrMt9m034[ISS_CAPT_INST_MAX] = { 0x5D };
    UInt8 devAddrTvp514x[ISS_CAPT_INST_MAX] = { 0x5D };
    UInt8 devAddrMt9j003[ISS_CAPT_INST_MAX] = { 0x36 };
    UInt8 devAddrMt9m034dbl[ISS_CAPT_INST_MAX] = { 0x10 };
    UInt8 devAddrImx136[ISS_CAPT_INST_MAX] = {0x2d};//lvds324
    UInt8 devAddrOv7740[ISS_CAPT_INST_MAX] = { 0x21 };
    UInt8 devAddrOv2710[ISS_CAPT_INST_MAX] = { 0x36 };
    UInt8 devAddrImx104[ISS_CAPT_INST_MAX] = { 0x21 };
    UInt8 devAddrAl30210[ISS_CAPT_INST_MAX] = { 0x21 };
#endif
    //UInt8 devAddrOv7740[ISS_CAPT_INST_MAX] = { 0x21 };
    GT_assert(GT_DEFAULT_MASK, vipInstId < ISS_CAPT_INST_MAX);

    switch (vidDecId)
    {
        case FVID2_ISS_SENSOR_AR0331_DRV:
            devAddr = devAddrAr0331[vipInstId];
            break;

        case FVID2_ISS_SENSOR_MN34041_DRV:
            devAddr = devAddrMn34041[vipInstId];
            break;

        case FVID2_ISS_SENSOR_IMX035_DRV:
            devAddr = devAddrImx035[vipInstId];
            break;

        case FVID2_ISS_SENSOR_OV2715_DRV:

            devAddr = devAddrOv2715[vipInstId];
            Vps_printf
                ("##&&Iss_platformTI814xGetSensorI2cAddr -- vipInstId=%d, devAddrOv2715[vipInstId]= %x !\n",
                 vipInstId, devAddrOv2715[vipInstId]);
            break;

        case FVID2_ISS_SENSOR_IMX036_DRV:
            devAddr = devAddrImx036[vipInstId];
            break;

        case FVID2_ISS_SENSOR_OV9712_DRV:
            devAddr = devAddrOv9712[vipInstId];

            break;

        case FVID2_ISS_SENSOR_OV10630_DRV:
            devAddr = devAddrOv10630[vipInstId];

            break;

        case FVID2_ISS_SENSOR_MT9P031_DRV:
            devAddr = devAddrMt9p031[vipInstId];

            break;

        case FVID2_ISS_SENSOR_MT9D131_DRV:

            devAddr = devAddrMt9d131[vipInstId];
            break;

        case FVID2_ISS_SENSOR_MT9M034_DRV:
            devAddr = devAddrMt9m034[vipInstId];
            break;
        case FVID2_ISS_SENSOR_TVP514X_DRV:
            devAddr = devAddrTvp514x[vipInstId];
            break;
        case FVID2_ISS_SENSOR_AR0330_DRV:
            devAddr = devAddrAr0330[vipInstId];
            break;
		case FVID2_ISS_SENSOR_MT9M034_DUAL_HEAD_BOARD_DRV:
			devAddr = devAddrMt9m034dbl[vipInstId];
			break;
        case FVID2_ISS_SENSOR_MT9J003_DRV:
            devAddr = devAddrMt9j003[vipInstId];
            break;
        case FVID2_ISS_SENSOR_OV7740_DRV:
            devAddr = devAddrOv7740[vipInstId];
            break;
        case FVID2_ISS_SENSOR_OV2710_DRV:
            devAddr = devAddrOv2710[vipInstId];
            break;
        case FVID2_ISS_SENSOR_IMX136_DRV:
            devAddr = devAddrImx136[vipInstId];
            break;
        case FVID2_ISS_SENSOR_IMX104_DRV:
	       devAddr = devAddrImx104[vipInstId];
            break;	
        case FVID2_ISS_SENSOR_AL30210_DRV:
            devAddr = devAddrAl30210[vipInstId];
            break;	
		case FVID2_ISS_SENSOR_IMX122_DRV:
			devAddr = devAddrImx122[vipInstId];
            break;	
        default:
            GT_0trace(GT_DEFAULT_MASK, GT_ERR, "Invalid decoder ID\n");
            break;
    }

    return (devAddr);
}

#define CSL_TI814x_ISS_BASE 0x0                            // to be done
#define ISSHAL_VIP_INST_MAX 0x1                            // to be done
#define ISSHAL_ISS_CLKC_VIP0 0x1                           // to be done
#define ISSHAL_ISS_CLKC_VIP1 0x1                           // to be done

/* ===================================================================
 *  @func     Iss_platformTI814xSetPinMux                                               
 *                                                                    
 *  @desc     Function does the following                             
 *                                                                    
 *  @modif    This function modifies the following structures         
 *                                                                    
 *  @inputs   This function takes the following inputs                
 *            <argument name>                                         
 *            Description of usage                                    
 *            <argument name>                                         
 *            Description of usage                                    
 *                                                                    
 *  @outputs  <argument name>                                         
 *            Description of usage                                    
 *                                                                    
 *  @return   Return value of this function if any                    
 *  ==================================================================
 */                                                                   
static Int32 Iss_platformTI814xSetPinMux(void)
{
#ifdef CBB_PLATFORM
	//	
#else
    /* Vout 0 configuration DVO2 Function 1 */
    /* TODO There are two pins for the fid. Need to see whichone is used */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0AB8) = 0x2;     /* vout0_fid_mux1 */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0ABC) = 0x1;     /* vout0_clk */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0AC0) = 0x1;     /* vout0_hsync */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0AC4) = 0x1;     /* vout0_vsync */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0AC8) = 0x80;    /* vout0_avid */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0ACC) = 0x80;    /* vout0_b_cb_c[2] 
                                                            */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0AD0) = 0x80;    /* vout0_b_cb_c[3] 
                                                            */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0AD4) = 0x1;     /* vout0_b_cb_c[4] 
                                                            */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0AD8) = 0x1;     /* vout0_b_cb_c[5] 
                                                            */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0ADC) = 0x1;     /* vout0_b_cb_c[6] 
                                                            */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0AE0) = 0x1;     /* vout0_b_cb_c[7] 
                                                            */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0AE4) = 0x1;     /* vout0_b_cb_c[8] 
                                                            */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0AE8) = 0x1;     /* vout0_b_cb_c[9] 
                                                            */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0AEC) = 0x80;    /* vout0_g_y_yc[2] 
                                                            */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0AF0) = 0x1;     /* vout0_g_y_yc[3] 
                                                            */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0AF4) = 0x1;     /* vout0_g_y_yc[4] 
                                                            */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0AF8) = 0x1;     /* vout0_g_y_yc[5] 
                                                            */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0AFC) = 0x1;     /* vout0_g_y_yc[6] 
                                                            */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0B00) = 0x1;     /* vout0_g_y_yc[7] 
                                                            */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0B04) = 0x1;     /* vout0_g_y_yc[8] 
                                                            */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0B08) = 0x1;     /* vout0_g_y_yc[9] 
                                                            */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0B0C) = 0x80;    /* vout0_r_cr[2] */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0B10) = 0x1;     /* vout0_r_cr[3] */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0B14) = 0x1;     /* vout0_r_cr[4] */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0B18) = 0x1;     /* vout0_r_cr[5] */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0B1C) = 0x1;     /* vout0_r_cr[6] */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0B20) = 0x1;     /* vout0_r_cr[7] */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0B24) = 0x1;     /* vout0_r_cr[8] */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0B28) = 0x1;     /* vout0_r_cr[9] */

#if 0
    /* HDMI I2C_scl and I2C_sda Function 2 */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0934) = 0xE0002; /* hdmi_ddc_scl_mux0 
                                                            */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0938) = 0xE0002; /* hdmi_ddc_sda_mux0 
                                                            */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x09BC) = 0x40010; /* hdmi_hpd_mux0
                                                            * pinmmr112[4] */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x09B8) = 0x60010; /* hdmi_cec_mux0
                                                            * pinmmr111[4] */
    /* TODO HDMI CEC and HPD to be added in pinmux */
    /* Currently its shared with GPMC. */
#endif

    /* VIN0 TODO Do we need to enable RXACTIVE Bit in pinmux for input pins? */
    /* Vin0 hsync1 and vin0 vsync1 */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A14) = 0x40001; /* vin0_clk1 */
//     REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A18) = 0xE0001; /* vin0_de0_mux0 - 
//                                                             * DeSelect input */
//     REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A1C) = 0xE0001; /* vin0_fld0_mux0 */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A20) = 0xC0001; /* vin0_clk0 */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A24) = 0xE0001; /* vin0_hsync0 */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A28) = 0xE0001; /* vin0_vsync0 */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A2C) = 0xC0001; /* vin0_d0 */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A30) = 0xC0001; /* vin0_d1 */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A34) = 0xC0001; /* vin0_d2 */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A38) = 0xC0001; /* vin0_d3 */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A3c) = 0xC0001; /* vin0_d4 */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A40) = 0xC0001; /* vin0_d5 */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A44) = 0xC0001; /* vin0_d6 */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A48) = 0xC0001; /* vin0_d7 */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A4c) = 0xC0001; /* vin0_d8 */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A50) = 0xC0001; /* vin0_d9 */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A54) = 0xC0080; /* vin0_d10 */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A58) = 0xC0080; /* vin0_d11 */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A5C) = 0x40001; /* vin0_d12 */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A60) = 0xC0080; /* vin0_d13 */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A64) = 0xC0080; /* vin0_d14 */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A68) = 0xC0080; /* vin0_d15 */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A6C) = 0xE0002; /* vin0_d16 */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A70) = 0xC0002; /* vin0_d17 */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A74) = 0xE0002; /* vin0_d18 */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A78) = 0xE0002; /* vin0_d19 */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A7C) = 0xC0002; /* vin0_d20 */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A80) = 0x40002; /* vin0_d21 */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A84) = 0x40002; /* vin0_d22 */
#ifdef 	IMGS_OMNIVISION_OV7740
	REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A88) = 0x50001;	 /* vin0_d23 */
	REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A8C) = 0x50001;	 /* vin0_de0_mux1 */
	REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A90) = 0x50001;	/* vin0_de1 */
	REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A94) = 0x50001;	 /* vin0_fld0_mux1 */
	REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A98) = 0x50001;	 /* vin0_fld1 */
#else
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A88) = 0x40002; /* vin0_d23 */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A8C) = 0x60002; /* vin0_de0_mux1 */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A90) = 0x60002; /* vin0_de1 */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A94) = 0x60002; /* vin0_fld0_mux1 */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A98) = 0x60002; /* vin0_fld1 */
#endif
    /* VIN1 Configuration Function 3 */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0B2C) = 0x40001; /* vin1_hsync0 */
    /* this is function 2 */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x09F0) = 0x60001; /* vin1_clk1 */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0B30) = 0x40001; /* vin1_vsync0 */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0B34) = 0x40001; /* vin1_de0 */

    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0B38) = 0x40001; /* vin1_clk0 */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0B3C) = 0x40001; /* vin1a_d[0] */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0B40) = 0x40001; /* vin1a_d[1] */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0B44) = 0x40001; /* vin1a_d[2] */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0B48) = 0x40001; /* vin1a_d[3] */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0B4C) = 0x40001; /* vin1a_d[4] */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0B50) = 0x40001; /* vin1a_d[5] */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0B54) = 0x40001; /* vin1a_d[6] */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0B58) = 0x40080; /* vin1a_d[8] */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0B5C) = 0x40080; /* vin1a_d[9] */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0B60) = 0x40080; /* vin1a_d[10] */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0B64) = 0x40080; /* vin1a_d[11] */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0B68) = 0x40080; /* vin1a_d[12] */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0B6C) = 0x40080; /* vin1a_d[13] */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0B70) = 0x40080; /* vin1a_d[14] */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0B74) = 0x40001; /* vin1a_d[15] */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0B78) = 0x40001; /* vin1a_d[16] */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0B7C) = 0x40001; /* vin1a_d[17] */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0B80) = 0x40001; /* vin1a_d[18] */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0B84) = 0x40001; /* vin1a_d[19] */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0B88) = 0x40001; /* vin1a_d[20] */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0B8C) = 0x60080; /* vin1a_d[21] */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0B90) = 0x60001; /* vin1a_d[22] */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0B94) = 0x40001; /* vin1a_d[23] */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0B98) = 0x60001; /* vin1a_d[7] */

    /* Function 2 */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0BA8) = 0x40001; /* vin1a_d[0] */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0BAC) = 0x40001; /* vin1a_d[1] */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0BB0) = 0x40001; /* vin1a_d[2] */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0BB4) = 0x1;     /* vin1a_d[3] */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0BB8) = 0x1;     /* vin1a_d[4] */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0BBC) = 0x1;     /* vin1a_d[5] */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0BC0) = 0x40001; /* vin1a_d[6] */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0BC4) = 0x40001; /* vin1a_d[7] */

#if 0
    /* I2c2 configuration Function 6 */
#if defined(TI_814X_BUILD)	
	REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0924) = 0xE0020; /* i2c2_scl_mux0 */
	REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0928) = 0xE0020; /* i2c2_sda_mux0 */
#endif
#endif

#if defined(TI_8107_BUILD)
	#if defined IMGS_MICRON_MT9M034
	REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0924) = 0xE0020; /* i2c2_scl_mux0 */
	REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0928) = 0xE0020; /* i2c2_sda_mux0 */
// 	REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A18) = 0xE0020;
// 	REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A1C) = 0xE0020;
	#endif
#endif

    /* TODO Find proper place for this Set the divider for the SYSCLK10 */
    *(UInt32 *) 0x48180324 = 3;
#ifndef IMGS_OMNIVISION_OV7740	
    /* Iss specific Input PIN MUX settings */
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A6C) = 0x50002;
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A70) = 0x50002;
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A74) = 0x50002;
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A78) = 0x50002;
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A7C) = 0x50002;
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A80) = 0x50002;
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A84) = 0x50002;
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A88) = 0x50002;
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A8C) = 0x50002;
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A90) = 0x50002;
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A94) = 0x50002;
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A98) = 0x50002;
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A9C) = 0x50002;
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0AA0) = 0x50002;
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0AA4) = 0x50002;
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0AA8) = 0x50002;
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0AAC) = 0x50002;
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0AB0) = 0x50002;
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0AB4) = 0x50002;
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0AB8) = 0x50002;

    /* setup I2C2 pin mux */
#ifdef IMGS_MICRON_MT9J003	
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0924) = 0x00020;
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0928) = 0x00020;
#endif
#ifdef IMGS_MICRON_MT9P031	
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0AAC ) = 0x00060002;    // CAM_HSYNC        PINCNTL172[1]
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0AB0 ) = 0x00060002;    // CAM_VSYNC        PINCNTL173[1]
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0AB8 ) = 0x00060002;    // CAM_PCLK         PINCNTL175[1]
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A58 ) = 0x00060020;    // CAM_WEn          PINCNTL151[5] cam_de_mux1
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A60 ) = 0x00060080;    // gpio2[18]        PINCNTL153[7] // 0x00060080   CAM_RST          PINCNTL153[5]
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A64 ) = 0x00060020;    // CAM_STROBE       PINCNTL154[5]
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A68 ) = 0x00060020;    // CAM_SHTR         PINCNTL155[5]
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0AA8 ) = 0x00060002;    // CAM_D0           PINCNTL171[1]
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0AA4 ) = 0x00060002;    // CAM_D1           PINCNTL170[1]
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0AA0 ) = 0x00060002;    // CAM_D2           PINCNTL169[1]
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A9C ) = 0x00060002;    // CAM_D3           PINCNTL168[1]
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A98 ) = 0x00060002;    // CAM_D4           PINCNTL167[1]
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A94 ) = 0x00060002;    // CAM_D5           PINCNTL166[1]
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A90 ) = 0x00060002;    // CAM_D6           PINCNTL165[1]
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A8C ) = 0x00060002;    // CAM_D7           PINCNTL164[1]
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A6C ) = 0x00060002;    // CAM_D8           PINCNTL156[1]
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A70 ) = 0x00060002;    // CAM_D9           PINCNTL157[1]
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A74 ) = 0x00060002;    // CAM_D10          PINCNTL158[1]
    REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A78 ) = 0x00060002;    // CAM_D11          PINCNTL159[1]
#endif	
#endif	
#endif
    return (FVID2_SOK);
}

/* ===================================================================
 *  @func     Iss_platformTI814xGetCpuRev                                               
 *                                                                    
 *  @desc     Function does the following                             
 *                                                                    
 *  @modif    This function modifies the following structures         
 *                                                                    
 *  @inputs   This function takes the following inputs                
 *            <argument name>                                         
 *            Description of usage                                    
 *            <argument name>                                         
 *            Description of usage                                    
 *                                                                    
 *  @outputs  <argument name>                                         
 *            Description of usage                                    
 *                                                                    
 *  @return   Return value of this function if any                    
 *  ==================================================================
 */                                                                   
Iss_PlatformCpuRev Iss_platformTI814xGetCpuRev(void)
{
    UInt32 cpuId, cpuRev;

    Iss_PlatformCpuRev cpuRevEnum;

    /* Read CPU ID */
    cpuId = REG32(ISS_CTRL_MODULE_DEV_CFG_BASE_ADDR + 0x0000u);

    cpuRev = ((cpuId >> 28u) & 0x0Fu);
    switch (cpuRev)
    {
        case 0x0u:
            cpuRevEnum = ISS_PLATFORM_CPU_REV_1_0;
            break;

        case 0xCu:                                        /* Certain intial
                                                            * sample of PG
                                                            * 2.1 has C but
                                                            * the production
                                                            * samples should
                                                            * read out 3 */
        case 0x3u:
            cpuRevEnum = ISS_PLATFORM_CPU_REV_2_1;
            break;

        default:
            // cpuRevEnum = ISS_PLATFORM_CPU_REV_UNKNOWN;
            Vps_printf
                (" PLATFORM: UNKNOWN CPU detected, defaulting to ISS_PLATFORM_CPU_REV_2_1\n");
            cpuRevEnum = ISS_PLATFORM_CPU_REV_2_1;
            break;
    }

    return (cpuRevEnum);
}

/* ===================================================================
 *  @func     Iss_platformTI814xGetBaseBoardRev                                               
 *                                                                    
 *  @desc     Function does the following                             
 *                                                                    
 *  @modif    This function modifies the following structures         
 *                                                                    
 *  @inputs   This function takes the following inputs                
 *            <argument name>                                         
 *            Description of usage                                    
 *            <argument name>                                         
 *            Description of usage                                    
 *                                                                    
 *  @outputs  <argument name>                                         
 *            Description of usage                                    
 *                                                                    
 *  @return   Return value of this function if any                    
 *  ==================================================================
 */                                                                   
Iss_PlatformBoardRev Iss_platformTI814xGetBaseBoardRev(void)
{
    /* Only one revision of board till date */
    return (ISS_PLATFORM_BOARD_REV_A);
}

/* ===================================================================
 *  @func     Iss_platformTI814xGetDcBoardRev                                               
 *                                                                    
 *  @desc     Function does the following                             
 *                                                                    
 *  @modif    This function modifies the following structures         
 *                                                                    
 *  @inputs   This function takes the following inputs                
 *            <argument name>                                         
 *            Description of usage                                    
 *            <argument name>                                         
 *            Description of usage                                    
 *                                                                    
 *  @outputs  <argument name>                                         
 *            Description of usage                                    
 *                                                                    
 *  @return   Return value of this function if any                    
 *  ==================================================================
 */                                                                   
Iss_PlatformBoardRev Iss_platformTI814xGetDcBoardRev(void)
{
    /* Only one revision of board till date */
    return (ISS_PLATFORM_BOARD_REV_A);
}

/* ===================================================================
 *  @func     Iss_platformTI814xSelectVideoDecoder                                               
 *                                                                    
 *  @desc     Function does the following                             
 *                                                                    
 *  @modif    This function modifies the following structures         
 *                                                                    
 *  @inputs   This function takes the following inputs                
 *            <argument name>                                         
 *            Description of usage                                    
 *            <argument name>                                         
 *            Description of usage                                    
 *                                                                    
 *  @outputs  <argument name>                                         
 *            Description of usage                                    
 *                                                                    
 *  @return   Return value of this function if any                    
 *  ==================================================================
 */                                                                   
/* ===================================================================
 *  @func     Iss_platformTI814xSelectSensor                                               
 *                                                                    
 *  @desc     Function does the following                             
 *                                                                    
 *  @modif    This function modifies the following structures         
 *                                                                    
 *  @inputs   This function takes the following inputs                
 *            <argument name>                                         
 *            Description of usage                                    
 *            <argument name>                                         
 *            Description of usage                                    
 *                                                                    
 *  @outputs  <argument name>                                         
 *            Description of usage                                    
 *                                                                    
 *  @return   Return value of this function if any                    
 *  ==================================================================
 */                                                                   
Int32 Iss_platformTI814xSelectSensor(UInt32 vidDecId, UInt32 vipInstId)
{
    UInt32 i2cInstId = Iss_platformTI814xGetI2cInstId();

    UInt32 i2cDevAddr;

    UInt8 regValue[2];

    Iss_PlatformBoardId boardId;

    Int32 status = FVID2_SOK;

    boardId = Iss_platformGetBoardId();

    /* In TI814X, GMII1 and SiL9135A are muxed on the VC board. */
    if (boardId == ISS_PLATFORM_BOARD_VCAM)
    {
        i2cDevAddr = gTi814xBoardVer.vcIoExpAddr;
        regValue[0] = 0xEF;
        regValue[1] = 0xFF;
    }

    status = Iss_deviceRawWrite8(i2cInstId, i2cDevAddr, regValue, 2);
    return status;
}

0 Akash Gajjar over 8 years ago in reply to Akash Gajjar

Intellectual 510 points

Hi Dwarakesh,

Is there any update on this issue.

Regards,
Akash

0 Dwarakesh Radhakrishnan over 8 years ago in reply to Akash Gajjar

Guru 13620 points

Hi Akash,

I had plans of checking few registers. Will send them today. Were you able to probe and check the clock and the values being fine before and after firmware load ?

0 Akash Gajjar over 8 years ago in reply to Dwarakesh Radhakrishnan

Intellectual 510 points

HI Dwarakesh,

yes, i'll do that.

Regards,
Akash

0 Akash Gajjar over 8 years ago in reply to Akash Gajjar

Intellectual 510 points

Hi Dwarakesh,

I've done changes in vps_platformTI814x.c, disabling pinmuxing as well as bypassing interrupt initialization
for i2c bus 2.

// REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A18) = 0x0; /* vin0_de0_mux0 - DeSelect input */
// REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A1C) = 0x50001; /* vin0_fld0_mux0 */

along with changes in Vps_platformTI814xDeviceInit() with bypassing interrupt initialization
for i2c bus 2.
/*
* Initialize I2C instances
*/
for (i2cCnt = 0; i2cCnt < VPS_DEVICE_I2C_INST_ID_MAX; i2cCnt++)
{
deviceInitPrm.i2cRegs[i2cCnt] = (Ptr)(i2cRegs[i2cCnt]);
deviceInitPrm.i2cClkKHz[i2cCnt] = VPS_DEVICE_I2C_INST_NOT_USED;
if (2 == i2cCnt)
continue;
deviceInitPrm.i2cIntNum[i2cCnt] = i2cInt[i2cCnt];
}
same in iss_platformTI814x.c, disabled pinmuxing along with bypassing interrupt initialization
for i2c bus 2.

// REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A18) = 0xE0001; /* vin0_de0_mux0 -
// * DeSelect input */
// REG32(CSL_TI814x_CTRL_MODULE_BASE + 0x0A1C) = 0xE0001; /* vin0_fld0_mux0 */

and

for (i2cCnt = 0; i2cCnt < ISS_DEVICE_I2C_INST_ID_MAX; i2cCnt++)
{
deviceInitPrm.i2cRegs[i2cCnt] = (Ptr) (i2cRegs[i2cCnt]);
deviceInitPrm.i2cClkKHz[i2cCnt] = VPS_DEVICE_I2C_INST_NOT_USED;
if (2 == i2cCnt)
continue;
deviceInitPrm.i2cIntNum[i2cCnt] = i2cInt[i2cCnt];
}
deviceInitPrm.isI2cInitReq = initPrms->isI2cInitReq;

disabling interrupt initialization in both code results that i am able to access devices connected on i2c bus 2,
but camera module connected on i2c bus 0 is not working.

Regards,
Akash

0 Dwarakesh Radhakrishnan over 8 years ago in reply to Akash Gajjar

Guru 13620 points

Hi Akash,

that seems pretty strange. I2c1 and I2c2 interrupts are shared. But not i2c0 and i2c2.

0 Akash Gajjar over 8 years ago in reply to Dwarakesh Radhakrishnan

Intellectual 510 points

Hi Dwarakesh,

in my recent activity i changed crossbar mapping for i2c2 but no success,
what seems to be cause for this behavior.

Regards,
Akash

0 Dwarakesh Radhakrishnan over 8 years ago in reply to Akash Gajjar

Guru 13620 points

Hi Akash,

Were you able to make progress ? Sorry, couldn't find time to reply to you.

0 Akash Gajjar over 8 years ago in reply to Dwarakesh Radhakrishnan

Intellectual 510 points

Hi Dwarakesh,

Thanks for your reply, i am stucking at the same point.

Regards,

Akash

0 Dwarakesh Radhakrishnan over 8 years ago in reply to Akash Gajjar

Guru 13620 points

Hi Akash,

Were you able to probe via Osciloscope ? How did you change the cross bar value ?

0 suresh kanzariya1 over 8 years ago in reply to Dwarakesh Radhakrishnan

Intellectual 270 points

Hello Dwarakesh,

Akash has already explain the scenario. I just repeat the problem in very short.

Basically we have connected our sensor on I2C0 than I2C2 of IPNC RDK. For the same we modify the hdvpss and iss code to get the correct data from the sensor. We have connected RTC and temp. sensor on I2C2, both the device is working fine without firmware load, when we load the M3 core firmware, both the device stops working. For ex. when firmware is running and If I apply 'hwclock -w' command it gives below error.

hwclock: RTC_SET_TIME: Connection timed out
omap_i2c omap_i2c.3: controller timed out
rtc-ds1307 3-0068: write error -110

If I apply same command from userspace (without firmware load) both the device is working fine and I am able to get/set value from the devices.

Now as you mentioned about the pin muxing in hdvpss and iss code for the same I comment out below line from file Source/ti_tools/hdvpss_01_00_01_37/packages/ti/psp/platforms/ti814x/src/vps_platformTI814x.c

#define CONFIG_PIN_MUX
#define CONFIG_INT_MUX

in iss, file Source/ti_tools/iss_03_80_00_00/packages/ti/psp/platforms/ti814x/src/iss_platformTI814x.c I define the macro 'CBB_PLATFORM' so that it won't overwrite the pin mux

But still I am not able to access RTC on I2C2 bus.

Above changes are straight forware and overwrite pin mux than uboot and kernel, so I changed it but still it is not working.

Default IPNC RDK implementation has sensor connected on I2C2 bus, so I believe that somewhere it is still override the functionality. It will be great if you can help us in deriving the solution.

Without firmware load it is working fine so I can;t doubt on uboot/kernel, but with firmware it is not working so firmware code is causing problem on I2C2 bus.

Also Akash has already share the code for both the file and log, Please let us know if you require further information.

Fast response is highly appreciated.

Thanks & Regards,

Suresh

0 suresh kanzariya1 over 8 years ago in reply to suresh kanzariya1

Intellectual 270 points

I have inserted print 'vps_platformTI814x.c' of hdvpss and found 'platformTI814xGetVidDecI2cAddr' function being called 4 times, we don't have any daughter card on board also we are not using tvp5158 video decoder.

[m3vpss ] initPrms.isI2cInitReq = 1
[m3vpss ] initPrms.isI2cInitReq = 1
[m3vpss ] PLATFORM: Vps_platformTI814xSetVencPixClk
[m3vpss ] PLATFORM: Vps_platformPllCfg
[m3vpss ] PLATFORM: Vps_platformTI814xSetVencPixClk
[m3vpss ] PLATFORM: Vps_platformPllCfg
[m3vpss ] PLATFORM: Vps_platformTI814xDeviceInit
[m3vpss ] PLATFORM: Vps_platformTI814xGetVidDecI2cAddr
[m3vpss ] PLATFORM: Vps_platformTI814xGetVidDecI2cAddr
[m3vpss ] PLATFORM: Vps_platformTI814xGetVidDecI2cAddr
[m3vpss ] PLATFORM: Vps_platformTI814xGetVidDecI2cAddr
[m3vpss ] Vps_deviceInit Daughter card not detected/connected!
[m3vpss ] I2C0: Passed for address 0x10 !!!

Let me know if this or something else is causing issue with I2C2.

-Suresh

0 Dwarakesh Radhakrishnan over 8 years ago in reply to suresh kanzariya1

Guru 13620 points

Hi Suresh,

Can you try the following devmem2 before and after the module is loaded ?

#devmem2 0x4819c010

#devmem2 0x4819c02c

#devmem2 0x4819c038

#devmem2 0x4819c03c

#devmem2 0x4819c094

#devmem2 0x4819c0a4

#devmem2 0x4819c0a8

#devmem2 0x4819c0ac

#devmem2 0x4819c0b0

These are few i2c2 controller registers. Please send me the output of these, before and after the firmware is loaded.

0 Akash Gajjar over 8 years ago in reply to Dwarakesh Radhakrishnan

Intellectual 510 points

Hi Dwarkesh,

Here's the result of I2C address registers.

##########################################
before firmware loading
##########################################
devmem 0x4819c010 0x00000015
devmem 0x4819c02c 0x0000001E
devmem 0x4819c038 0x00000000
devmem 0x4819c03c 0x00000000
devmem 0x4819c094 0x00000000
devmem 0x4819c0a4 0x00008000
devmem 0x4819c0a8 0x00000000
devmem 0x4819c0ac 0x00000077
devmem 0x4819c0b0 0x000000FF
##########################################
after firmware loading
##########################################
devmem 0x4819c010 0x00000015
devmem 0x4819c02c 0x0000001E
devmem 0x4819c038 0x00000000
devmem 0x4819c03c 0x00000000
devmem 0x4819c094 0x00000000
devmem 0x4819c0a4 0x00008000
devmem 0x4819c0a8 0x00000000
devmem 0x4819c0ac 0x00000077
devmem 0x4819c0b0 0x000000FF
##########################################

Here we have also one observation with i2cdetect utility on i2c-2 slave address
that it changes value of i2c slave register 0x4819c0ac after and before camera firmware loading
with customized code which is already discussed by suresh.

[root@root ~]# devmem 0x4819c0ac
0x00000068
[root@root ~]#
[root@root ~]#
[root@root ~]# i2cdetect -y -r 3
0 1 2 3 4 5 6 7 8 9 a b c d e f
00: -- -- -- -- -- -- -- -- -- -- -- -- --
10: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
20: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
30: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
40: -- -- -- -- -- -- -- -- -- -- -- -- UU -- -- --
50: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
60: -- -- -- -- -- -- -- -- UU -- -- -- -- -- -- --
70: -- -- -- -- -- -- -- --
[root@root ~]#
[root@root ~]# devmem 0x4819c0ac
0x00000077
[root@root ~]#
[root@root ~]#

After Camera firmware loading

root@root ~]#
[root@root ~]# devmem 0x4819c0ac
0x00000077
[root@root ~]#
[root@root ~]#
[root@ ~]# i2cdetect -y -r 3
0 1 2 3 4 5 6 7 8 9 a b c d e f
-- [ 881.370000] omap_i2c omap_i2c.3: controller timed out
-- [ 882.370000] omap_i2c omap_i2c.3: controller timed out
-- [ 883.370000] omap_i2c omap_i2c.3: controller timed out
-- [ 884.370000] omap_i2c omap_i2c.3: controller timed out
-- [ 885.370000] omap_i2c omap_i2c.3: controller timed out
-- ^C[ 886.370000] omap_i2c omap_i2c.3: controller timed out

[root@root ~]#
[root@root ~]#
[root@root ~]# devmem 0x4819c0ac
0x00000004
[root@root ~]# i2cdetect -y -r 3
0 1 2 3 4 5 6 7 8 9 a b c d e f
-- [ 881.370000] omap_i2c omap_i2c.3: controller timed out
-- [ 882.370000] omap_i2c omap_i2c.3: controller timed out
-- [ 883.370000] omap_i2c omap_i2c.3: controller timed out
-- [ 884.370000] omap_i2c omap_i2c.3: controller timed out
-- [ 885.370000] omap_i2c omap_i2c.3: controller timed out
-- ^C[ 886.370000] omap_i2c omap_i2c.3: controller timed out

[root@root ~]#
[root@root ~]# devmem 0x4819c0ac
0x0000000A
[root@root ~]#
[root@root ~]#

Regards,
Akash

0 Dwarakesh Radhakrishnan over 8 years ago in reply to Akash Gajjar

Guru 13620 points

Hi Akash,

1. May I know why in the initial dump, the slave address has not changed ?

2. Customized code means the pinmuxing changes ?

3. Can you make your RTC i2c module and insert it after firmware load ?

3. I will check where slave address is overwritten with 0x0A

0 Akash Gajjar over 8 years ago in reply to Dwarakesh Radhakrishnan

Intellectual 510 points

Hi Dwarkesh,

1. initially we have not used i2cdetect command to detect device so the slave address is not changed.

2. yes, Customized code means the code which has pinmuxing changes

3. when i insert rtc driver, it throws below logs

[ 182.030000] omap_i2c omap_i2c.3: controller timed out
[ 182.030000] rtc-ds1307: probe of 3-0068 failed with error -5

Regards,
Akash

0 Dwarakesh Radhakrishnan over 8 years ago in reply to Akash Gajjar

Guru 13620 points

Hi Akash,

Ok got it. i2cdetect tries to probe slave addresses from 0x00 to 0xFF, and hence you see different slave addresses depending on when you gave (CTRL+C). So no need to worry about the changing of slave addresses.

Trying the order, clarifies few things. There seems to be set of registers which are over-written in only firmware code and not in Linux(A8), which is affecting irrespective of the order of loading.

These changes are specific to cross bar configuration and with respect to i2c2. These configurations are only M3 specific. If all the registers are fine, it could time out because interrupt is not getting properly configured.

Can you try the following ?

In ti_tools/hdvpss_01_00_01_37/packages/ti/psp/cslr/soc_TI814x.h

Can you make the following:

#define CSL_INTC_EVENTID_I2CINT2 (00u)

Also in ti_tools/iss_03_80_00_00/packages/ti/psp/cslr/soc_TI814x.h

Can you make the following

#define CSL_INTC_EVENTID_I2CINT2 (00u)

Iss_platformTI814xSetIntMux() -> comment out this function call(inside function Iss_platformTI814xInit()) in file ti_tools/iss_03_80_00_00/packages/ti/psp/platforms/ti814x/src/iss_platformTI814x.c

Vps_platformTI814xSetIntMux() -> comment out this function call(inside function Vps_platformTI814xInit()) in file ti_tools/hdvpss_01_00_01_37/packages/ti/psp/platforms/ti814x/src/vps_platformTI814x.c

0 Akash Gajjar over 8 years ago in reply to Dwarakesh Radhakrishnan

Intellectual 510 points

Hi Dwarkesh,

As per your saying i've changed crossbar interrupt of i2c 2 in both the file you've mentioned
And also disabled vpss/iss_platformTI814xSetIntMux() in vpss and iss platform files.
Still I am facing controller timed out issue and not able to get access of devices on i2c 2 bus after firmware loading.

Regards,
Akash

0 Dwarakesh Radhakrishnan over 8 years ago in reply to Akash Gajjar

Guru 13620 points

Hi Akash,

I will send all possible registers dump requirement shortly. Hope you tried the above along with the pinmux settings shared before.

0 Akash Gajjar over 8 years ago in reply to Dwarakesh Radhakrishnan

Intellectual 510 points

Hi Dwarkesh,

Yes, the result shared is already tried with the pinmux settings which is shared before.

Regards
Akash

0 Akash Gajjar over 8 years ago in reply to Akash Gajjar

Intellectual 510 points

Hi Dwarkesh,

Is there any update on this issue.

Regards,

Akash

0 Dwarakesh Radhakrishnan over 8 years ago in reply to Akash Gajjar

Guru 13620 points

Hi Akash,

I would like you to do ioremap of all these registers in the file drivers/i2c/busses/i2c-omap.c, when you get the "controller timed out" error in function omap_i2c_xfer_msg.

example ioremap:

if (time_after(jiffies, delay)) {

int *reg1;

reg1 = (int *)ioremap(0x48140f64, 0x04);

printk("reg: %x val: %x\n", 0x48140f64, *reg1);

}

For the following registers:

1. 0x48140f64

2. 0x48140A1C

3. 0x48140A18

4. 0x48181564

5.0x48181400

6. 0x48180324

7. 0x48140BA8

8. 0x48140924

9. 0x48140928

10. 0x48140A6C

11. 0x48140B8C

12. 0x48140B90

13. 0x4819c010

14. 0x4819c02c

15. 0x4819c038

16. 0x4819c03c

17. 0x4819c094

18. 0x4819c0a4

19. 0x4819c0a8

20. 0x4819c0ac

21. 0x4819c0b0

22. 0x4819c0b4

23. 0x4819c0b8

Also check this in the success case also(before loading the firmware), when timed out doesn't happen. Put it outside above if condition also. Please share the values.

The timedout comes because the A8 has asked for i2c controller to generate start bit, but the controller is not able to set the start bit and respond back. Have you physically probed the i2c lines ?

Also what are all other connections other than i2c2 sclk and i2c2 sda that are going to RTC ? Have you checked their state too by probing ?

0 suresh kanzariya1 over 7 years ago in reply to Dwarakesh Radhakrishnan

Intellectual 270 points

Hi Dwarkesh,

We are able to resolve the issue by commenting out below two line in sensor file. Source/ti_tools/iss_03_80_00_00/packages/ti/psp/devices/ar0331/src/issdrv_ar0331Api.c

PINCNTL74
PINCNTL75

Also previous we had disable pin mux for I2C2 in hdvpss and iss, by applying above changes, I2C2 issue resolve. Now we are able to get/set I2C2 device when m3vpss firmware is running.

Thank You for your time and support.

Regards,
Suresh

0 Dwarakesh Radhakrishnan over 7 years ago in reply to suresh kanzariya1

Guru 13620 points

Hi Suresh,

Glad to know that.

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