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DM8148. Encoder links start reject frames after some time

Hello TI' teams.
In additional for capture video from VIP ports, my usecase perfrom screen capture from SC_WB5 device (capture processed video with overlayed graphics), perform encode and local record or/and stream:

screen capture -> NSF (color convert) -> Duplicate and Merge (produce 2 channels from single frame) -> HDVPSS IpcOut -> VideoIpcIn -> VideoEncode (H264/30fps and MJPEG/4fps) -> VideoIpcOut -> HostIpcIn -...-> stream/video_record/snapshot.

Use-case works fine, but after some time (this problem occured randomally: may after 5...10 min or may after 1..2 or even after 5...6 hours)
encoder start reject all frames from input queue. And only board HW-reset restore the functionality.
After quick browsing on e2e forum I found very similar issue here:

e2e.ti.com/.../1266842

As in above post I tried to change file "/dvr_rdk/mcfw/src_bios6/links_m3video/codec_utils/src/iresman_hdvicp2_fwif.c" as
Badri recommend:

HDVICP_Wait

to

UTILS_assert (Semaphore_pend(_HDVICP2_context[iresHandle->id].semHandle,
                        1000) == TRUE)

And after "make sys_all" and board reboot saw that really this assertion occured - HDVICP is hung. No warnings or errors before this assert.
As desribes above, this assertion occured randomally, may after short time (5..10 min) or may after a long time running, after 5...6 hours.

[m3video]  6344872: Assertion @ Line: 451 in links_m3video/codec_utils/src/iresman_hdvicp2_fwif.c: (res = Semaphore_pend(_HDVICP2_context[iresHandle->id].semHandle, 1000)) == TRUE : failed !!!


Please let me knows:
1) what is reason for this assertion and how I can fix the issue?
2) Even assertion occured (HDVICP Semaphore in timeout) - any way for recover and restore system functionality without HW-reboot?

I'm works with DM8148 (silicon revision 3.0, industrial temperarue range) and latest version of dvr-rdk 04.01 from ud-works.

System PLL's:
L3 clk         : 220MHz
IVA clk        : 306MHz
ISS clk        : 400MHz
DSP clk        : 600MHz
DSS clk        : 200MHz
ARM clk        : 720MHz
DDR clk        : 400MHz


DDR SW leveling passed successfully, DDR memory test passed to.
Other system componnets - HDVPSS, DSP, ARM/A8, etc.. work fine and stable.