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DM8127 2G DDR relace 512M DDR

Vincent wu
Prodigy 60 points

Hi

DM8127 IPNC_RDK 3.8 Run well with DDR 512MB(MT41K64M16). when chang it with DDR 2GB(MT41K256M16),U-boot can run well,But can not receive any encode videos.I modify the u-boot about DDR initialization.

u-boot/arch/arm/include/asm/arch-ti81xx/ddr_defs_ti814x.h

#define DDR3_EMIF_READ_LATENCY             0x0017020C

#define DDR3_EMIF_TIME1                              0x1557B9A5

#define DDR3_EMIF_TIM2                                0x4C5F7FEB

#define DDR3_EMIF_TIM3                                 0x00000578

#define DDR3_EMIF_REF_CTRL                       0x10000578

#define DDR3_EMIF_SDRAM_CONFIG            0x61C33B32

#define PG2_1_DMM_LISA_MAP_0                 0x0

#define PG2_1_DMM_LISA_MAP_1                 0x0

#define PG2_1_DMM_LISA_MAP_2                 0x80640300

#define PG2_1_DMM_LISA_MAP_0                 0xc0640320

I never modify bld file,so why did it happened(Can not receive encode video)

  • 0
    Intellectual 530 points

    Hi,

    I forwarded this question to the experts. They will reply to this thread.

    Meanwhile you can check these threads:
    https://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/716/t/251597

    https://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/716/p/433427/1551934

    https://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/716/t/357908


    Thank you !!!

    BR
    -Kaushal

  • 0
    TI__Guru**** 170625 points
    Hi user4186971,

    Have you made DDR3 software leveling? I would also suggest to test the DDR3 with the u-boot mtest:

    processors.wiki.ti.com/.../DM816x_C6A816x_AM389x_DDR3_Init

    Regards,
    Pavel
  • 0 in reply to Pavel Botev
    TI__Mastermind 37500 points

    Hello,

    I see you have included the DDR registers,   I assume you have followed the DM813x/dm8148 DDR configuration, for your specific DDR clock rate

    and OPP mode.   There is a new DM8127 DDR configuration wiki, processors.wiki.ti.com/.../DM8127_DDR_Config_Resources

    Once you have done the configuration, based on the DDR3 single edge clock (400,533), topology (16 or 32bits), and DDR3 device parameters, you would update the registers (as you reported).

    The second part of this as Patel has suggested, is to run the DM813x Software levelling for byte or word levelling.  There is a GEL file and CCS project to search the DQS delay, and DDR Clock polarity values.

    After this as Patel suggests, a complete DDR test should be done.

    In your DDR3 mapping if there are page registers, maybe these need to be evaluated since your DDR3 size has increased.

    Regards,

    Joe Quintal

  • 0 in reply to Radio-Joe
    Prodigy 60 points
    Hi Joe,
    I have done Byte Software Leveling.And I test the mtest DDR3 with the u-boot mtest:
    mtest 0x81000000 0xA0000000 0xaa55aa55 3
    Pattern AA55AA54 Writing... Reading...Tested 3 iteration(s) with 0 errors.
    mtest 0xA0000000 0xC0000000 0xaa55aa55 3
    Pattern AA55AA54 Writing... Reading...Tested 3 iteration(s) with 0 errors.
    Does it mean DDR is ok?
    Sometimes the system can get few encode streams,And Sometimes can get none.
    It is run well with DDR MT64M16*4(512M 10 columns,8 banks,12 rows).Fail with MT25616*4(2G 10 column,8 banks,15 rows).what is diffrence between them.What should I modify if I want to use 2G DDR.
    Thanks Vicent
  • 0 in reply to Pavel Botev
    Prodigy 60 points
    Hi Pavel,
    I have done Byte Software Leveling.And I test the mtest DDR3 with the u-boot mtest:
    mtest 0x81000000 0xA0000000 0xaa55aa55 3
    Pattern AA55AA54 Writing... Reading...Tested 3 iteration(s) with 0 errors.
    mtest 0xA0000000 0xC0000000 0xaa55aa55 3
    Pattern AA55AA54 Writing... Reading...Tested 3 iteration(s) with 0 errors.
    Does it mean DDR is ok?
    Sometimes the system can get few encode streams,And Sometimes can get none.
    It is run well with DDR MT64M16*4(512M 10 columns,8 banks,12 rows).Fail with MT25616*4(2G 10 column,8 banks,15 rows).what is diffrence between them.What should I modify if I want to use 2G DDR.
    Thanks Vicent
  • 0 in reply to Vincent wu
    TI__Guru**** 170625 points

    Hi Vicent,

    user4186971 said:
    I test the mtest DDR3 with the u-boot mtest:
    mtest 0x81000000 0xA0000000 0xaa55aa55 3
    Pattern AA55AA54 Writing... Reading...Tested 3 iteration(s) with 0 errors.
    mtest 0xA0000000 0xC0000000 0xaa55aa55 3
    Pattern AA55AA54 Writing... Reading...Tested 3 iteration(s) with 0 errors.
    Does it mean DDR is ok?

    You skip to test the addresses between 0x80000000 and 0x81000000. You might test these also, but run the test from 0x80800000 to not overwrite u-boot.

    Also there is more intensive DDR stress test, but you need JTAG+CCS for it. See the below e2e threads for more info:

    user4186971 said:
    Sometimes the system can get few encode streams,And Sometimes can get none.

    Do you have the same linux kernel and application running on both boards (512M and 2GB)? Or you made some changes?

    Regards,
    Pavel

  • 0 in reply to Pavel Botev
    TI__Guru**** 170625 points

    Note also that in DVR RDK we have config_2G.bld file that should be used, for IPNC we might have something similar. Also the boot arguments are important, please share your boot argument for review. See if the below e2e threads will be in help:

    e2e.ti.com/.../1556617
    e2e.ti.com/.../250616
    e2e.ti.com/.../1203600
    e2e.ti.com/.../1262237
    e2e.ti.com/.../781818

    Regards,
    Pavel

  • 0 in reply to Pavel Botev
    Prodigy 60 points
    Hi Pavel:
    Thanks for your answer. I do have the same linux kernel and application running on both boards(512M and 2GB).I just modify u-boot about DDR parts.
    Regards,
    Vincent
  • 0 in reply to Pavel Botev
    Prodigy 60 points
    Hi Pavel:
    My bootargs is :bootargs=console==ttyO0,115200n8 root/dev/nfs rw mem=80 vram=4M notifyk.vpssm3_sva=0xBFD00000 nfsroot=192.168.1.61:/opt/APPRO_DM8127/Source/ipnc_rdk/target/filesys,nolock,eth=00:0C:A0:07:66 ip=192.168.1.224 cmemk.phys_start=0x85000000 cmemk.pys_end=0x89000000 cmemk.allowVverlap=1 earlyprintk'
    It is same as in 512M DDR.Is it a problem?
  • 0 in reply to Vincent wu
    TI__Guru**** 170625 points

    Vincent wu said:
    I do have the same linux kernel and application running on both boards(512M and 2GB).I just modify u-boot about DDR parts.
    Regards,

    Then I will suggest you to test the DDR with mtest, but the whole 2GB range, from 0x80800000 to 0xFFFFFFFF. You can also test DDR with the JTAG/CCS/EDMA test. Try also to access/read/write various DDR locations (in the range 0x80000000 to 0xFFFFFFFF) from user space with devmem2 tool or mmap function.

    If all the DDR tests run fine (which means DDR is correct), then you should focus on boot arguments and config/build file adjustment.

    Regards,
    Pavel

  • 0 in reply to Vincent wu
    TI__Guru**** 170625 points

    Vincent wu said:
    My bootargs is :bootargs=console==ttyO0,115200n8 root/dev/nfs rw mem=80 vram=4M notifyk.vpssm3_sva=0xBFD00000 nfsroot=192.168.1.61:/opt/APPRO_DM8127/Source/ipnc_rdk/target/filesys,nolock,eth=00:0C:A0:07:66 ip=192.168.1.224 cmemk.phys_start=0x85000000 cmemk.pys_end=0x89000000 cmemk.allowVverlap=1 earlyprintk'
    It is same as in 512M DDR.Is it a problem?

    In EZSDK we have different boot arguments for 256M, 512M and 1G, see the below wiki page:

    In EZSDK 1GB DDR3, we have the below boot args:

    mem=364M@0x80000000 mem=320M@0x9FC00000 vmalloc=500M  notifyk.vpssm3_sva=0xBF900000

    You might try with these.

    Regards,
    Pavel

  • 0
    TI__Mastermind 37500 points

    Hello,

    In order to ensure that the DDR3 device, is configured, uboot is OK, and then you have performed DDR3 testing, please consider

    following the DDR3 configuration guideline - processors.wiki.ti.com/.../DM8127_DDR_Config_Resources

    following the DDR3 leveling, and DDR3 testing - processors.wiki.ti.com/.../TI814x-DDR3-Init-U-Boot

    following related E2E posts - e2e.ti.com/.../450176

    There are specific page size limits, you might consider using the existing size data transfers with the new memories, and then try to expand the size.

    Regards,

    Joe Quintal