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Problem about DM8148 boot logo on DVO2:DVO2 port is set to 720P60 and work well ,but no data output on DVO2.

Hi everyone,

    I`m working on DM8148 boot logo on DVO2 with 720P60 ..

    Now the dvo2 port of hdvpss is set to 720P60 and work well (tv can detecte 720p60  signal correctly).

    But there is no logo data on tv.  Just something like background data(black screen) is show on tv.

    I have no idea to debug on tihis problem.  Something wrong with grpx / vpdma setting ?  Can you give me some advise to debug ?  Thanks verymuch.

My logo data is loaded by tftp at uboot stage :   "tftp 0x82000000 car.bmp; "

start logo display at uboot stage :  " logo on 0x82000000 0xA0000000  0x81600000  10  60 "

                                                        (logo on     img_src     img_dst   vpdma_desc_dest disp_time disp_fps)

here is the code .

/**************************************************************/

static int do_boot_logo(cmd_tbl_t * cmdtp,int flag, int argc, char *argv[])
{
       uint32_t *firmware_addr;
       uint32_t *list_addr;
 uint32_t *payload_buffer;
 uint32_t size;
 uint32_t image_source = 0;
 uint32_t disp_time = 0;
 uint32_t disp_fps = 0;
 uint32_t image_dest = 0;
 uint32_t vpdma_desc_dest = 0;
 uint32_t paddr;
 /* check whether the arguments passed are correct  */
 if (argc < 2)
 {
   cmd_usage(cmdtp);
   return 1;
 }
 else if (strcmp(argv[1],"on") == 0)
 {
  if (argc != 7)
  {
   cmd_usage(cmdtp);
   return 1;
  }
  else
  {
   /* address in memory where bmp image is loaded */
   image_source = simple_strtoul(argv[2], NULL, 16);
   image_dest = simple_strtoul(argv[3], NULL, 16);
   vpdma_desc_dest = simple_strtoul(argv[4], NULL, 16);   /*  set by arguement --- 0x81600000 */
   disp_time = simple_strtoul(argv[5], NULL, 10);
   if(disp_time <= 0)
   {
    printf("Bootup splash display time is out of range, using default value(60s)\n");
    disp_time = DEFAULT_BOOT_LOGO_DISPLAY_TIME_IN_SECS;
   }
    disp_fps = simple_strtoul(argv[6], NULL, 10);
   if((disp_fps > 60) || (disp_fps < 1))
   {
    printf("Bootup splash display FPS entered is out of range, using default value(60fps)\n");
    disp_fps = DEFAULT_BOOT_LOGO_DISPLAY_FPS;
   }
  }
 }
 else if (strcmp(argv[1],"off") == 0)
 {
  vpdma_write32(VPDMA_LIST_ATTR, vpdma_read32(VPDMA_LIST_ATTR)
               | (VPDMA_LIST_NUMBER_HD<<24)  /* list number */
               | (1<<20)  /* stop bit for list  */
               );
  vpdma_write32(VPDMA_LIST_ATTR, vpdma_read32(VPDMA_LIST_ATTR)
               | (VPDMA_LIST_NUMBER_SD<<24)  /* list number */
               | (1<<20)  /* stop bit for list  */
               );
  return 0;
 }
 else
 {
  cmd_usage(cmdtp);
  return 1;
 }

 /* memory address for loading vpdma firmware and descriptors, payload */
 firmware_addr    = (uint32_t*)(vpdma_desc_dest+VPDMA_DESC_FIRMWARE_OFFSET);
 payload_buffer   = (uint32_t*)(vpdma_desc_dest+VPDMA_DESC_PAYLOAD_OFFSET);
 list_addr        = (uint32_t*)(vpdma_desc_dest+VPDMA_DESC_LIST_OFFSET);

 /* memory address for displaying the image formatted on the hdmi, the offset from the source location is 2 * WIDTH * HEIGHT */
 //image_dest = image_source + 3 * 3 * WIDTH * HEIGHT;

 if(image_source == image_dest)
 {
  printf("\nERROR: <logo_read_address> & <final_bmp address> cannot be same\n");
  return -1;
 }
 if((image_source == 0) || (image_dest == 0))
 {
  printf("\nERROR: <logo_read_address> or <final_bmp address> is NULL\n");
  return -1;
 }

 /* reading the bmp image from the specified location */
 if(ti810x_read_bmp_image(image_source,image_dest)  == -1)
 {
  printf("\nERROR: reading BMP image failed\n");
  return -1;
 }

 /********************[SET DVO2 PORT]*******************/
 if(ti810x_prcm_init()  == -1)
 {
#ifdef DEBUG_VPSS
  printf("\nERROR: ti810x_prcm_init failed\n");
#endif
  return -1;
 }
 
 /**Control module PINMUX settings**/
 //ti810x_control_pinmux();
 
 if(ti810x_pll_init()  == -1)
 {
#ifdef DEBUG_VPSS
  printf("\nERROR: ti810x_pll_init failed\n");
#endif
  return -1;
 }
 if(ti810x_vps_init()  == -1)
 {
#ifdef DEBUG_VPSS
  printf("\nERROR: ti810x_vps_init failed\n");
#endif
  return -1;
 }
 if(ti810x_set_mode(1,WIDTH,HEIGHT,argv[0]) == -1)
 {
#ifdef DEBUG_VPSS
  printf("\nERROR: ti810x_set_mode failed\n");
#endif
  return -1;
 }
 
#if 0    /* We don`t use SD port && won`t set i2c-device under hdvpss */
#ifdef CONFIG_I2C
 #ifndef CONFIG_TI814X
 configure_i2c_sd_thsfilter();
 #endif
  #ifndef CONFIG_UD8107_DVR
        configure_i2c_sii9022a();
        #endif
#endif

 //set the SD clocks Video0 PLL to fixed 54MHz
 ti810x_pll_configure_SD();
 //configure the SD Venc parameters, and set the work mode as normal mode
 ti810x_configure_SD_venc_registers(NORMAL_MODE);
#endif
 /********************[SET DVO2 PORT]*******************/

 if (ti810x_vpdma_load_firmware(firmware_addr) == -1)
 {
#ifdef DEBUG_VPSS
  printf("\nERROR: vpdma_load_firmware failed\n");
#endif
  return -1;
 }
   
       /* destination address */
 paddr = image_dest;

 /* HDMI->VGA Configuration Desc:GRPX0 */
 /* Allocate physical memory for MV data */
 size = ti810x_dispmgr_create_grpx_conf_descriptor(0, list_addr, payload_buffer,WIDTH,HEIGHT);
 ti810x_vpdma_send_list(list_addr, size, 0);//last param 0, list number hardcoded for HDMI->VGA
       /* wait for list complete interrupt */
 if(ti810x_dispmgr_wait_for_list_complete(1) == -1)
 {
#ifdef DEBUG_VPSS
  printf("\nERROR: wait for list complete FAILED!\n");
#endif
  return -1;
 }

 /* DVO2 Configuration Desc:GRPX1 */  /*Review[VIVB]*/
 /* Allocate physical memory for MV data */
 size = ti810x_dispmgr_create_grpx_conf_descriptor(1, list_addr + 0x40000, payload_buffer + 0x10,WIDTH,HEIGHT);
 ti810x_vpdma_send_list(list_addr + 0x40000, size, 1);//last param 1, list number hardcoded for DVO2
       /* wait for list complete interrupt */
 if(ti810x_dispmgr_wait_for_list_complete(1) == -1)
 {
#ifdef DEBUG_VPSS
  printf("\nERROR: wait for list complete FAILED!\n");
#endif
  return -1;
 }
#if 0    /* We don`t use SD port */
 //SD Configuration Desc:GRPX2
 size = ti810x_dispmgr_create_grpx_conf_descriptor(2, list_addr + 0x20000, payload_buffer + 0x8,WIDTH,HEIGHT);
 ti810x_vpdma_send_list(list_addr + 0x20000, size, 2);

       // wait for list complete interrupt
 if(ti810x_dispmgr_wait_for_list_complete(2) == -1)
 {
#ifdef DEBUG_VPSS
  printf("\nERROR: wait for list complete FAILED!\n");
#endif
  return -1;
 }
#endif
 // the frame start event must be properly set, or will cause screen scroll issue
 //set the frame start event of GRPX2 to 'channel active'

 vpdma_write32(VPDMA_GRPX0_DATA_CSTAT,0x00001C00);// Hardcoded: HDMI(+VGA)->GRPX0  (0x00001C00)(0x00000000)
 vpdma_write32(VPDMA_GRPX1_DATA_CSTAT,0x00001C00);// Hardcoded: DVO2->GRPX1        (0x00001C00)(0x00000400)
 //vpdma_write32(VPDMA_GRPX2_DATA_CSTAT,0x00000C00);// Hardcoded: SD->GRPX2
       //set the frame start event of GRPX1 to 'SD field ID changes'
 
       //DATA Descriptors for HDMI/VGA
 size = ti810x_dispmgr_setup_layers(list_addr,STRIDE,WIDTH,HEIGHT,disp_time,disp_fps,paddr);
 ti810x_vpdma_send_list(list_addr, size, VPDMA_LIST_NUMBER_HD); //list_no = 4

       //create data transfer descriptor for GRPX1
 //the list_addr has 0x10000 offset, because 2 GRPX share the same GRPX desc buffer = 4096 descs

 size = ti810x_dispmgr_setup_layers_DVO2(list_addr + 0x40000,STRIDE,WIDTH,HEIGHT,disp_time,disp_fps,paddr);
 ti810x_vpdma_send_list(list_addr + 0x40000, size, VPDMA_LIST_NUMBER_DVO2); //list_no = 3 

#if 0 /* We don`t use SD port */
 //DATA Descriptors for SD
 size = ti810x_dispmgr_setup_layers_SD(list_addr + 0x20000,STRIDE,WIDTH,HEIGHT,disp_time,disp_fps,paddr);
 ti810x_vpdma_send_list(list_addr + 0x20000, size, VPDMA_LIST_NUMBER_SD); //list_no = 5
#endif
 while (ti810x_dispmgr_wait_for_list_complete(1) == -1)
 {
  printf("ti810x_dispmgr_wait_for_list_complete is busy \n");
 };
 return 0;
}

/************************************************************************************************************************/

  • Hi


    Please change Width and height variables to 1280x720, they are used on below lines, please also change the stride variable to appropriate value.

    size = ti810x_dispmgr_create_grpx_conf_descriptor(1, list_addr + 0x40000, payload_buffer + 0x10,WIDTH,HEIGHT);
    size = ti810x_dispmgr_setup_layers_DVO2(list_addr + 0x40000,STRIDE,WIDTH,HEIGHT,disp_time,disp_fps,paddr);


    Rgds,
    Brijesh
  • Hi Brijesh
    I have change width and height variables to 1280 and 720 ,also the stride variable is set to 1280*3 . BUT I still can`t get any BMP img data on DVO2. It seem vpdma is not working properly, How can I check the vpdma ? Is there any way to check whether the BMP data is moved to GRPX1 ? Thanx
  • Hi,

    What do you see on the display? Is it still background color or some junk data?

    Rgds,
    Brijesh
  • Hi,

    Still background color . By the way,I have checked that BMP image data is loaded to DDR correctly, but still no data on display.
  • Hi,

    If it just shows background color, it means either grpx is not connected to the venc, or graphics list is not posted.. 

    It is not about the bmp, even if bmp is not right, it should show some junk data. but since it is not showing anything, graphics pipeline is not connected or list is not posted. Please check these two things.

    Regards,

    Brijesh

  • Hi,

        Thank you for your reply.

        I have checked COMP_DVO2_setting register (0x48105208) ,the value is 0x0000E402 .  GRPX1 is  enable.  So grpx1 is connected to VENC.

        You sadi maybe graphics list is not posted , How can I  check this ?

  • Hi,

    I have found the bug, is about VENC of DVO2..... I have make it correct now .
    now I can see some junk data on display , and the display time is more than I set in the code.
    maybe something wrong with desc_buffers_size?
  • Hi 

        Thanks for your help and I can get some junk data output on DVO2

         My test bmp is a pure red screen with size of 720P,  but what I get on display is as shown below :

    It seems that vpdma is still not working right.  I have two question for this issue:  

    1, Maybe something  wrong with "STRIDE" value ? Now I set STRIDE = 3*WIDTH,(1280*3 =3840).  DVO_FMT is set to "Two 10bit wide video streams(YCbCr)", NOT "Three channel 10bit video stream(YCbCr/RGB)",  In my case ,How should I set the STRIDE value ?

    2, In "ti814x_read_bmp_imge\" function , if the logo.bmp is smaller than venc out size, the logo image will be show on the middle of screen,  by setting startaddr offset. . But when I load a smaller bmp file (640*480) , I still can see junk data on the whole screen.  Something wrong with vpdma firmwire ?  My firmware version is vpdmaFirmware_1B2. 

      Thanks!

  • Hi,

    1, pitch can be set by setting STRIDE variable correctly. But i think the format of the grpx is not RGB888. Can you please check this? If format is not RGB888, then change the STRIDE appropriately or change the format in grpx

    2, In addition to sending smaller bmp file, you will require to change grpx input frame size. If your bmp size is 720x480, change width and height variables appropriately. It will show small 720x480 image on 720p display and the rest of the display will have just back ground color.

    Regards,

    Brijesh

  • Hi,

         In my code , the bmp file will be checked whether it is RGB888 :

      bmp_pixel_bits = bmp_read16(bmp_source + BMP_BITS_PER_PIXEL_OFFSET);
      /* check whether the number of bits used for pixel is 24 or not */
      if (bmp_pixel_bits != 24)
      {
       printf("\nERROR: Not able to read image, use 24-bit BMP Image\n");
       return -1;
      }

    so I`M sure the bmp data loaded to DDR is RGB888.Do I need to set the format of GRPX accroding to BMP data? If yes , How to set this ?

  • Hi  Brijesh ,

        I  found something wrong with the display time when I`m debugging the issue of "Junk data" 

        when I set "disp_time" to 10 seconds,  It acturally display about 33 seconds   

        when I set "disp_time" to 20 seconds,  It acturally display about 65 seconds

        when I set "disp_time" to 50 seconds,  It acturally display about 170 seconds

        It seems that it acturally display 3 times of "disp_time" .  

    1, the BMP and grpx format is both RGB888, and output format of DVO2 is YCbCr422, considering the amount of data, RGB888 is 3 times of YCbCr422.

        would it be the reason of "3 times of disp_time"  ?  If yes, how could I fix it ? 

    2, I compate my code with the latest uboot code on git , I found some different in do_boot_logo()  (cmd_logo_814x.c)

    My code : 

    vpdma_write32(VPDMA_GRPX0_DATA_CSTAT,0x00001C00);// Hardcoded: HDMI(+VGA)->GRPX0 (0x00001C00)(0x00000000)
    vpdma_write32(VPDMA_GRPX1_DATA_CSTAT,0x00001C00);// Hardcoded: DVO2->GRPX1 (0x00001C00)(0x00000400)
    vpdma_write32(VPDMA_GRPX2_DATA_CSTAT,0x00000C00);// Hardcoded: SD->GRPX2

    Codes on git:

    vpdma_write32(VPDMA_GRPX0_DATA_CSTAT,0x00000000);// Hardcoded: HDMI(+VGA)->GRPX0
    vpdma_write32(VPDMA_GRPX1_DATA_CSTAT,0x00000400);// Hardcoded: DVO2->GRPX1
    vpdma_write32(VPDMA_GRPX2_DATA_CSTAT,0x00000C00);// Hardcoded: SD->GRPX2

    Codes in uboot of  DVRRDK_3.5

    vpdma_write32(VPDMA_GRPX0_DATA_CSTAT,0x00000000);// Hardcoded: HDMI(+VGA)->GRPX0
    vpdma_write32(VPDMA_GRPX1_DATA_CSTAT,0x00001C00);// Hardcoded: DVO2->GRPX0
    vpdma_write32(VPDMA_GRPX2_DATA_CSTAT,0x00000C00);// Hardcoded: SD->GRPX0

    What is decription of  "VPDMA_GRPX*_DATA_CSTAT"  register  (bit 10~13)?  How should I set this register in my usecase ?

    I`m not very familar with VPDMA register  and I think it may be the key to this problem.   Thank for your help~~~~

  • Hi

    Display time and different in formats are unrelated. There might be some issue in the code for timing calculation..

    CSTAT register just tells which graphics pipeline is connected to which venc,
    so
    in your config, there is a separate grxp pipeline connected to each venc
    in code on git, grpx0 is connected to hdmi and grpx1 is connected to both dvo2 and sdvenc
    in uboot code of dvrrdk, grpx0 is connected to all three vencs..

    I think you can keep your settings, it is fine. Just make sure that GRPX1, which is connected to DVO2 in your case, is configured correctly. It should be configured with 1280x720 frame size and RGB888 frame format..

    Regards,
    Brijesh
  • Can you share your file? i want to check if grpx1 is configured correctly..

    Rgds,
    Brijesh
  • Hi ,

        Thanks for your help.

        Here is the code:

    2234.cmd_logo.c
    #include <logo_814x.h>
    #ifndef CONFIG_TI814X_MIN_CONFIG
    int ti810x_read_bmp_image(uint32_t bmp_source, uint32_t bmp_dest)
    {
    	unsigned long long bmp_size = 0;
    	//uint32_t bmp_size = 0;
    	int cut_width = 0;
    	int bmp_width = 0;
    	int bmp_height = 0;
    	int bmp_stride = 0;
    	int bmp_data_offset = 0;
    	int bmp_pixel_bits = 0;
    	int pad	= 0;
    	int image_type = 0;
    	int image_start_addr;
    	int row_no;
    	int row_dest;
    
    	if(bmp_read16(bmp_source) == BMP_SIGNATURE)
    	{
    		/*read size of bmp file*/
    		bmp_size = (bmp_read64(bmp_source) >> 16) & 0xFFFFFFFF;
    #ifdef DEBUG_BMP
    		printf("\nfile size = %x",bmp_size);
    #endif
    		/*read data starting offset*/
    		bmp_data_offset = bmp_read16(bmp_source + BMP_DATA_OFFSET);
    #ifdef DEBUG_BMP
    		printf("\ndata offset = %x",bmp_data_offset);
    #endif
    
    		/*read bmp width*/
    		bmp_width  = bmp_read16(bmp_source + BMP_WIDTH_OFFSET);
    #ifdef DEBUG_BMP
    		printf("\ndword width  = %d",bmp_width);
    #endif
    		bmp_stride =  bmp_width * 3;
    
    		/*read bmp height*/
    		bmp_height = bmp_read16(bmp_source + BMP_HEIGHT_OFFSET );
    		if (bmp_height < 0)
    		{
    			image_type = BMP_IMAGE_TOPDOWN;
    			bmp_height *= -1;
    		}
    		else
    		{
    			image_type = BMP_IMAGE_BOTTOMUP;
    			bmp_height *= 1;
    		}
    #ifdef DEBUG_BMP
    		printf("\ndword height = %d\n",bmp_height);
    #endif
    		bmp_pixel_bits = bmp_read16(bmp_source + BMP_BITS_PER_PIXEL_OFFSET);
    		/* check whether the number of bits used for pixel is 24 or not */
    		if (bmp_pixel_bits != 24)
    		{
    			printf("\nERROR: Not able to read image, use 24-bit BMP Image\n");
    			return -1;
    		}
    
    		pad = (bmp_size - (bmp_stride * bmp_height) - 54);
    		pad /= bmp_height;
    		/*
    		   set background color
    		 */
    		memset((void *)(bmp_dest),LOGO_BGCOLOR, FRAME_SIZE);
    		if(bmp_width > WIDTH)
    		{
    			cut_width = bmp_width - WIDTH;
    			bmp_width = WIDTH;
    			bmp_stride = WIDTH * 3;
    
    		}
    		if(bmp_height > HEIGHT)
    		{
    			bmp_height = HEIGHT;
    		}
    
    		/*image start offset*/
    		image_start_addr = bmp_dest + (STRIDE * ((HEIGHT - bmp_height) >> 1 )) + ((STRIDE - (bmp_stride)) >> 1);
                  printf("<buzh_dbg>image_start_addr[0x%x], bmp_dest[0x%x],STRIDE[%d],HEIGHT[%d],bmp_height[%d],bmp_stride[%d]\n",
    			  	image_start_addr,bmp_dest,STRIDE,HEIGHT,bmp_height,bmp_stride);		/* aligning the address with 24 bit sets */
    		if ((image_start_addr - bmp_dest) % 3 == 1)
    		{
    			image_start_addr += 2;
    		}
    		else if ((image_start_addr - bmp_dest) % 3 == 2)
    		{
    			image_start_addr += 1;
    		}
    
    		/*copy image data row by row to destination offset*/
    		if (image_type == BMP_IMAGE_BOTTOMUP)
    		{
    			for(row_no = (bmp_height-1), row_dest = 0; row_no >= 0; row_no--, row_dest++)
    			{
    				memcpy((uint32_t*) (image_start_addr + (row_dest * (STRIDE))),
    				(uint32_t*) ((bmp_source + bmp_data_offset) + (row_no * (bmp_stride + (cut_width * 3)+pad))),
    					(bmp_stride));
    				/*printf("===bmp_source[0x%x],bmp_data_offset[%x],row_no[%d],bmp_stride[%d],cut_width[%d],pad[%d],src_addr[0x%x],dst_addr[0x%x]\n",
    					bmp_source,bmp_data_offset,row_no,bmp_stride,cut_width,pad,
    					(uint32_t*) ((bmp_source + bmp_data_offset) + (row_no * (bmp_stride + (cut_width * 3)+pad))),
    					image_start_addr + (row_dest * (STRIDE)));*/
    			}
    		}
    		else
    		{
    			for(row_no = 0, row_dest = 0; row_no <= (bmp_height-1); row_no++, row_dest++)
    			{
    				memcpy((uint32_t*) (image_start_addr + (row_dest * (STRIDE))),
    				(uint32_t*) ((bmp_source + bmp_data_offset) + (row_no * (bmp_stride + (cut_width * 3)+pad))),
    					(bmp_stride));
    			}
    		}
    		return 0;
    	}
    
    	return -1;
    }
    
    int ti810x_prcm_init()
    {
    	if (ti810x_prcm_enable_vps_power_and_clock()<0)
    		return -1;
    
    	return 0;
    }
    
    static int ti810x_prcm_enable_vps_power_and_clock()
    {
    	int repeat;
    	int ok;
    	uint32_t val;
    
    	/* SW_WKUP: Start a software forced wake up transition on the domain. */
    	prcm_write32(CM_HDVPSS_CLKSTCTRL, 0x02);
    
    	/* wait for 1000 cycles before checking for power update */
    	udelay(10);
    
    	/* Check the power state after the wakeup transistion */
    	for (ok=0, repeat=0; repeat<5; repeat++)
    	{
    		val = prcm_read32(PM_HDVPSS_PWRSTST);
    		if (val == 0x37)
    		{
    			ok = 1;
    			break;
    		}
    		udelay(10);
    	}
    	if (!ok)
    	{
    		return -1;
    	}
    
    	/* Enable HDVPSS Clocks */
    	prcm_write32(CM_HDVPSS_HDVPSS_CLK_CTRL, 0x02);
    
    	/* Enable HDMI Clocks */
    	prcm_write32(CM_HDVPSS_HDMI_CLKCTRL, 0x02);
    
    	for (ok=0, repeat=0; repeat<5; repeat++)
    	{
    		val = prcm_read32(CM_HDVPSS_CLKSTCTRL);
    		if ((val & 0x100) == 0x100)
    		{
    			ok = 1;
    			break;
    		}
    		udelay(10);
    	}
    	if (!ok)
    	{
    		return -1;
    	}
    
    	/* reset HDVPSS and HDMI */
    	prcm_write32(RM_HDVPSS_RSTCTRL, 0x04);
    	udelay(10);
    	prcm_write32(RM_HDVPSS_RSTST, 0x04);
    	udelay(10);
    
            /* release reset from HDVPSS and HDMI */
    	prcm_write32(RM_HDVPSS_RSTCTRL, 0x00);
    	udelay(10);
    
            /* wait for SW reset to complete */
    	for (ok=0, repeat=0; repeat<5; repeat++)
    	{
    		val = prcm_read32(RM_HDVPSS_RSTST);
    		if ((val & 0x4) == 0x4)
    		{
    			ok = 1;
    			break;
    		}
    		udelay(10);
    	}
            if (!ok)
            {
        	        return -1;
            }
    
    	/* put HDVPSS in ON State */
    	val = prcm_read32(PM_HDVPSS_PWRSTCTRL);
    	val |= 0x3;
    	prcm_write32(PM_HDVPSS_PWRSTCTRL, val);
    
    	/* wait 10 cycles after powering on */
    	udelay(10);
    
    	/* check power status */
    	for (ok=0, repeat=0; repeat<5; repeat++)
    	{
    		val = prcm_read32(PM_HDVPSS_PWRSTST);
    		if (val==0x37)
    		{
    			ok = 1;
    			break;
    		}
    		udelay(10);
    	}
        if (!ok)
        {
        	    return -1;
        }
    	/*if (CPU_TYPE == CPU_TI810X) {
    		cm_write32(HD_DAC_CTRL_REG_ADDR, 0x0000E01C);
    		cm_write32(HD_DAC_CTRL_REG_ADDR, 0x0000E000);
    		cm_write32(HD_DAC_CTRL_REG_ADDR, 0x0000E001);
    		cm_write32(HD_DAC_CTRL_REG_ADDR, 0x0000E003);
    		cm_write32(HD_DAC_CTRL_REG_ADDR, 0x0000E021);
    		cm_write32(HD_DAC_CTRL_REG_ADDR, 0x0000E1E1);
    		cm_write32(HD_DAC_CTRL_REG_ADDR, 0x0000E1E3);
    		cm_write32(HD_DAC_CTRL_REG_ADDR, 0x000001E3);
    		//cm_write32(HD_DAC_CTRL_REG_ADDR, 0x018800DB);
    	}*/
    	return 0;
    }
    
    /**
     * Initialize the PLLs
     */
    int ti810x_pll_init()
    {
    	if (ti810x_pll_config_hdvpss()<0)
    		return -1;
    
    	return 0;
    }
    
    /**
     * Configure PLL for HDVPSS unit
     */
    static int ti810x_pll_config_hdvpss()
    {
    	uint32_t rd_osc_src;
    	rd_osc_src = pll_read32(PLL_VIDEO2_PINMUX);
    	rd_osc_src &= 0xFFFFFFFE;
        #ifdef CONFIG_MACH_TI814XDVR
    	rd_osc_src |= (1<<24); // select the vout0 clock source the same as hdmi source 
        #endif
    	pll_write32(PLL_VIDEO2_PINMUX,rd_osc_src);
    	//ti810x_pll_configure(PLL_HDVPSS_BASE,19,800,4,0x00000801);
    
    	return 0;
    }
    
    /**
     * Program a PLL unit
     */
    static void ti810x_pll_configure(uint32_t baseAddr, uint32_t N, uint32_t M, uint32_t M2, uint32_t clkCtrlValue)
    {
    	uint32_t m2nval,mn2val,clkctrl,clk_out,ref_clk,clkout_dco = 0;
    	uint32_t status;
    
    	m2nval = (M2<<16) | N;
    	mn2val =  M;
    	ref_clk     = OSC_FREQ / (N+1);
    	clkout_dco  = ref_clk * M;
    	clk_out     = clkout_dco / M2;
    
    	pll_write32((baseAddr+M2NDIV    ),m2nval);
    	pll_write32((baseAddr+MN2DIV    ),mn2val);
    	pll_write32((baseAddr+TENABLEDIV),0x1);
    	pll_write32((baseAddr+TENABLEDIV),0x0);
    	pll_write32((baseAddr+TENABLE   ),0x1);
    	pll_write32((baseAddr+TENABLE   ),0x0);
    
    	clkctrl = pll_read32(baseAddr+CLKCTRL);
    	clkctrl = (clkctrl & ~(7<<10 | 1<<23)) | clkCtrlValue;
    	pll_write32(baseAddr+CLKCTRL,clkctrl);
    
    	do
    	{
    		status = pll_read32(baseAddr+STATUS);
    	} while ((status & 0x00000600) != 0x00000600);
    }
    
    /**
     * Initialize HDVPSS unit
     */
    int ti810x_vps_init()
    {
    	/* enable clocks on all units */
    	vps_write32(VPS_CLKC_ENABLE,0x01031fff);
    	/*setup both HDMI and HDCOMP Clock source*/
    	vps_write32(VPS_CLKC_VENC_CLK_SELECT, 0x0009050f);
    	udelay(10);
    
    	/* enable comp units(HDMI and HDCOMP(exclude TI814X)) */
    	vps_write32(VPS_COMP_STATUS,0x3010101 /*0x0000101*/);
    
    	// set background color
    	vps_write32(VPS_COMP_BGCOLOR, LOGO_BGCOLOR);
    
    	return 0;
    }
    
    int ti810x_set_mode(int dispno,int xres, int yres, char cmd[])
    {
    	ti810x_pll_config_hdmi(74250000);//ti810x_pll_config_hdmi(25200000);
    	ti810x_hdmi_enable((74250000));//ti810x_hdmi_enable(25200000);
    
    	/* LCD pixel clock 6.5 MHz */
    	ti810x_pll_config_dvo2((74250000));//ti810x_pll_config_dvo2(6500000);
    	pll_write32(PLL_VIDEO2_PINMUX, 0);
        
    	/*modeline "1920x1080" 148.50 1920 2008 2052 2200 1080 1084 1088 1125 +HSync +VSync */
    	/*modeline "720x480" 27.000 720 736 798 858 480 489 495 525 -hsync -vsync*/
    	/*modeline "640x480" 25.20 640 656 752 800 480 490 492 525 -HSync -VSync*/
    	/** DVO1(HDMI) **/
    	//ti810x_vps_configure_venc(0x6000, 640, 656, 752, 800, 480, 490, 492, 525, 0, 1, 1,cmd);
    	ti810x_vps_configure_venc(0x6000, 1280, 1390, 1430, 1650, 720, 725, 730, 750, 0, 1, 1,cmd);
    
    	/** VENC_A(HDCOMP) **/
    	//ti810x_vps_configure_venc(0x8000, 640, 656, 752, 800, 480, 490, 492, 525, 0, 1, 1,cmd);
    	ti810x_vps_configure_venc(0x8000, 1280, 1390, 1430, 1650, 720, 725, 730, 750, 0, 1, 1,cmd);
    
    	/** DVO2 **/
    	//ti810x_vps_configure_venc(0xA000, 640, 656, 752, 800, 480, 490, 492, 525, 0, 1, 1,cmd);
    	ti810x_vps_configure_venc(0xA000, 1280, 1390, 1430, 1650, 720, 725, 730, 750, 0, 1, 1,cmd);
    
    	/* enable all video encoders */
    	vps_write32(VPS_CLKC_VENC_ENABLE, 0xF);
    
    	ti810x_pll_hdmi_setwrapper_clk();
    
    	return 0;
    }
    
    /**
     * Configure PLL for HDMI
     */
    int ti810x_pll_config_hdmi(uint32_t freq)
    {
    	uint32_t rd_osc_src;
    	pll_config_t config;
    
    	rd_osc_src = pll_read32(PLL_OSC_SRC_CTRL);
    	pll_write32(PLL_OSC_SRC_CTRL,(rd_osc_src & 0xfffbffff) | 0x0);
    
    	rd_osc_src = pll_read32(PLL_VIDEO2_PINMUX);
    	rd_osc_src &= 0xFFFFFFFE;
    	pll_write32(PLL_VIDEO2_PINMUX,rd_osc_src);
    	ti810x_pll_get_dividers(freq, 1, &config);
    
    	ti810x_pll_configure(PLL_VIDEO2_BASE, config.n, config.m, config.m2, config.clk_ctrl);
    
    	return 0;
    }
    
    /**
     * Configure PLL for DVO2
     */
    int ti810x_pll_config_dvo2(uint32_t freq)
    {
    	uint32_t rd_osc_src;
    	pll_config_t config;
    
    	rd_osc_src = pll_read32(PLL_OSC_SRC_CTRL);
    	pll_write32(PLL_OSC_SRC_CTRL,(rd_osc_src & 0xfffbffff) | 0x0);
    	
    	ti810x_pll_get_dividers(freq, 1, &config);
    
    	ti810x_pll_configure(PLL_VIDEO1_BASE, config.n, config.m, config.m2, config.clk_ctrl);
    
    	return 0;
    }
    
    /**
     * Enable HDMI output.
     */
    void ti810x_hdmi_enable(int freq)
    {
    	uint32_t temp, temp1;
    
    	/* wrapper soft reset */
    	temp = hdmi_read32(0x0010) ;
    	temp1 = ((temp & 0xFFFFFFFE)| 0x1 );
    	hdmi_write32(0x0300, temp1);
    	temp = 0;
    	udelay(10);
    
    	/* configure HDMI PHY */
    	/* 48 Mhz Clock input to HDMI ie SDIO clock output from PRCM */
    	prcm_write32(0x15B0,0x2);
    
    	/* Power on the phy from wrapper */
    	hdmi_write32(0x0040, 0x8);
    
    	while((hdmi_read32(0x0040) & 0x00000003) != 2);
    
    	hdmi_write32(0x0040, 0x4A);
    	while((hdmi_read32(0x0040) & 0x000000FF ) != 0x5A);
    
    	hdmi_write32(0x0040, 0x8A);
    	while((hdmi_read32(0x0040) & 0xFF) != 0xAA);
    
    	/* Dummy read to PHY base to complete the SCP reset process HDMI_PHY_U_BAS */
    	temp = hdmi_read32(0x0300);
    
    	temp = hdmi_read32(0x0300);
    
    	if(freq > 50000000)
    	temp1 = ((temp & 0x3FFFFFFF)|(0x1 << 30));//0x40000000);
    	else
    	temp1 = ((temp & 0x3FFFFFFF)|(0x0 << 30));//0x40000000);
    	hdmi_write32(0x0300, temp1);
    
    	temp = hdmi_read32(0x030C) ;
    	temp1 = ((temp & 0x000FFFFF)|0x85400000);
    	hdmi_write32(0x030C, temp1);
    
    	hdmi_write32(0x0304, 0xF0000000);
    
    	udelay(10);
    
    	/* cec clock divider config */
    	temp = hdmi_read32(0x0070) ;
    	temp1 = temp | 0x00000218;
    	hdmi_write32(0x0070, temp1);
    
    	/* wrapper debounce config */
    	temp = hdmi_read32(0x0044) ;
    	temp1 = temp | 0x00001414;
    	hdmi_write32(0x0044, temp1);
    
    	/* packing mode config */
    	temp = hdmi_read32(0x0050) ;
    	temp1 = temp | 0x105;
    	hdmi_write32(0x0050, temp1);
    
    	/* disable audio */
    	hdmi_write32(0x0080, 0x0);
    
    	/* release HDMI IP CORE reset and release power down of core */
    	hdmi_write32(0x0414, 0x1);
    	hdmi_write32(0x0424, 0x1);
    
    	/* video action  config of hdmi */
    	hdmi_write32(0x0524, 0x0);
    
    	/* config input data bus width */
    	hdmi_write32(0x0420, 0x7);
    
    	/* configure AVI INFOFRAME */
    	hdmi_write32(0x0528, 0x0);  // VID_MODE CONFIG
    	hdmi_write32(0x04CC, 0x1);  // DATA ENABLE CNTRL
    	hdmi_write32(0x0420, 0x37); // ENABLE VSYNC AND HSYNC
    	hdmi_write32(0x04F8, 0x0);  // iadjust config to enable vsync
    	hdmi_write32(0x0520, 0x10); // csc is bt709
    	// enable change HDMI mode to DVI mode,
    	// both DVI and HDMI monitor can works under DVI mode
    	hdmi_write32(0x09BC, 0x20); // enable hdmi
    
    	hdmi_write32(0x0608, 0x20); // tmds_ctrl
    	hdmi_write32(0x0904, 0x0);  // disable n/cts of actrl
    	hdmi_write32(0x0950, 0x0);  // disable audio
    	hdmi_write32(0x0414, 0x0);  // keep audio  operation in reset state
    
    	/* configure AVI INFOFRAME */
    	hdmi_write32(0x0A00, 0x82);
    	hdmi_write32(0x0A04, 0x2);
    	hdmi_write32(0x0A08, 0xD);
    	hdmi_write32(0x0A10, 0x1);
    	hdmi_write32(0x0A14, 0xA0);
    	hdmi_write32(0x0A1C, 0x8F);
    
    	hdmi_write32(0x0538 , 0x3);  // DISABLE DEEP COLOR MODE IN DC PACKET
    	hdmi_write32(0x09C0 , 0x10);
    	hdmi_write32(0x09F8 , 0x3);  // ENABLE AND REPEAT AVI INFOFRAM TRANSMISSON
    	hdmi_write32(0x09FC , 0xF);  // ENABLE AND REPEAT GENEERAL PACKET TRANSMISSION
    }
    
    int ti810x_control_pinmux(void)
    {
    	volatile unsigned int int_mux;
    	
    	if (CPU_TYPE == CPU_TI814X) 
          {
    		REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0AB8) = 0x1;   /* vout0_fid_mux1 */
    		REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0ABC) = 0x1;   /* vout0_clk */
    		REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0AC0) = 0x1;   /* vout0_hsync */
    		REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0AC4) = 0x1;   /* vout0_vsync */
    		REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0AC8) = 0x1;   /* vout0_avid */
    		REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0ACC) = 0x1;   /* vout0_b_cb_c[2] */
    		REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0AD0) = 0x1;   /* vout0_b_cb_c[3] */
    		REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0AD4) = 0x1;   /* vout0_b_cb_c[4] */
    		REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0AD8) = 0x1;   /* vout0_b_cb_c[5] */
    		REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0ADC) = 0x1;   /* vout0_b_cb_c[6] */
    		REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0AE0) = 0x1;   /* vout0_b_cb_c[7] */
    		REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0AE4) = 0x1;   /* vout0_b_cb_c[8] */
    		REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0AE8) = 0x1;   /* vout0_b_cb_c[9] */
    		REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0AEC) = 0x1;   /* vout0_g_y_yc[2] */
    		REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0AF0) = 0x1;   /* vout0_g_y_yc[3] */
    		REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0AF4) = 0x1;   /* vout0_g_y_yc[4] */
    		REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0AF8) = 0x1;   /* vout0_g_y_yc[5] */
    		REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0AFC) = 0x1;   /* vout0_g_y_yc[6] */
    		REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0B00) = 0x1;   /* vout0_g_y_yc[7] */
    		REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0B04) = 0x1;   /* vout0_g_y_yc[8] */
    		REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0B08) = 0x1;   /* vout0_g_y_yc[9] */
    #if 0	
                  REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0B0C) = 0x1;   /* vout0_r_cr[2] */
    		REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0B10) = 0x1;   /* vout0_r_cr[3] */
    		REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0B14) = 0x1;   /* vout0_r_cr[4] */
    		REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0B18) = 0x1;   /* vout0_r_cr[5] */
    		REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0B1C) = 0x1;   /* vout0_r_cr[6] */
    		REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0B20) = 0x1;   /* vout0_r_cr[7] */
    		REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0B24) = 0x1;   /* vout0_r_cr[8] */
    		REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0B28) = 0x1;   /* vout0_r_cr[9] */
    
    		/* HDMI I2C_scl and I2C_sda Function 2*/
    		REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0934) = 0x60002;   /* hdmi_ddc_scl_mux0 */
    		REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0938) = 0x60002;   /* hdmi_ddc_sda_mux0 */
    		REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x09BC) = 0x40010;  /*hdmi_hpd_mux0 pinmmr112[4]*/
    		REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x09B8) = 0x60010;  /*hdmi_cec_mux0 pinmmr111[4] */
    		/* TODO HDMI CEC and HPD to be added in pinmux */
    		/* Currently its shared with GPMC. */
    #endif
    		/* VIN0 TODO Do we need to enable RXACTIVE Bit in pinmux for input pins? */
    		/* Vin0 hsync1 and vin0 vsync1 */
    		REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0A14) = 0x50001;   /* vin0_clk1 */
    		REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0A18) = 0x0;       /* vin0_de0_mux0 - DeSelect input */
    		REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0A1C) = 0x50001;   /* vin0_fld0_mux0 */
    		REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0A20) = 0x50001;   /* vin0_clk0 */
    		REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0A24) = 0x50001;   /* vin0_hsync0 */
    		REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0A28) = 0x50001;   /* vin0_vsync0 */
    		REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0A2C) = 0x50001;   /* vin0_d0 */
    		REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0A30) = 0x50001;   /* vin0_d1 */
    		REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0A34) = 0x50001;   /* vin0_d2 */
    		REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0A38) = 0x50001;   /* vin0_d3 */
    		REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0A3c) = 0x50001;   /* vin0_d4 */
    		REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0A40) = 0x50001;   /* vin0_d5 */
    		REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0A44) = 0x50001;   /* vin0_d6 */
    		REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0A48) = 0x50001;   /* vin0_d7 */
    		REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0A4c) = 0x50001;   /* vin0_d8 */
    		REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0A50) = 0x50001;   /* vin0_d9 */
    		REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0A54) = 0x50001;   /* vin0_d10 */
    		REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0A58) = 0x50001;   /* vin0_d11 */
    		REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0A5C) = 0x50001;   /* vin0_d12 */
    		REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0A60) = 0x50001;   /* vin0_d13 */
    		REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0A64) = 0x50001;   /* vin0_d14 */
    		REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0A68) = 0x50001;   /* vin0_d15 */
    #if 0
    		REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0A6C) = 0x50001;   /* vin0_d16 */
    		REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0A70) = 0x50001;   /* vin0_d17 */
    		REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0A74) = 0x50001;   /* vin0_d18 */
    		REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0A78) = 0x50001;   /* vin0_d19 */
    		REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0A7C) = 0x50001;   /* vin0_d20 */
    		REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0A80) = 0x50001;   /* vin0_d21 */
    		REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0A84) = 0x50001;   /* vin0_d22 */
    		REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0A88) = 0x50001;   /* vin0_d23 */
    		REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0A8C) = 0x50001;   /* vin0_de0_mux1 */
    		REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0A90) = 0x50001;  /* vin0_de1 */
    		REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0A94) = 0x50001;   /* vin0_fld0_mux1 */
    		REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0A98) = 0x50001;   /* vin0_fld1 */
    
    
    		/* VIN1 Configuration Function 3*/
    		REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0B2C) = 0x50004;   /* vin1_hsync0 */
    		/* this is function 2 */
    		REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x09F0) = 0x50002;   /* vin1_clk1 */
    		REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0B30) = 0x50004;   /* vin1_vsync0 */
    		REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0B34) = 0x50008;   /* vin1_de0 */
    
    		REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0B38) = 0x50004;   /* vin1_clk0 */
    		REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0B3C) = 0x50004;   /* vin1a_d[0] */
    		REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0B40) = 0x50004;   /* vin1a_d[1] */
    		REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0B44) = 0x50004;   /* vin1a_d[2] */
    		REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0B48) = 0x50004;   /* vin1a_d[3] */
    		REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0B4C) = 0x50004;   /* vin1a_d[4] */
    		REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0B50) = 0x50004;   /* vin1a_d[5] */
    		REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0B54) = 0x50004;   /* vin1a_d[6] */
    		REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0B58) = 0x50004;   /* vin1a_d[8] */
    		REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0B5C) = 0x50004;   /* vin1a_d[9] */
    		REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0B60) = 0x50004;   /* vin1a_d[10] */
    		REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0B64) = 0x50004;   /* vin1a_d[11] */
    		REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0B68) = 0x50004;   /* vin1a_d[12] */
    		REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0B6C) = 0x50004;   /* vin1a_d[13] */
    		REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0B70) = 0x50004;   /* vin1a_d[14] */
    		REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0B74) = 0x50004;   /* vin1a_d[15] */
    		REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0B78) = 0x50004;   /* vin1a_d[16] */
    		REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0B7C) = 0x50004;   /* vin1a_d[17] */
    		REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0B80) = 0x50004;   /* vin1a_d[18] */
    		REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0B84) = 0x50004;   /* vin1a_d[19] */
    		REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0B88) = 0x50004;   /* vin1a_d[20] */
    		REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0B8C) = 0x50004;   /* vin1a_d[21] */
    		REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0B90) = 0x50004;   /* vin1a_d[22] */
    		REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0B94) = 0x50004;   /* vin1a_d[23] */
    		REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0B98) = 0x50004;   /* vin1a_d[7] */
    
    		/* I2c2  configuration Function 6*/
    		REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0924) = 0x60020;   /* i2c2_scl_mux0 */
    		REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0928) = 0x60020;   /* i2c2_sda_mux0 */
    
    		/* TODO Find proper place for this Set the divider for the SYSCLK10 */
    		*(volatile unsigned int *)0x48180324 = 3;
    		
    		/* I2C2 interrupt is routed through I2C1 interrupt through the
    		 * crossbar. For this, INT_MUX_[#int_number] register in the
    		 * Chip Control Module needs to be programmed.
    		 * INT_MUX_[#int_number] registers start from 0xF54
    		 * offset and one register is used to program 4 interrupt
    		 * muxes (6 bits for each mux, 2 bits reserved).
    		 * After reset INT_MUX_[#int_number] defaults to 000000, which
    		 * maps the interrupt from default mapping to interrupt_[#int_number].
    		 *
    		 * I2C_INT1 is mapped to interrupt line 19 and
    		 * INTMUX 16 to 19 --> 0x0f64. So read it first,
    		 * modify the respective bit field and write is back.
    		 */
    		int_mux = REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0f64);
    		/* I2CINT2 value = 4, INT_MUX_19_SHIFT = 24*/
    		int_mux |= (4 << 24);
    		REG32(CSL_TI8107_CTRL_MODULE_BASE + 0x0f64) = int_mux;
    	}
    	//else if(CPU_TYPE == CPU_TI814X)
    	//{
    		/**TO DO**/
    	//}
    #endif	
    	}
    	return 0;
    }
    
    
    /* Change pin mux */
    void ti810x_pll_hdmi_setwrapper_clk()
    {
            uint32_t rd_osc_src;
            rd_osc_src = pll_read32(PLL_VIDEO2_PINMUX);
            rd_osc_src |= 0x1;
            pll_write32(PLL_VIDEO2_PINMUX,rd_osc_src);
    }
    
    static int ti810x_pll_get_dividers(uint32_t req_out_clk, int hdmi, pll_config_t* config)
    {
    	int32_t ret = -1;
    	int32_t n, m, m2;
    	float ref_clk, dco_clk, clk_out;
    	float best_delta;
    
    	config->n = 0;
    	config->m = 0;
    	config->m2 = 0;
    	config->clk_ctrl = 0;
    	best_delta = 1E20;
    
    	if(req_out_clk == 6500000)
    	{
    		config->n = 19;
    		config->m = 504;
    		config->m2 = 20;
    		config->clk_ctrl = 0x801;
    		return 0;		
    	}
    
    	if(hdmi)
    	{
    		config->n = 19;//n;
    		config->m = 1485;//m;
    		config->m2 =10;//m2;
    		config->clk_ctrl = 0x200a1001;
    			if(req_out_clk ==74250000 )
    			{
    				config->n = 19;//n;
    				config->m = 742;//m;
    				config->m2 =10;//m2;
    				config->clk_ctrl = 0x20020801;
    			}
        		else if(req_out_clk ==65000000 )
        		{
        			config->n = 19;//n;
        			config->m = 650;//m;
        			config->m2 =10;//m2;
    	    		config->clk_ctrl = 0x20020801;
        		}
    	    	else if(req_out_clk ==54000000 )
    			{
    				config->n = 19;//n;
    				config->m = 540;//m;
    				config->m2 =10;//m2;
    				config->clk_ctrl = 0x20020801;
    			}
        		else if(req_out_clk ==27000000 )
    	    	{
    		    	config->n = 19;//n;
    	    		config->m = 540;//m;
    		    	config->m2 =2;//m2;
        			config->clk_ctrl = 0x200A0801;//0x20020801;
        		}
    	    	else if(req_out_clk == 33000000 )
        		{
    	    		config->n = 19;//n;
    	    		config->m = 660;//m;
        			config->m2 =2;//m2;
    	    		config->clk_ctrl = 0x200A0801;//0x20020801;
    	    	}
    			else if(req_out_clk == 25200000)
    			{
    				config->n = 19;//n;
    				config->m = 1512;//m;
    				config->m2 = 6;//m2;
    				config->clk_ctrl = 0x200a1001;//0x20020801;
    			}
    
    
        		ref_clk = 20E6f / (config->n+1);
    	    	dco_clk = ref_clk * config->m;
        		clk_out = dco_clk / config->m2;
    	}
    	else
    	{
    		for (n=19; n<=19 && ret!=0; n++)
    		{
    			ref_clk = 20E6f / (n+1);
    			if (ref_clk < 2.5E6)
    			{
    				int32_t m_min;
    				int32_t m_max;
    
    				if (hdmi)
    				{
    					m_min = 1000.0E6f / ref_clk;
    					m_max = 2000.0E6f / ref_clk;
    				}
    				else
    				{
    					m_min =  500.0E6f / ref_clk;
    					m_max = 1000.0E6f / ref_clk;
    				}
    
    				for (m=m_min; m<m_max && ret!=0; m++)
    				{
    					dco_clk = ref_clk * m;
    					for (m2 = 10; m2 <= 20; m2++)
    					{
    						float delta;
    						clk_out = dco_clk / m2;
    						delta = clk_out-req_out_clk;
    						if (delta<0)
    						{
    							delta = -delta;
    						}
    
    						if (delta<best_delta)
    						{
    							config->n = n;
    							config->m = m;
    							config->m2 = m2;
    							if (hdmi)
    							{
    								config->clk_ctrl = 0x200a1001;
    							}
    							else
    							{
    								config->clk_ctrl = 0x00000801;
    							}
    
    							best_delta = delta;
    
    							if (delta==0.0)
    							{
    								ret = 0;
    								break;
    							}
    						}
    					}
    				}
    			}
    		}
    	}
    	return ret;
    }
    
    /**
     * Configure VENC unit
      */
    static void ti810x_vps_configure_venc(uint32_t cfg_reg_base, int hdisp, int hsyncstart, int hsyncend, int htotal, int vdisp, int vsyncstart, int vsyncend, int vtotal, int enable_invert, int hs_invert, int vs_invert,char *cmd)
    {
    
      	int av_start_h = htotal-hsyncstart;
    	/*int av_start_v = vtotal-vsyncstart;*/
    	int hs_width = hsyncend-hsyncstart;
    	int vs_width = vsyncend-vsyncstart;
    	int cfg0;
    	 /* CFG10: clamp, lines (total num lines), pixels (total num pixels/line) */
    
    	vps_write32(cfg_reg_base+0x28, 0x84000000 | (vtotal<<12) | (htotal));  // 84h=132d for 1080i
    
    	/*CFG10: HSYNC Width, 2nd VBI end, 1st VBI END*/
    	vps_write32(cfg_reg_base+0x2C, (hs_width << 24) | (vtotal - vdisp - 3));
    	 /* CFG12: hs_width, act_pix, h_blank-1 */
    
      	vps_write32(cfg_reg_base+0x30, (hs_width<<24) | (hdisp<<12) | (av_start_h-1));
    
     	 /* CFG15: vout_hs_wd, vout_avdhw, vout_avst_h (same as in 0x6030?) */
    
      	vps_write32(cfg_reg_base+0x3c, (hs_width<<24) | (hdisp<<12) | (av_start_h));
    
      	/* CFG16: bp_pk_l (back porch peak), vout_avst_v1 (active video start field 1), vout_hs_st (hsync start) */
    
      	vps_write32(cfg_reg_base+0x40, ((vtotal - vdisp)<<12));
    
     	 /* CFG17: bp_pk_h (back porch peak), vout_avst_vw (num active lines), vout_avst_v1 (active video start field 2) */
    
      	vps_write32(cfg_reg_base+0x44, (vdisp<<12));
    
      	/* CFG18: vout_vs_wd1, vout_vs_st1 (vsync start), vout_avd_vw2 (vs width field 2) */
    
      	vps_write32(cfg_reg_base+0x48, (vs_width<<24) | ((vsyncstart - vdisp) << 12));
    
    	vps_write32(cfg_reg_base+0x4C, 0x4000);
    
      	/* CFG21: osd_avd_hw (number of pixels per line), osd_avst_h */
    
    	if (cfg_reg_base == 0x8000)
      		vps_write32(cfg_reg_base+0x54, (hs_width<<24) | (hdisp<<12) | (av_start_h - 5));
    	else
      		vps_write32(cfg_reg_base+0x54, (hs_width<<24) | (hdisp<<12) | (av_start_h - 8));
    
      	/* CFG22: osd_avst_v1 (first active line), osd_hs_st (HS pos) */
    
      	vps_write32(cfg_reg_base+0x58, ((vtotal - vdisp) << 12));
    
      	/* CFG23: osd_avd_vw1 (number of active lines), osd_avst_v2 (first active line in 2nd field) */
    
      	vps_write32(cfg_reg_base+0x5c, (vdisp<<12));
    
      	/* CFG24: osd_vs_wd1 (vsync width), osd_vs_st1 (vsync start), osd_avd_vw2 */
    
      	vps_write32(cfg_reg_base+0x60, (vs_width<<24));
    
      	/* CFG25: osd_vs_wd2, osd_fid_st1, osd_vs_st2 */
    
      	vps_write32(cfg_reg_base+0x64, 0x00000000);
    
    	/*for the HDCOMP VGA output, need remove the SOG to support VGA
    	for the DM8107, special CSC coefficients are required to swap the color
    	*/
    	cfg0 = (enable_invert<<25) | (hs_invert<<24) | (vs_invert<<23) \
        | (3<<16) // video out format: 10 bit, separate syncs
        | (1<<13) // bypass gamma correction
        | (1<<5)  // bypass CSC
        | (1<<4)  // bypass 2x upscale
        | (1<<0);  // 480p format
    
    	if (cfg_reg_base == 0x8000) {
    		if (CPU_TYPE == CPU_TI810X) {
    			vps_write32(cfg_reg_base + 0x08, 0x04000400);
    			vps_write32(cfg_reg_base + 0x10, 0x04000000);
    			vps_write32(cfg_reg_base + 0x1c, 0x00000b00);
    			/*enable the CSC due to the color swap issue.*/
    //	cfg0 &= (~(1 << 5));
    		}
    		vps_write32(cfg_reg_base + 0x20, 0x00000b00);
    		vps_write32(cfg_reg_base + 0x24, 0x00000b00);
    	}
    	vps_write32(cfg_reg_base+0x00, cfg0);
    	
    	if(cfg_reg_base == 0xA000)
    	{
    		/**Two 10-bit wide video streams, 
    		 * color space conversion engaged, 
    		 * YUV colorspace for DVO2**/
    		vps_write32(cfg_reg_base + 0, 0x44013051);
    		
    		/**CSC Settings: RGB to YUV Related for DVO2**/
    		vps_write32(cfg_reg_base + 0x4, 0x003f0275); 	
    		vps_write32(cfg_reg_base + 0x8, 0x1ea500bb);
    		vps_write32(cfg_reg_base + 0xC, 0x1f9901c2);
    		vps_write32(cfg_reg_base + 0x10, 0x1fd71e67);
    		vps_write32(cfg_reg_base + 0x14, 0x003f01c2);
    		vps_write32(cfg_reg_base + 0x18, 0x00200200);
    	}
    
    	if (strcmp(cmd,"colorbar") == 0)
    		vps_write32(cfg_reg_base+0x00, vps_read32(cfg_reg_base+0x00) | 0x40000000 | 1<<15); /* start encoder with color bar bit set*/
    	else
    		vps_write32(cfg_reg_base+0x00, vps_read32(cfg_reg_base+0x00) | 0x40000000); /* start encoder */
    }
    
    /**
     * Load firmware for VPDMA.
     */
    static int ti810x_vpdma_load_firmware(uint32_t* desc_buffer)
    {
    	uint32_t* firmware;
    	volatile uint32_t status;
    
        volatile uint32_t vpdma_firmware_size;
        uint16_t *vpdma_firmware;
    
    	int repeat;
    	int result = 0;
    	int ok;
    
    	/* allocate physical contiguous memory for firmware buffer */
    	firmware = (uint32_t*)desc_buffer;
    	if (!firmware)
    	{
    #ifdef DEBUG_VPSS
    		printf("unable to allocate memory for VPDMA firmware\n");
    #endif
    		return -1;
    	}
    
        /* default firmware */
        vpdma_firmware      = vpdmaFirmware_1AD;//vpdmaFirmware_1B2;//
        vpdma_firmware_size = vpdmaFirmware_1AD_size;//vpdmaFirmware_1B2_size;//
    /*
        #ifdef CONFIG_TI813X
        {
            // if DM385 then load different firmware 
            vpdma_firmware      = vpdmaFirmware_1B7;
            vpdma_firmware_size = vpdmaFirmware_1B7_size;
        }
        #endif
    
        #ifdef CONFIG_TI816X
        if(get_cpu_rev() >= PG2_0)
        {
            //  if TI816x and >= PG2.0 then load different firmware 
            vpdma_firmware      = vpdmaFirmware_1B2;
            vpdma_firmware_size = vpdmaFirmware_1B2_size;
        }
        #endif
    */
    	/* copy firmware to buffer */
    	memcpy(firmware,vpdma_firmware, vpdma_firmware_size);
    	/* Reset VPDMA module */
    	ti810x_vps_reset_module( VPS_MODULE_VPDMA, 1);
    	udelay(1000000);
    	ti810x_vps_reset_module( VPS_MODULE_VPDMA, 0);
    
    	/* load firmware */
    	vpdma_write32(VPDMA_LIST_ADDR, (uint32_t)firmware);
    
    	/* wait till firmware is loaded */
            for (ok=0, repeat=0; repeat<100 && !ok; repeat++)
    	{
    		status = vpdma_read32(VPDMA_LIST_ATTR);
    		if ((status & 0x80000) == 0x80000)
    		{
    			ok = 1;
    		}
    		else
    		{
    			udelay(10);
    		}
    	}
    
            if (!ok)
            {
    #ifdef DEBUG_VPSS
        	        printf("failed to load VPDMA firmware\n");
    #endif
        	        result = -1;
            }
    
        printf("VPDMA Firmware Version = 0x%08x\n", vpdma_read32(VPDMA_PID));
    
    	return result;
    }
    
    void ti810x_vps_reset_module(vps_module_t module, int assert_reset)
    {
    	uint32_t val = vps_read32(VPS_CLKC_RESET);
    
    	if (assert_reset)
    		val |= (1<<module);
    	else
    		val &= ~(1<<module);
    
    	vps_write32(VPS_CLKC_RESET, val);
    }
    
    uint32_t ti810x_dispmgr_create_grpx_conf_descriptor(int grpx_unit, uint32_t* desc_buffer, uint32_t* payload_buffer, uint32_t xres, uint32_t yres)
    {
    	uint32_t size = 0;
    	uint32_t* desc;
    	uint32_t* payload;
    
    	/* set up frame configuration descriptor */
    	desc = desc_buffer;
    	desc[0] = 0x1;   /* frame configuration address */
    	desc[1] = 16;    /* data length */
    	desc[2] = (uint32_t)payload_buffer;  /* payload location */
    	desc[3] = 0
    		| (0xB<<27)     /* packet type */
    		| (0<<26)       /* indirect command */
    		| (1<<24)       /* block type */
    		| ((grpx_unit+1)<<16)  /* destination GRPX0..GRPX2 */
    		| (1<<0)        /* payload size in 128 bit units */
    		;
    	size += 16;
    	payload = payload_buffer;
    	payload[0] = 0;      /* reserved */
    	if(grpx_unit == 2)
    	{
    		payload[1] = 0
    		    | (720<<16)  /* frame width */
    		    | (480<<0);   /* frame height */
    	}
    	else
    	{
    		payload[1] = 0
    		    | (xres<<16)  /* frame width */
    		    | (yres<<0);   /* frame height */
    	}
    	payload[2] = 0;      /* reserved */
    	payload[3] = 0
    		| (0<<30)    /* progressive format */
    		| (1<<31);   /* soft reset of GRPX unit */
    
    	printf("<buzh_dbg>[ti810x_dispmgr_create_grpx_conf_descriptor]grpx_unit[%d], desc[0x%x,0x%x,0x%x,0x%x],payload[0x%x,0x%x,0x%x,0x%x]\n",grpx_unit,desc[0],desc[1],desc[2],desc[3],payload[0],payload[1],payload[2],payload[3]);
    	return size;
    }
    
    uint32_t ti810x_dispmgr_setup_layers(uint32_t* desc_buffer,
                                         int stride,
                                         int width,
                                         int height,
                                         uint32_t dispTime,
                                         uint32_t dispFps,
                                         uint32_t paddr)
    {
    	uint32_t size = 0;
    	uint32_t numDesc = 0, i =0;
    	uint32_t* desc;
    	int chan;
    	int x = 0;
    	int y = 0;
    	uint32_t layer_ctrl;
    
    	desc = desc_buffer ;
    	layer_ctrl = 0x0000E400;
    
    	/* add src_viewport origin to surface start address */
    	/*This should be made a param for multiple displays*/
    	layer_ctrl |= 1<<(2);  /* enable GRPX0 layer */
    
    	chan = 29;
    
        /* Program the same data descriptor
            BOOT_LOGO_DISPLAY_TIME_IN_SECS x BOOT_LOGO_DISPLAY_FPS
            times.
    
           Buffer size for descriptors is VPDMA_DESC_BUFFER_SIZE.
            If size needed for descriptors is more than this
            then limit number of descriptors to fit within
            VPDMA_DESC_BUFFER_SIZE
        */
        numDesc = dispTime * dispFps;
    
        if(numDesc*VPDMA_DATA_DESC_SIZE > VPDMA_DESC_BUFFER_SIZE)
        {
            numDesc = VPDMA_DESC_BUFFER_SIZE/VPDMA_DATA_DESC_SIZE;
        }
    
        for(i=0; i<numDesc; i++)
        {
            /* set up data transfer descriptor */
            desc[0] = 0
                | (DATA_TYPE<<26)    // RGB-888
                | (0<<25)            // no notification
                | (0<<24)            // field number
                | (0<<23)            // 2-dimensional data
                | (0<<20)            // +1 line skip (even)
                | (0<<16)            // +1 line skip (odd)
                | (stride)           // line stride
                ;
            desc[1] = 0
                | (width<<16)        // line length in pixels
                | (height)           // number of rows
                ;
            desc[2] = paddr;
            desc[3] = 0
                    | (0xA<<27)    // packet type
                | (0<<26)      // 1D mode
                | (0<<25)      // inbound direction
                | (chan<<16)   // channel
                | (0<<9)       // priority
                | (chan<<0)    // next channel
                ;
            desc[4] = 0
                | (width<<16)  // region width
                | (height)     // region height
                ;
            desc[5] = 0
                | (x<<16)      // horizontal start
                | (y<<0)       // vertical start
                ;
            desc[6] = 0
                | (1<<7)       // first region
                | (1<<8)       // last region
                ;
            desc[7] = 0; // alpha blending enable
        	desc += 8;
    	    size += 32;
        }
    
    	vps_write32(VPS_COMP_HDMI_VOUT1, layer_ctrl);
    	/*HDCOMP register was swapped from DM816X to DM810X*/
    	if (CPU_TYPE == CPU_TI816X)
    		vps_write32(VPS_COMP_HDCOMP, layer_ctrl);
    	else if (CPU_TYPE == CPU_TI810X)
    		vps_write32(VPS_COMP_COMP_RESV, layer_ctrl);
    	/*Review[VIVB]*/	
    #ifdef CONFIG_MACH_TI814XDVR
        vps_write32(VPS_COMP_HDCOMP, layer_ctrl);    
    #endif   
    
    	return size;
    }
    
    uint32_t ti810x_dispmgr_setup_layers_DVO2(uint32_t* desc_buffer,
                                              int stride,
                                              int width,
                                              int height,
                                              uint32_t dispTime,
                                              uint32_t dispFps,
                                              uint32_t paddr)
    {
    	uint32_t size = 0;
    	uint32_t numDesc = 0, i =0;
    	uint32_t* desc;
    	int chan;
    	int x = 0;
    	int y = 0;
    	uint32_t layer_ctrl;
    
    	desc = desc_buffer ;
    	layer_ctrl = 0x0000E400;
    
    	/* add src_viewport origin to surface start address */
    	/*This should be made a param for multiple displays*/
    	layer_ctrl |= 1<<(1);  /* enable GRPX1 layer */
    
    	chan = 30;    /* GRPX1_CHANNEL_NUMBER */
    
        /* Program the same data descriptor
            BOOT_LOGO_DISPLAY_TIME_IN_SECS x BOOT_LOGO_DISPLAY_FPS
            times.
    
           Buffer size for descriptors is VPDMA_DESC_BUFFER_SIZE.
            If size needed for descriptors is more than this
            then limit number of descriptors to fit within
            VPDMA_DESC_BUFFER_SIZE
        */
        numDesc = dispTime * dispFps;
    	
        if(numDesc*VPDMA_DATA_DESC_SIZE > VPDMA_DESC_BUFFER_SIZE)
        {
            numDesc = VPDMA_DESC_BUFFER_SIZE/VPDMA_DATA_DESC_SIZE;
        }
    
        for(i=0; i<numDesc; i++)
        {
            /* set up data transfer descriptor */
            desc[0] = 0
                | (DATA_TYPE<<26)    // RGB-888
                | (0<<25)            // no notification
                | (0<<24)            // field number
                | (0<<23)            // 2-dimensional data
                | (0<<20)            // +1 line skip (even)
                | (0<<16)            // +1 line skip (odd)
                | (stride)           // line stride
                ;
            desc[1] = 0
                | (width<<16)        // line length in pixels
                | (height)           // number of rows
                ;
            desc[2] = paddr;
            desc[3] = 0
                    | (0xA<<27)    // packet type
                | (0<<26)      // 1D mode
                | (0<<25)      // inbound direction
                | (chan<<16)   // channel
                | (0<<9)       // priority
                | (chan<<0)    // next channel
                ;
            desc[4] = 0
                | (width<<16)  // region width
                | (height)     // region height
                ;
            desc[5] = 0
                | (x<<16)      // horizontal start
                | (y<<0)       // vertical start
                ;
            desc[6] = 0
                | (1<<7)       // first region
                | (1<<8)       // last region
                ;
            desc[7] = 0; // alpha blending enable
        	desc += 8;
    	    size += 32;
        }
    printf("<buzh_dbg>[ti810x_dispmgr_setup_layers_DVO2] desc[0x%x,0x%x,0x%x,0x%x],desc[0x%x,0x%x,0x%x,0x%x]\n",desc[0],desc[1],desc[2],desc[3],desc[4],desc[5],desc[6],desc[7]);
    	
           //vps_write32(VPS_COMP_HDMI_VOUT0, layer_ctrl);  /* buzh added for boot_logo on DVO2  */
    	vps_write32(VPS_COMP_DVO2, layer_ctrl);
    		
    #ifdef CONFIG_MACH_TI814XDVR
        vps_write32(VPS_COMP_HDCOMP, layer_ctrl);    
    #endif   
    
    	return size;
    }
    
    int ti810x_vpdma_send_list(uint32_t* desc_buffer, int desc_len, int list_no)
    {
    	/* convert descriptor size from byte units to 128-bit units */
    	desc_len = (desc_len+15)>>4;
    	/* send list */
    	vpdma_write32(VPDMA_LIST_ADDR,(uint32_t)desc_buffer);
    	vpdma_write32(VPDMA_LIST_ATTR, 0
    			| (list_no<<24)  /* list number */
    			| (0<<16)        /* list type: normal */
    			| (desc_len<<0)  /* list size */
    			);
    
    	return 0;
    }
    
    int ti810x_dispmgr_wait_for_list_complete(int dispno)
    {
            uint32_t status;
    	int repeat;
    	int ok;
        	for (ok=0, repeat=0; repeat<100 && !ok; repeat++)
    	{
    		status = vpdma_read32(VPDMA_LIST_ATTR);
    		if ((status & 0x80000) == 0x80000)
    		{
    			ok = 1;
    		}
    		else
    		{
    			udelay(10);
    		}
    	}
        	if(repeat == 100)
    		return -1;
    
    	return 0;
    }
    
    
    static int do_color_bar(cmd_tbl_t * cmdtp,int flag, int argc, char *argv[])
    {
    	if(ti810x_prcm_init()  == -1)
    	{
    #ifdef DEBUG_VPSS
    		printf("\nERROR: ti810x_prcm_init failed");
    #endif
    		return -1;
    	}
    	
    	/**Control module PINMUX settings**/
    	ti810x_control_pinmux();
    	
    	if(ti810x_pll_init()  == -1)
        {
    #ifdef DEBUG_VPSS
    		printf("\nERROR: ti810x_pll_init failed");
    #endif
    		return -1;
    	}
    
    	if(ti810x_vps_init() == -1)
        {
    #ifdef DEBUG_VPSS
    		printf("\nERROR: ti810x_vps_init failed");
    #endif
    		return -1;
    	}
    
    	if(ti810x_set_mode(1,WIDTH,HEIGHT,argv[0])  == -1)
        {
    #ifdef DEBUG_VPSS
    		printf("\nERROR: ti810x_set_mode failed");
    #endif
    		return -1;
    	}
    	return 0;
    }
    
    static int do_boot_logo(cmd_tbl_t * cmdtp,int flag, int argc, char *argv[])
    {
        uint32_t *firmware_addr;
        uint32_t *list_addr;
    	uint32_t *payload_buffer;
    	uint32_t size;
    	uint32_t image_source = 0;
    	uint32_t disp_time = 0;
    	uint32_t disp_fps = 0;
    	uint32_t image_dest = 0;
    	uint32_t vpdma_desc_dest = 0;
    	uint32_t paddr;
    
    	/* check whether the arguments passed are correct  */
    	if (argc < 2)
    	{
    			cmd_usage(cmdtp);
    			return 1;
    	}
    	else if (strcmp(argv[1],"on") == 0)
    	{
    		if (argc != 7)
    		{
    			cmd_usage(cmdtp);
    			return 1;
    		}
    		else
    		{
    			/* address in memory where bmp image is loaded */
    			image_source = simple_strtoul(argv[2], NULL, 16);
    			image_dest = simple_strtoul(argv[3], NULL, 16);
    			vpdma_desc_dest = simple_strtoul(argv[4], NULL, 16);
    
    			disp_time = simple_strtoul(argv[5], NULL, 10);
                if(disp_time <= 0)
                {
    				printf("Bootup splash display time is out of range, using default value(60s)\n");
    				disp_time = DEFAULT_BOOT_LOGO_DISPLAY_TIME_IN_SECS;
    			}
    
     			disp_fps = simple_strtoul(argv[6], NULL, 10);
                if((disp_fps > 60) || (disp_fps < 1))
                {
    				printf("Bootup splash display FPS entered is out of range, using default value(60fps)\n");
    				disp_fps = DEFAULT_BOOT_LOGO_DISPLAY_FPS;
    			}
    		}
    	}
    	else if (strcmp(argv[1],"off") == 0)
    	{
    		vpdma_write32(VPDMA_LIST_ATTR, vpdma_read32(VPDMA_LIST_ATTR)
    		             | (VPDMA_LIST_NUMBER_HD<<24)  /* list number */
    		             | (1<<20)  /* stop bit for list  */
    		             );
    		vpdma_write32(VPDMA_LIST_ATTR, vpdma_read32(VPDMA_LIST_ATTR)
    		             | (VPDMA_LIST_NUMBER_SD<<24)  /* list number */
    		             | (1<<20)  /* stop bit for list  */
    		             );
    		return 0;
    	}
    	else
    	{
    		cmd_usage(cmdtp);
    		return 1;
    	}
    
    	/* memory address for loading vpdma firmware and descriptors, payload */
        firmware_addr    = (uint32_t*)(vpdma_desc_dest+VPDMA_DESC_FIRMWARE_OFFSET);
        payload_buffer   = (uint32_t*)(vpdma_desc_dest+VPDMA_DESC_PAYLOAD_OFFSET);
        list_addr        = (uint32_t*)(vpdma_desc_dest+VPDMA_DESC_LIST_OFFSET);
    
    	/* memory address for displaying the image formatted on the hdmi, the offset from the source location is 2 * WIDTH * HEIGHT */
    	//image_dest = image_source + 3 * 3 * WIDTH * HEIGHT;
    
    	if(image_source == image_dest)
        {
    		printf("\nERROR: <logo_read_address> & <final_bmp address> cannot be same\n");
    		return -1;
    	}
    	if((image_source == 0) || (image_dest == 0))
        {
    		printf("\nERROR: <logo_read_address> or <final_bmp address> is NULL\n");
    		return -1;
    	}
    
    	/* reading the bmp image from the specified location */
    	if(ti810x_read_bmp_image(image_source,image_dest)  == -1)
    	{
    		printf("\nERROR: reading BMP image failed");
    		return -1;
    	}
    
    	
    	/********************[SET DVO2 PORT]*******************/
    	if(ti810x_prcm_init()  == -1)
    	{
    #ifdef DEBUG_VPSS
    		printf("\nERROR: ti810x_prcm_init failed\n");
    #endif
    		return -1;
    	}
    	
    	/**Control module PINMUX settings**/
    	ti810x_control_pinmux();
    	
    	if(ti810x_pll_init()  == -1)
    	{
    #ifdef DEBUG_VPSS
    		printf("\nERROR: ti810x_pll_init failed\n");
    #endif
    		return -1;
    	}
    	if(ti810x_vps_init()  == -1)
    	{
    #ifdef DEBUG_VPSS
    		printf("\nERROR: ti810x_vps_init failed\n");
    #endif
    		return -1;
    	}
    	if(ti810x_set_mode(1,WIDTH,HEIGHT,argv[0]) == -1)
    	{
    #ifdef DEBUG_VPSS
    		printf("\nERROR: ti810x_set_mode failed\n");
    #endif
    		return -1;
    	}
    	/********************[SET DVO2 PORT]*******************/
    
    	if (ti810x_vpdma_load_firmware(firmware_addr) == -1)
    	{
    #ifdef DEBUG_VPSS
    		printf("\nERROR: vpdma_load_firmware failed\n");
    #endif
    		return -1;
    	}
        	paddr = image_dest;
    	/* HDMI->VGA Configuration Desc:GRPX0 */
    	/* Allocate physical memory for MV data */
    	printf("<buzh_dbg>--->HDMI--->descbuffer[0x%x], payload_buffer[0x%x], WIDTH[%d], HEIGHT[%d]...\n",list_addr, payload_buffer,WIDTH,HEIGHT);
    	size = ti810x_dispmgr_create_grpx_conf_descriptor(0, list_addr, payload_buffer,WIDTH,HEIGHT);
    	ti810x_vpdma_send_list(list_addr, size, 0);//last param 0, list number hardcoded for HDMI->VGA
           /* wait for list complete interrupt */
    	if(ti810x_dispmgr_wait_for_list_complete(1) == -1)
    	{
    #ifdef DEBUG_VPSS
    		printf("\nERROR: wait for list complete FAILED!\n");
    #endif
    		return -1;
    	}
    
    	/* DVO2 Configuration Desc:GRPX1 */  /*Review[VIVB]*/
    	/* Allocate physical memory for MV data */
    	printf("<buzh_dbg>--->DVO2--->descbuffer[0x%x], payload_buffer[0x%x], WIDTH[%d], HEIGHT[%d]...\n",list_addr + 0x40000, payload_buffer + 0x10,WIDTH,HEIGHT);
    	size = ti810x_dispmgr_create_grpx_conf_descriptor(1, list_addr + 0x40000, payload_buffer + 0x10,WIDTH,HEIGHT);
    	ti810x_vpdma_send_list(list_addr + 0x40000, size, 1);//last param 1, list number hardcoded for DVO2
           /* wait for list complete interrupt */
    	if(ti810x_dispmgr_wait_for_list_complete(1) == -1)
    	{
    #ifdef DEBUG_VPSS
    		printf("\nERROR: wait for list complete FAILED!");
    #endif
    		return -1;
    	}
    	// the frame start event must be properly set, or will cause screen scroll issue
    	//set the frame start event of GRPX2 to 'channel active'
    
    	vpdma_write32(VPDMA_GRPX0_DATA_CSTAT,0x00000000);// Hardcoded: HDMI(+VGA)->GRPX0
    	vpdma_write32(VPDMA_GRPX1_DATA_CSTAT,0x00000400);// Hardcoded: DVO2->GRPX1
    	//vpdma_write32(VPDMA_GRPX2_DATA_CSTAT,0x00000C00);// Hardcoded: SD->GRPX2
        //set the frame start event of GRPX1 to 'SD field ID changes'
    	
        //DATA Descriptors for HDMI/VGA
    	size = ti810x_dispmgr_setup_layers(list_addr,STRIDE,WIDTH,HEIGHT,disp_time,disp_fps,paddr);
    	ti810x_vpdma_send_list(list_addr, size, VPDMA_LIST_NUMBER_HD);	//list_no = 4
           printf("\n<buzh_dbg>===HDMI dispmgr_setup_layer: desc_buffer:[0x%x], STRIDE[%d], WIDTH[%d], HEIGHT[%d] ,paddr[0x%x]!!!\n",list_addr,STRIDE,WIDTH,HEIGHT,paddr);
           //create data transfer descriptor for GRPX1
    	//the list_addr has 0x10000 offset, because 2 GRPX share the same GRPX desc buffer = 4096 descs
    
    	size = ti810x_dispmgr_setup_layers_DVO2(list_addr + 0x40000,STRIDE,WIDTH,HEIGHT,disp_time,disp_fps,paddr);
    	printf("\n<buzh_dbg>===DVO2 dispmgr_setup_layers: desc_buffer:[0x%x], STRIDE[%d], WIDTH[%d], HEIGHT[%d] ,paddr[0x%x]!!!\n",list_addr + 0x40000,STRIDE,WIDTH,HEIGHT,paddr);
    	ti810x_vpdma_send_list(list_addr + 0x40000, size, VPDMA_LIST_NUMBER_DVO2);	//list_no = 3	
    	
    	while (ti810x_dispmgr_wait_for_list_complete(1) == -1);
    	return 0;
    }
    
    U_BOOT_CMD(colorbar, 4, 1, do_color_bar,"Displays a color bar using HDVPSS","");
    U_BOOT_CMD(logo, 7, 0, do_boot_logo,"Displays a logo using HDVPSS",
    "on <logo_read_address> <final_BMP DSS read address> <VPDMA Descriptor address> <Display time in seconds> <Display fps (less than 60)> \n"
    "logo off");
    
    static int disp_logo(uint32_t *buffer)
    {
    	uint32_t  desc_buffer_base;
        uint32_t *firmware_addr;
        uint32_t *list_addr;
    	uint32_t *payload_buffer;
    	uint32_t size;
    	uint32_t disp_fps = 0;
    	uint32_t disp_time = 0;
    	uint32_t image_dest = 0;
    	uint32_t paddr;
    	/* VPDMA list number to use; please also check ISR */
    	int g_vpdma_list_no = 2;//VPDMA_LIST_NUMBER;
    
    	uint32_t grpx_unit = 1;
    
    
    	image_dest = (uint32_t)buffer;
    	disp_time = DEFAULT_BOOT_LOGO_DISPLAY_TIME_IN_SECS;
    	disp_fps = DEFAULT_BOOT_LOGO_DISPLAY_FPS;
    	
    
    	/* memory address for loading vpdma firmware and descriptors, payload */
    	desc_buffer_base = 0x82600000;//VPDMA_DESC_BUFFER_BASE ;
    
        firmware_addr    = (uint32_t*)(desc_buffer_base+VPDMA_DESC_FIRMWARE_OFFSET);
        payload_buffer   = (uint32_t*)(desc_buffer_base+VPDMA_DESC_PAYLOAD_OFFSET);
        list_addr        = (uint32_t*)(desc_buffer_base+VPDMA_DESC_LIST_OFFSET);
    
    	if(ti810x_prcm_init()  == -1)
    	{
    #ifdef DEBUG_VPSS
    		printf("\nERROR: ti814x_prcm_init failed");
    #endif
    		return -1;
    	}
    	if(ti810x_pll_init()  == -1)
    	{
    #ifdef DEBUG_VPSS
    		printf("\nERROR: ti814x_pll_init failed");
    #endif
    		return -1;
    	}
    	if(ti810x_vps_init()  == -1)
    	{
    #ifdef DEBUG_VPSS
    		printf("\nERROR: ti814x_vps_init failed");
    #endif
    		return -1;
    	}
    	if (ti810x_vpdma_load_firmware(firmware_addr) == -1)
    	{
    #ifdef DEBUG_VPSS
    		printf("\nERROR: vpdma_load_firmware failed");
    #endif
    		return -1;
    	}
    
    	/* destination address */
    	paddr = image_dest;
    
    	/* Allocate physical memory for MV data */
    	size = ti810x_dispmgr_create_grpx_conf_descriptor(grpx_unit, list_addr, payload_buffer,WIDTH,HEIGHT);
    	ti810x_vpdma_send_list(list_addr, size, g_vpdma_list_no);
    
           	/* wait for list complete interrupt */
    	if(ti810x_dispmgr_wait_for_list_complete(1) == -1)
    	{
    #ifdef DEBUG_VPSS
    		printf("\nERROR: wait for list complete FAILED!");
    #endif
    		return -1;
    	}
    
    	//vpdma_write32(VPDMA_GRPX0_DATA_CSTAT,0x00001C00);
    	vpdma_write32(VPDMA_GRPX1_DATA_CSTAT,0x00001C00);
    	//vpdma_write32(VPDMA_GRPX2_DATA_CSTAT,0x00001C00);
    
    	size = ti810x_dispmgr_setup_layers(list_addr, STRIDE, WIDTH, HEIGHT+60, disp_time, disp_fps, paddr);
    	printf("size = %d\n",size);
    	ti810x_vpdma_send_list(list_addr, size, g_vpdma_list_no);
    	while (ti810x_dispmgr_wait_for_list_complete(1) == -1);
    
    	if(ti810x_set_mode(1,WIDTH, HEIGHT, "on") == -1)
    	{
    #ifdef DEBUG_VPSS
    		printf("\nERROR: ti814x_set_mode failed");
    #endif
    		return -1;
    	}
    
    	return 0;
    }
    
    struct PICTUREINFO {
    	char	name[32];	/* ͼƬ������Ϣ�����ڲ鿴ͼƬ���� */
    	int		components;	/* ÿ���ص��Ӧ�ֽ��� */
    	int		width;		/* ͼƬ��ȣ�x�������ص���� */
    	int		height;		/* ͼƬ�߶ȣ�y�������ص���� */
    	void	*data;		/* ͼƬ���� */
    };
    
    
    
    int do_jpeg_test (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
    {
    	extern int decompress_jpeg_rgb(const void *picture_src, 
    		int picture_size, 
    		uint16_t maxWidth, 
    		uint16_t maxHeight, 
    		uint16_t fb_comps,
    		struct PICTUREINFO *picture);
    
    	uint16_t width;
    	uint16_t height;
    	int picsize;
    	
    	struct PICTUREINFO picture = {0};
    	picture.data = simple_strtoul (argv[2], NULL, 16);
    
    	picsize = simple_strtoul(argv[3], NULL, 10);
    	width = simple_strtoul(argv[4], NULL, 10);
    	height = simple_strtoul(argv[5], NULL, 10);
    	
    	printf("rgb to %x size = %d\n", picture.data, picsize);
    		
    	decompress_jpeg_rgb(
    		simple_strtoul(argv[1], NULL, 16), 
    		picsize, 
    		1600, 
    		1200, 
    		3, 
    		&picture
    		);
    
    	printf("picture info: %d %d %d\n", picture.components, picture.width, picture.height);
    
    	disp_logo(picture.data);
    	
    	return 0;
    }
    
    U_BOOT_CMD(
    	jpegtest, 6, 0, do_jpeg_test,
    	"\n",
    	"jpegtest src dst picsize width height "
    	);
    #endif
    
           5857.logo_814x.h

  • Hi Brijesh,
    Did you get the files ? Please let me know if anything incorrect in the code . Thanks for your help.~
  • Hi,

       I tried to config boot logo only on DVO2 (without HDMI and SD port), and I found that maybe VPDMA is not working correctly as setting.

    expeiment_1 :    as in the code :  HDMI->GRPX0 / DVO2->GPRX1.     Result : we get  junk logo.bmp data on DVO2.

    size = ti810x_dispmgr_create_grpx_conf_descriptor(0, list_addr, payload_buffer,WIDTH,HEIGHT);
    ti810x_vpdma_send_list(list_addr, size, 0);//last param 0, list number hardcoded for HDMI->VGA
    size = ti810x_dispmgr_create_grpx_conf_descriptor(1, list_addr + 0x40000, payload_buffer + 0x10,WIDTH,HEIGHT);
    ti810x_vpdma_send_list(list_addr + 0x40000, size, 1);//last param 1, list number hardcoded for DVO2
    vpdma_write32(VPDMA_GRPX0_DATA_CSTAT,0x00000000);// Hardcoded: HDMI(+VGA)->GRPX0
    vpdma_write32(VPDMA_GRPX1_DATA_CSTAT,0x00000400);// Hardcoded: DVO2->GRPX1
    size = ti810x_dispmgr_setup_layers(list_addr,STRIDE,WIDTH,HEIGHT,disp_time,disp_fps,paddr);
    ti810x_vpdma_send_list(list_addr, size, VPDMA_LIST_NUMBER_HD); //list_no = 4
    size = ti810x_dispmgr_setup_layers_DVO2(list_addr + 0x40000,STRIDE,WIDTH,HEIGHT,disp_time,disp_fps,paddr);
    ti810x_vpdma_send_list(list_addr + 0x40000, size, VPDMA_LIST_NUMBER_DVO2); //list_no = 3

    expeiment_2 :    DVO2->GPRX1 Only.             Result : we get BackGround Color on DVO2.

    //size = ti810x_dispmgr_create_grpx_conf_descriptor(0, list_addr, payload_buffer,WIDTH,HEIGHT);
    //ti810x_vpdma_send_list(list_addr, size, 0);//last param 0, list number hardcoded for HDMI->VGA
    size = ti810x_dispmgr_create_grpx_conf_descriptor(1, list_addr + 0x40000, payload_buffer + 0x10,WIDTH,HEIGHT);
    ti810x_vpdma_send_list(list_addr + 0x40000, size, 1);//last param 1, list number hardcoded for DVO2
    //vpdma_write32(VPDMA_GRPX0_DATA_CSTAT,0x00000000);// Hardcoded: HDMI(+VGA)->GRPX0
    vpdma_write32(VPDMA_GRPX1_DATA_CSTAT,0x00000400);// Hardcoded: DVO2->GRPX1
    //size = ti810x_dispmgr_setup_layers(list_addr,STRIDE,WIDTH,HEIGHT,disp_time,disp_fps,paddr);
    //ti810x_vpdma_send_list(list_addr, size, VPDMA_LIST_NUMBER_HD); //list_no = 4
    size = ti810x_dispmgr_setup_layers_DVO2(list_addr + 0x40000,STRIDE,WIDTH,HEIGHT,disp_time,disp_fps,paddr);
    ti810x_vpdma_send_list(list_addr + 0x40000, size, VPDMA_LIST_NUMBER_DVO2); //list_no = 3

    expeiment_3 :    DVO2->GPRX1 and set conf_desc for HDMI             Result : we get  junk logo.bmp data on DVO2,  just as experiment_1

    size = ti810x_dispmgr_create_grpx_conf_descriptor(0, list_addr, payload_buffer,WIDTH,HEIGHT);
    ti810x_vpdma_send_list(list_addr, size, 0);//last param 0, list number hardcoded for HDMI->VGA
    size = ti810x_dispmgr_create_grpx_conf_descriptor(1, list_addr + 0x40000, payload_buffer + 0x10,WIDTH,HEIGHT);
    ti810x_vpdma_send_list(list_addr + 0x40000, size, 1);//last param 1, list number hardcoded for DVO2
    //vpdma_write32(VPDMA_GRPX0_DATA_CSTAT,0x00000000);// Hardcoded: HDMI(+VGA)->GRPX0
    vpdma_write32(VPDMA_GRPX1_DATA_CSTAT,0x00000400);// Hardcoded: DVO2->GRPX1
    //size = ti810x_dispmgr_setup_layers(list_addr,STRIDE,WIDTH,HEIGHT,disp_time,disp_fps,paddr);
    //ti810x_vpdma_send_list(list_addr, size, VPDMA_LIST_NUMBER_HD); //list_no = 4
    size = ti810x_dispmgr_setup_layers_DVO2(list_addr + 0x40000,STRIDE,WIDTH,HEIGHT,disp_time,disp_fps,paddr);
    ti810x_vpdma_send_list(list_addr + 0x40000, size, VPDMA_LIST_NUMBER_DVO2); //list_no = 3

    It seems that  VPDMA get wrong desciptor from DDR , which make it working incorrectly.

    (I have checked the desc on ddr , they are set correctly as in the code without address conflict )

    How can I check VPDMA ?  Thansk very much

  • Brijesh,

    Customer simplified the use case to only display GRPX0 content on DVO2 as below. (The code is based the latest one on git)

          size = ti810x_dispmgr_create_grpx_conf_descriptor(0, list_addr+0x40000, payload_buffer+0x10,WIDTH,HEIGHT);
          ti810x_vpdma_send_list(list_addr+0x40000, size, 1);
          vpdma_write32(VPDMA_GRPX0_DATA_CSTAT,0x00000000);
         size = ti810x_dispmgr_setup_layers_DVO2(list_addr+0x40000,STRIDE,WIDTH,HEIGHT,disp_time,disp_fps,paddr);  /* enable Grpx0 for COMP_DVO2; vpdma_chan = 29 */
          ti810x_vpdma_send_list(list_addr+0x40000, size, VPDMA_LIST_NUMBER_DVO2);

    But the result is still no correct as below and the output on display is flickering. The content of RGB (1280x720) for GRPX0 is 255 0 0 (red).

    Would you pls give more suggestion on how to debug this issue?

  • Brijesh,

    After removing the comment on below code in yellow, now there is correct output on DVO2.

    Do you know why the code on git comment below code in yellow?

    /**
     * Configure PLL for HDVPSS unit
     */
    static int ti810x_pll_config_hdvpss()
    {
        uint32_t rd_osc_src;
        rd_osc_src = pll_read32(PLL_VIDEO2_PINMUX);
        rd_osc_src &= 0xFFFFFFFE;
        #ifdef CONFIG_MACH_TI814XDVR
        rd_osc_src |= (1<<24); // select the vout0 clock source the same as hdmi source
        #endif
        pll_write32(PLL_VIDEO2_PINMUX,rd_osc_src);
        //ti810x_pll_configure(PLL_HDVPSS_BASE,19,800,4,0x00000801);

        return 0;
    }

  • Hello Chris,

    May be because the default output mode for all VENCs is D1, so PLL configuration for 720p is commented out.

    Regards,

    Brijesh