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The influence of AM3874 when tRPRE and tRPST cannot satisfy specifications?

shigehiro tsuda
Mastermind 9490 points
Other Parts Discussed in Thread: AM3874

Hi,

It is the question about specifications of DDR2 connecting with AM3874.
tRPRE and tRPST are defined in a timing of DQS in READ of the DDR(AM3874 catches it a side) .
When width of this tRPRE and tRPST do not slightly satisfy the specification, what kind of problem occurs in AM3874?

Best Regards,
Shigeiro Tsuda

  • 0
    TI__Guru**** 393215 points
    Moving this to the AM387x forum.
  • 0
    TI__Guru**** 170625 points
    Hi Shigeiro,

    Where are these tRPRE/tRPST parameters documented? I checked AM387x documentation (datasheet, TRM) and I can not find such parameters?

    Do you ask regarding external DDR2 chip tRPRE/tRPST parameters? If yes, what is the relation with AM387x device? I mean if you need to know more details regarding DDR2 chip parameters (which are documented in DDR2 chip datasheet), why you ask in AM387x forum and not DDR2 chip supplier?

    Regards,
    Pavel
  • 0 in reply to Pavel Botev
    Mastermind 9490 points
    Hi Pavel,

    Thank you for quick reply.
    It is not written in data sheet and TRM in a timing of DDR2 of AM3874.
    Because it is written that the controller of DDR2 is based on a standard of JESD79-2E, I confirm the document.

    Best Regards,
    Shigehiro Tsuda
  • 0 in reply to shigehiro tsuda
    TI__Guru**** 170625 points
    Shigehiro,

    I confirm AM387x DDR memory controller supports JEDEC standard compliant DDR2 SDRAM external chips. For more details see AM387x datasheet, section 9.13.4.1.1.2 Compatible JEDEC DDR2 Devices

    Regards,
    Pavel
  • 0 in reply to Pavel Botev
    Mastermind 9490 points

    Hi Pavel,

    Thank you for quick reply.

    A compliance test of DDR2 in our customers does fail.
    Please tell me whether a problem occurs in a wave pattern of the input of AM3874.

    In the case of a problem, what kind of situation will occur it?
    Or please tell me if there is a solution by the setting of the register.

    Best Regards,
    Shigehiro Tsuda

  • 0 in reply to shigehiro tsuda
    TI__Guru**** 170625 points

    Shigehiro,

    tRPRE parameter is documented in external DDR2 chip documentation, thus you should check with the DDR2 chip supplier for more info regarding this parameter.

    Regarding AM387x DDR2 controller, I can not find register that will control that parameter tRPRE. There are registers that control other parameters like tRP, tRCD, tWR, tRAS, tCKE etc (see AM387x TRM, registers SDRTIM1/2/3).

    On all silicon revisions, DDR2 and DDR3 requires software leveling to tune the device I/Os to the timing characteristics of a particular board design. Hardware leveling is not supported.  

    Software leveling is a procedure by which the time delays between DDR2/3 signals can be compensated by appropriate values programmed in the corresponding slave ratio registers of the DDR PHY.

    For details on software leveling, see the below wiki page and AM387x TRM, section 7.2.8 DDR3 Software Write/Read Leveling

    See also the below document:

    DDR App Note_v05.pdf

    Regards,
    Pavel

  • 0 in reply to Pavel Botev
    Mastermind 9490 points
    Hi Pavel,

    Thank you for quick reply.
    Our customer thinks with the influence with the design of the board.
    They have already executed software leveling and can read and write the data normally.
    Because the DDR2 compliance test does fail, our customer seems to mind it whether there is a problem in the controller of the DDR2 of AM3874.
    Can a timing of this tRPRE determine whether there is a problem?

    Best Regards,
    Shigehiro Tsuda
  • 0 in reply to Pavel Botev
    Mastermind 9490 points
    Hi Pavel,

    Thank you for quick reply.
    Our customer thinks with the influence with the design of the board.
    They have already executed software leveling and can read and write the data normally.
    Because the DDR2 compliance test does fail, our customer seems to mind it whether there is a problem in the controller of the DDR2 of AM3874.
    Can a timing of this tRPRE determine whether there is a problem?

    Best Regards,
    Shigehiro Tsuda
  • 0 in reply to shigehiro tsuda
    TI__Guru**** 170625 points
    Shigehiro,

    I have found two e2e threads which discuss DDR compliance test, have a look:
    e2e.ti.com/.../413018
    e2e.ti.com/.../482267

    In short:
    - try with invert_clkout=1
    - try with lower DDR2 frequency
    - check DDR PLL settings

    You can provide me your DDR PLL settings and main oscillator (OSC0) frequency, I will make double check.

    You can also run DDR memory stress test (which involves the EDMA), I can provide you the below pointers:

    processors.wiki.ti.com/.../Sitara_Linux_Training:_Tuning_the_DDR3_Timings_on_BeagleBoneBlack

    e2e.ti.com/.../1046142
    e2e.ti.com/.../1067409

    You can try to adjust this DDR test for your custom board.

    Regards,
    Pavel
  • 0 in reply to Pavel Botev
    Mastermind 9490 points
    Hi Pavel ,

    Thank you for much information.
    Would a wave pattern doing fail mentioned above confirm it whether there is a problem?
    Because a margin is thought that there is it in the control side by the maker of DDR2 of the customer, there seems to be an answer thought not to have any problem.
    When tRPRE is input across MAX, what kind of phenomenon will happen?
    Example)
    DDR2 controller of AM3874 is not readable.
    A timing to read becomes late.

    Best Regards,
    Shigehiro Tsuda
  • 0 in reply to shigehiro tsuda
    TI__Guru**** 170625 points
    Hi Shigehiro,

    AM387x DDR2/3 memory controller supports JEDEC standard-compliant DDR2 and DDR3 devices. If this tRPRE parameter value is not in conflict with the JEDEC DDR2 requirements, then no problem is expected with the AM387x DDR2/3 memory controller.

    Regards,
    Pavel