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Linux/AM3874: The value to be set of HD_VENC_CFG17 and HD_VENC_D_CFG23 of AM3874 ?

shigehiro tsuda
Mastermind 9490 points
Part Number: AM3874

Tool/software: Linux

Hi,

There is no mention of the information of the register of HD_VENC_D_XXX in TRM(sprugz7e.pdf) of AM3874.
In TRM(sprugz8g.pdf) of DM8148, explanation of OSD_AVD_VW1 bit of the register of HD_VENC_D_cfg23 has following mentions.
Defines the number of active lines for the input frame (or first field) of the HD_VENC_D.
Normally, this should be same as DVO_AVD_VW1.

Does the condition mentioned above apply to it in AM3874?

When OSD_AVD_VW1 is not same as DVO_AVD_VW1, a flag is set in underflow status bit of the clkc_underflow register.
When it is the same, the flag is not set in underflow status bit of the clkc_underflow register.
In the case of ezsdk of linux, a different value is set in it, and a flag of bit is set.

Should these registers usually make the same setting as use?

Best Regards,
Shigehiro Tsuda

  • 0
    TI__Guru**** 393215 points
    Moving this to the AM387x forum.
  • 0
    TI__Guru**** 170625 points
    Hi Shigehiro,

    The AM387x HDVPSS is documented in separate document, DM814x HDVPSS User's Guide (SPRUHF7B.pdf), see section 1.2.7 High-Definition Video Encoder (HD_VENC). Note that this document is available only through local TI FAE and under NDA. Meanwhile you can have a look in the DM38x version which is public:

    www.ti.com/.../spruhi7a.pdf

    Note that we have linux driver which is used to configure HDVPSS registers, we do not recommend configuring these registers directly. We recommend you to use the VPSS linux driver and configure HDVPSS registers through sysfs entries. See the below links for more info:

    processors.wiki.ti.com/.../TI81XX_PSP_VPSS_Video_Driver_User_Guide
    processors.wiki.ti.com/.../TI811X-HDVPSS-01.00.01.44_Feature_Performance_Guide
    processors.wiki.ti.com/.../TI81XX_PSP_VIDEO_CAPTURE_Driver_User_Guide
    e2e.ti.com/.../547907

    Regards,
    Pavel
  • 0 in reply to Pavel Botev
    Mastermind 9490 points

    Hi Pavel,

    Thank you for quick reply.

    I confirm by the ti-ezsdk_dm814x-evm_5_05_02_00.

    A different value is set when I dump these registers after displaying the graphic(matrix gui ) using the default linux kernel of ezsdk.

    DVO_AVD_VW1:768
    OSD_AVD_VW1:769

    The flag of underflow status bit of the clkc_underflow register is set immediately even if I clear this bit.

    There is following mention in TRM, and please tell me it whether DVO_AVD_VW1 and OSD_AVD_VW1 must be set to the same value.

    In TRM(sprugz8g.pdf) of DM8148, explanation of OSD_AVD_VW1 bit of the register of HD_VENC_D_cfg23 has following mentions.
    Defines the number of active lines for the input frame (or first field) of the HD_VENC_D.
    Normally, this should be same as DVO_AVD_VW1.

    There is a similar mention in spruhi7a introduced by you.

    Best Regards,
    Shigehiro Tsuda

  • 0 in reply to shigehiro tsuda
    TI__Guru**** 170625 points
    DVO_AVD_VW1 defines the number of active video lines in a frame.

    You can try also with ti-ezsdk_dm814x-evm_5_04_00_11, this is the last version tested on AM387x device.

    You can also compare these registers at u-boot level, see u-boot/drivers/video/ti814x_logo.c

    As stated before, we suggest that the customer references the Linux drivers for more information since we are not really able to provide much more support beyond our drivers. Could you please describe what is the main issue you have and what steps you are using to configure the Linux driver?

    Regards,
    Pavel
  • 0 in reply to Pavel Botev
    Mastermind 9490 points
    Hi Pavel,

    Thank you for quick reply.
    I under stand that DVO_AVD_VW1 defines the number of active video lines in a frame.
    Is the number of active video lines in a frame defined the OSD_AVD_VW1 setting value.
    Please tell me how it is defined.

    Best Regards,
    Shigehiro Tsuda
  • 0 in reply to shigehiro tsuda
    TI__Guru**** 170625 points
    OSD_AVD_VW1 defines the number of active lines for the input frame (or first field) of the HD_VENC_D. See how OSD_AVD_VW1 is used in u-boot
  • 0 in reply to Pavel Botev
    TI__Guru**** 170625 points
    See also vpss.c file, where both dvo_avd_vw1 and osd_avd_vw1 are used:

    LCD_VPSS_Config(void) {
    // Configure the VOUT0 VPSS registers

    WR_MEM_32(DVO2_CFG17,
    ((0x247 << 0) | // dvo_avst_v2: 583
    (0x21C << 12)));// dvo_avd_vw1: 540


    WR_MEM_32(DVO2_CFG23,
    ((0x247 << 0) | // osd_avst_v2: 583
    (0x21C << 12)));// osd_avd_vw1: 540
    }

    vpss.c file is located in the Mistral Solution package, IO EXPANSION BOARD\ Rev D/src/CCS_Test_Code/IOExpansion_Application/lcd_display/vpss.c
  • 0 in reply to Pavel Botev
    TI__Guru**** 170625 points

    We also have info regarding OSD_AVD_VW1 in the hdvpss source:

    ti-ezsdk_dm814x-evm_5_05_02_00/component-sources/hdvpss_01_00_01_44/packages/ti/psp/vps/hal/vpshal_hdvenc.h

    UInt16 activeVideoLines0;
    /**< OSD_AVD_VW1: Defines the number of active lines in a frame; In interlace mode, it defines the number of active lines in the first field. */

    UInt32 activeVideoLines0;
    /**< DVO_AVD_VW1: In progressive mode, it defines the number of active video lines in a frame. In interlace mode, it defines the number of active lines in the first field.*/

    ti-ezsdk_dm814x-evm_5_05_02_00/component-sources/hdvpss_01_00_01_44/packages/ti/psp/vps/hal/src/vpshal_hdvenc.c

    regsOvly->CFG23 = 0;
    regsOvly->CFG23 = ((oCfg->activeLineStart1 <<
    CSL_VPS_HD_VENC_A_CFG23_OSD_AVST_V2_SHIFT) &
    CSL_VPS_HD_VENC_A_CFG23_OSD_AVST_V2_MASK) |
    ((oCfg->activeVideoLines0 <<
    CSL_VPS_HD_VENC_A_CFG23_OSD_AVD_VW1_SHIFT) &
    CSL_VPS_HD_VENC_A_CFG23_OSD_AVD_VW1_MASK) |
    ((mCfg->mv450mvAgcPulseXSection <<
    CSL_VPS_HD_VENC_A_CFG23_P_450MV_SHIFT) &
    CSL_VPS_HD_VENC_A_CFG23_P_450MV_MASK);

    oCfg->activeVideoLines0 = ((regsOvly->CFG23 &
    CSL_VPS_HD_VENC_A_CFG23_OSD_AVD_VW1_MASK)
    >> CSL_VPS_HD_VENC_A_CFG23_OSD_AVD_VW1_SHIFT);

    #define CSL_VPS_HD_VENC_D_CFG23_OSD_AVD_VW1_MASK (0x00FFF000u)

    #define CSL_VPS_HD_VENC_D_CFG23_OSD_AVD_VW1_SHIFT (0x0000000Cu)

    Regards,
    Pavel

  • 0 in reply to Pavel Botev
    Mastermind 9490 points
    Hi Pavel ,

    Thank you for quick reply.

    I confirmed ti814x_logo.c of u-boot.

    DVO_AVD_VW1:
    /* bp_pk_h (back porch peak), vout_avst_vw (num active lines), vout_avst_v1 (active video start field 2) */
    __raw_writel((vtotal << 12), cfg_reg_base + 0x44);
    case 1080P
    vtotal=1125

    OSD_AVD_VW1:
    /* osd_avd_vw1 (number of active lines), osd_avst_v2 (first active line in 2nd field) */
    __raw_writel((vdisp << 12), cfg_reg_base + 0x5c);
    case 1080P
    vdisp=1080

    DVO_AVD_VW1 and OSD_AVD_VW1 are the different setting.

    1.The sample of BSP is the same setting.
    2.linux is different setting.
    3.u-boot is different setting.

    Which is right setting?

    Best Regards,
    Shigehiro Tsuda
  • 0 in reply to shigehiro tsuda
    TI__Guru**** 398420 points
    Both of these fields are essentially used for configuring number of active lines in OSD or DVO outputs. So they should be same. BSP drivers always configures them correctly.

    Regards,
    Brijesh
  • 0 in reply to Brijesh Jadav
    Mastermind 9490 points

    Hi Brijesh,

    Thank you for quick reply.

    I understood that the setting of DVO_AVD_VW1 must be the same as OSD_AVD_VW1.

    Best Regards,
    Shigehiro Tsuda

  • 0 in reply to shigehiro tsuda
    TI__Guru**** 398420 points
    Please close thread if your question is answered.

    Rgds,
    Brijesh