This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
Tool/software: Linux
I sent the pointer to the A8 core using shared memory region Syslink. The data i store from dsp or A8 can be read on either of the core , But as soon as i mmap it i am not able to read data from one core and see the update on other core.
Hi,
Could you tell me a few more details?
-The data store, is it in a retained section of memory? cache aligned? (for both ARM and DSP)
-If mmap from linux to the physical address, are you setting the O_SYNC bit?
-Is the DSP core still running when you attempt the read? or has it finished its processing? I've seen the memory get overwritten or reset when a DSP exits its tasks. I solve this by either having a while(1) at the end of the code for debugging when I have a short running application.
-Dan
Hi Dan,
Thank You for the reply ,
I am actually new to this , i am attaching my DSP cnfg file and Changes i did in frmware loader file.
I actually disable the cache in that shared region. i am using pointer at 0x96C00000.
Yes, i tried with O_SYNC Bit but the result was the same.
Yes i added the breakpoint in the end of DSP task before so it doesnt get finished after performing processing.
What i am doing is i am initializing a pointer array at DSP side with address in shared region ,
and sending it to A8 with Some values , till this point i am able to see the updates from both side.
As soon as i mmap the pointer to Fb0 , and read from a8 side all values are zero , but DSP shows me the previous value .
Then i change the value from A8 and print the buffer and it gets updated on A8 side , but DSP values remain the same.
Please if You can help me with this , i am searching for solution from long time . If You can share your Sample files with me may be it will help .
BR
Ammar Zafar
/*
* Copyright (c) 2010-2011, Texas Instruments Incorporated
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* Contact information for paper mail:
* Texas Instruments
* Post Office Box 655303
* Dallas, Texas 75265
* Contact information:
* http://www-k.ext.ti.com/sc/technical-support/product-information-centers.htm?
* DCMP=TIHomeTracking&HQS=Other+OT+home_d_contact
* ============================================================================
*
*/
/**
* @file memsegdef.c
*
* @brief Memory map segment definitions, This is auto generated file
*
*
*
* @ver 0.1
*
* ============================================================================
*/
/*----------------------------- Memory Segment configuration -----------------*/
#include <ldr_memseg.h>
uint32_t ldrmemcfg_ddrSize = LDR_DDR_SIZE_512M ;
LDR_MemSeg sdk_memseg_default[] =
{
/* Segment 0 */
{
1, /* valid */
"IPC_SR_VIDEO_M3_VPSS_M3", /* name */
0x00100000, /* size */
LDR_SEGMENT_TYPE_DYNAMIC_SHARED_HEAP, /* LDR_SEGMENT_TYPE_DYNAMIC_SHARED_HEAP,
seg_type */
0, /* flags */
0x9A100000, /* system_addr */
0x9A100000, /* slave_virtual_addr */
LDR_CORE_ID_A8, /* master_core_id */
((1 << LDR_CORE_ID_VM3) | (1 << LDR_CORE_ID_DM3) | (1 << LDR_CORE_ID_A8)),
/* core_id_mask */
((1 << LDR_CORE_ID_VM3) | (1 << LDR_CORE_ID_DM3)),
/* cache_enable_mask */
0, /* cache_operation_mask */
1 /* shared_region_id */
},
/* Segment 1 , Temporarily used by VFPC internal buff heap */
{
1, /* valid */
"VPSS_M3_INT_HEAP_CACHED", /* name */
0x01B00000, /* size */
LDR_SEGMENT_TYPE_DYNAMIC_LOCAL_HEAP, /* seg_type */
0, /* flags */
0x9A200000, /* system_addr */
0x9A200000, /* slave_virtual_addr */
-1, /* master_core_id */
(1 << LDR_CORE_ID_DM3), /* core_id_mask */
0, /* cache_enable_mask */
0, /* cache_operation_mask */
-1 /* shared_region_id */
},
/* Segment 2 , Temporarily used by VFPC internal buff heap */
{
1, /* valid */
"VIDEO_M3_INT_HEAP_CACHED", /* name */
0x02000000, /* size */
LDR_SEGMENT_TYPE_DYNAMIC_LOCAL_HEAP, /* seg_type */
0, /* flags */
0x9BD00000, /* system_addr */
0x9BD00000, /* slave_virtual_addr */
-1, /* master_core_id */
(1 << LDR_CORE_ID_VM3), /* core_id_mask */
1, /* cache_enable_mask */
0, /* cache_operation_mask */
-1 /* shared_region_id */
},
/* Segment 3 */
{
1, /* valid */
"IPC_SR_FRAME_BUFFERS", /* name */
0x0BC00000, /* size */
LDR_SEGMENT_TYPE_DYNAMIC_SHARED_HEAP, /* seg_type */
0, /* flags */
0xAB000000, /* system_addr */
0xAB000000, /* slave_virtual_addr */
LDR_CORE_ID_A8, /* master_core_id */
(1 << LDR_CORE_ID_VM3) | (1 << LDR_CORE_ID_DM3) | (1 << LDR_CORE_ID_A8) | (1 << LDR_CORE_ID_DSP),
/* core_id_mask */
(1 << LDR_CORE_ID_VM3) | (1 << LDR_CORE_ID_DM3) | (1 << LDR_CORE_ID_DSP), /* cache_enable_mask */
(1 << LDR_CORE_ID_VM3) | (1 << LDR_CORE_ID_DM3) | (1 << LDR_CORE_ID_DSP), /* cache_operation_mask
*/
2 /* shared_region_id */
},
/* Segment 4 */
{
1, /* valid */
"DSP_ALG_HEAP", /* name */
0x01400000, /* size */
LDR_SEGMENT_TYPE_DYNAMIC_LOCAL_HEAP, /* seg_type */
0, /* flags */
0x98000000, /* system_addr */
0x98000000, /* slave_virtual_addr */
LDR_CORE_ID_DSP, /* master_core_id */
(1 << LDR_CORE_ID_DSP), /* core_id_mask */
(1 << LDR_CORE_ID_DSP), /* cache_enable_mask */
(1 << LDR_CORE_ID_DSP), /* cache_operation_mask */
-1 /* shared_region_id */
},
{
1, /* valid */
"A8_DSP_CMEM", /* name */
0x1400000, /* 20MB-size */
LDR_SEGMENT_TYPE_DYNAMIC_SHARED_HEAP, /* seg_type */ // Making it Shared useable.
0, /* flags */
0x96C00000, /* system_addr */
0x96C00000, /* slave_virtual_addr */
LDR_CORE_ID_A8, /* master_core_id */
(1 << LDR_CORE_ID_A8) | (1 << LDR_CORE_ID_DSP), /* core_id_mask */
(1 << LDR_CORE_ID_A8) | (1 << LDR_CORE_ID_DSP), /* cache_enable_mask */
0, /* cache_operation_mask */ //Disable Cache
3 /* shared_region_id */
},
/* Last Segment, Marked by valid flag to 0 */
{
0,
},
};
/* End Of File */