• State Resolved
  • Locked Locked
  • Replies 3 replies
  • Answers 1 answer
  • Subscribers 101 subscribers
  • Views 524 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS320DM8148: Turning on the cache of M3

Ali Khalid
Prodigy 30 points
Part Number: TMS320DM8148
Other Parts Discussed in Thread: CCSTUDIO

Dear TI experts, 

I am using DM814 processor and I am trying to turn on the cache of cortex M3 core. What I have seen is that there is a sys/bios support for it but I do not want to use that. After referring to the TRM of cortex M3(ARM®v7-M Architecture), I have seen that I can control all MMU, D cache and I cache using a register "configuration and control register". Now, however it is a RW register, I am unable to write to it as it does not change it's value. 

Is there something I am doing wrong? Is there any Gel file enabling/disabling the cache of M3 core

Thanks

  • 0
    TI__Guru**** 170625 points
    Hi Ali,

    How you define that M3 cache is disabled by default?

    Which register exactly you are trying to write? What value? At which physical address? Do you try to access that register with JTAG and CCStudio?

    See if the below pointers will be in help:

    e2e.ti.com/.../193165
    e2e.ti.com/.../505217

    DM814x_PG2.x.gel - see DucatiClkEnable()

    syslink_bios_omap4_DM814x.gel - see InitAMMU()

    Regards,
    Pavel
  • 0 in reply to Pavel Botev
    TI__Prodigy 30 points

    Hello Pavel,

    As I said I am using the ARM®v7-M Architecture document for reference as Cortex M3 follows that architecture. It states in there that on reset all caches are disabled.  I am using configuration and control register as referenced in that guide and yes I am trying to access it using JTAG and CCStudio. 

     and it has a physical address 0xE000ED14 as shown in pictures below

    Best Regards,

    Ali

  • 0 in reply to Ali Khalid
    TI__Guru**** 170625 points
    Ali,

    Regarding ARM documentation questions, you should check with ARM support team.

    Regarding DM814x device, 0xE000ED14 is part of the DDR3 memory, this is not Cortex-M3 register address, check DM814x memory map.

    Regards,
    Pavel