Hi all and thanks in advance at who wants to help us.
We released a module based on TMS320DM8148 processor. After some production batches without significant problems, in last lot we had some modules that not establish the link with SATA devices, even using 1.5GBps speed.
SATA is using the 20MHz clock as a source for the link. We have a 100MHz clock connected to SERDES pins, but using with this clock, the SATA interface is not working at all and ETH on EMAC1 hangs.
Comparing 2 module (clocked with the 20MHz source), one with working SATA and one with not working interface, we can see some differences value for some PLL related registers.
PCIE_PLLSTATUS moves from 0x0000F8CD to 0x0000F84D, wich means that VTUNESTS change value from 4 to 12.
SATA_PLLSTATUS moves from 0x0000900D to 0x0000F00D, which means that some of the reserved area value of the register was different.
All *_CLKCTRL (i.e. PLL_DSP_CLKCTRL,PLL_SGX_CLKCTRL, etc) register are different for NWELLTRIM value.
Can someone help us to better understand what those registers mean exactly? In the documentation, there are no details for this values.
We can't find any other issue or difference between 2 modules that can explain where is the problem.