• TI Thinks Resolved

TMS320DM8148: Spurious interrupt handling

Part Number: TMS320DM8148

We are using an real time OS on TMS320DM8148 on the ARM side and using sysbios on DSP side.

The ARM IRQ handler sometime get spurious interrupt, but we do not know how the handler shall handle it.

Initially we try to ignore it and just return, but it seems the INT is not cleared and keep firing.

Then we try to handle it normally but the vector is wrong (0x7f) which is not used in our system, causing unhandled INT error.

So what is the proper way to handle spurious IRA for DM814x device?


  • This is from TRM:

    14.3.5 ARM A8 INTC Spurious Interrupt Handling
    The spurious flag indicates whether the result of the sorting (a window of 10 INTC functional clock cycles
    after the interrupt assertion) is invalid. The sorting is invalid if:
    • The interrupt that triggered the sorting is no longer active during the sorting.
    • A change in the mask has affected the result during the sorting time.
    As a result, the values in the INTCPS_MIRn, INTCPS_ILRm, or INTCPS_MIR_SETn registers must not be
    changed while the corresponding interrupt is asserted. Only the active interrupt input that triggered the
    sort can be masked before it turn on the sort. If these registers are changed within the 10-cycle window
    after the interrupt assertion. The resulting values of the following registers become invalid:
    This condition is detected for both IRQ and FIQ, and the invalid status is flagged across the
    SPURIOUSIRQFLAG (see NOTE 1) and SPURIOUSFIQFLAG (see NOTE 2) bit fields in the SIR and
    PRIORITY registers. A 0 indicates valid and a 1 indicates invalid interrupt number and priority. The invalid
    indication can be tested in software as a false register value.
  • In reply to Zhigang Liu:

    Hi Liu,

    Yes, DM814x TRM (section 14.3.5) should be followed regarding Spurious Interrupt Handling. See also if the below e2e threads will be in help: