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TI Home » TI E2E Community » Support Forums » Digital Signal Processors (DSP) » DaVinci™ Video Processors » DM816x, C6A816x and AM389x Processors Forum » fbset in triple buffering usage
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fbset in triple buffering usage

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Daniel70334
Posted by Daniel70334
on May 10 2012 15:35 PM
Expert1055 points

We have DM816x and DM814x EVMs in-house for our current project.  I've been looking into things that need to be changed when the output resolution changes on-the-fly, including the frame buffer setup.  I have a basic question about this line from /etc/init.d/pvr-init in the EZSDK:

# Try to enable triple buffering when there's enough VRAM
fbset -vyres $(expr $YRES \* 3)

I haven't been able to find any explanations as to how setting the fbdev's virtual yres enables triple buffering.  Is this an OpenGL thing?  A Qt thing?  Is the EZSDK's matrix app doing something special when vyes is a multiple of yres?

816x 816X example 8168 EZSDK 8168 evm
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  • Prathap Srinivas
    Posted by Prathap Srinivas
    on May 10 2012 17:08 PM
    Verified Answer
    Verified by Daniel70334
    Expert4050 points

    Hi Daniel,

    Setting FLIP mode in /etc/powervr.in leads to the ping ping-pong scheme being used for graphics(openGLES) updates. The numbe of buffers created depends on the vram size allocated in bootargs.

    When using Front mode in /etc/powervr.ini, SGX fb updates happen directly on single framebuffer (front buffer). Not really recommended except for SGX benchmarking as it will result tearing artifacts at high resolution and frame rates.

    Setting flip mode in /etc/powervr.ini,  uses ping-pong scheme for graphics updates and this is the default EGL library used if /etc/powervr.ini is not present.

    Modify the powervr.ini file under the <your_target_file_system>/etc to select between the FrontEGL or FlipEGL mode.

    Flip support requires increasing the virtual yres size in fb0 plane and allocating appropriate memory for framebuffer.

    Hence fbset command may be used to increase the virtual yres size in fb0 plane. The vyres size needs to be set to three times the height of the screen size for triple buffering.

    Please go through below links for more details if required -

    http://processors.wiki.ti.com/index.php/GSG:_OMAP35x_Graphics_SDK_Additional_Procedures#Switching_between_FrontEGL_and_FlipEGL_Modes

    http://processors.wiki.ti.com/index.php/SGXDbg#WindowSystem

    Thanks,

    Prathap.

    If my reply answers your question then please click on the "Verify Answer" button.

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  • Daniel70334
    Posted by Daniel70334
    on May 10 2012 17:41 PM
    Expert1055 points

    Prathap,

    Got it.  Thanks for the prompt reply, and the references.

    Dan -

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