We're using the DM8168 in a new design and want to make use of the ability to swap DQ data bits within a byte lane to make the PCB routing easier.
The flight time levelling aspect of DDR3 means that one bit in each byte (the prime) bit carries info during the levelling process, but the DDR3 spec does not specify which bit this will be. This implies that a DDR3 memory controller which aims to work with DDR3 components from all vendors will have to discover which bit which is prime on each board.
I understand that the DM816x doesn't fully support the hardware levelling algorithm in the Rev 1.1 and Rev 2.0 silicon versions, but does the replacement software levelling algorithm have any sensetivity to which bit is the prime bit?
There is a discussion of this issue for the DM814x on this thread, but my question is specific to the software levelling:
http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/716/p/160641/660439.aspx
Thanks
James
Hi James,
You can find the DDR3 initialization details with SW leveling at
http://processors.wiki.ti.com/index.php/DM816x_C6A816x_AM389x_DDR3_Init
Regards
AnilKumar
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The page you referred to looks like it describes what we need to do to run the levelling algorithm, but it doesn't describe much about the algorithm itself.
I'm concerned that since the DM8168 eval board uses micron memory and doesn't swap any pins that the algorithm might be specific to that setup. The micron memory parts output their levelling info (prime DQ) on DQ0 and so if the algorithm was expecting the information to be on DQ0, then our design might not work since we haven't mapped DQ0 on the memory to DQ0 on the DM8168.
Can you confirm whether the SW levelling searches all DQs for the prime DQ or not?
Is this likely to change in a future revision of the device if hardware levelling is implemented?
James.