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TI Home » TI E2E Community » Support Forums » Digital Signal Processors (DSP) » DaVinci™ Video Processors » DM816x, C6A816x and AM389x Processors Forum » questions about PLL parameters
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questions about PLL parameters

questions about PLL parameters

This question is not answered
mastupristi
Posted by mastupristi
on May 03 2012 05:49 AM
Intellectual800 points

I have some questions about PLL parameters.

 First of all I refer to PLL scheme:

 

The output frequency is given by:

 

The questions are:

  • Range of N? In reference manual is stated that “N = Multiplier is 9 bits and supported range is 1 to 511”, but in register description the field is 16 bits wide. I wonder if N is 9 or 16 bit wide.
    I wonder how to set the N field once I want to multiply by a certain value. For example, take into account Audio PLL. Maybe the value of N is equal to AUDIO_N+1 where AUDIO_N is bits 31-16 of AUDIOPLL_CTRL register. For example if I want to multiply by 34, do I need to write 33 o 34 in AUDIO_N?
    What happes if I write 0 in that field? It multiply by 1 or by 0?
  • Range of P? Same as above. Maybe the value of P is equal to AUDIO_P+1 where AUDIO_P is bits 15-8 of AUDIOPLL_CTRL register. If I want to divide by 3, do I need to write 2 or 3 in AUDIO_P field?
  • Range of M? Same as above. Maybe the value of M is equal to AUD_MDIV2+1 where AUD_MDIV2 is bits 7-0 of  AUDIOPLL_DIV2 register. If I want to divide by 3, do I need to write 2 or 3 in AUDIO_P field? In table 1-80 is listed supported divide ratios for M. What does it means? What happes if I write 23 in AUD_MDIV2?
  • Range of FREQ? In reference manual is stated that “FREQ = Supported integer range is 8 to 15 and fraction range is 0 to FFFF FFFFh.”. I guess that the fractional part range is a typo, since it is 24 bit wide, so its range should be 0-00FF FFFFh. What happens if I set integer part to 3?

Thanks

 

Best regards

C6A816X PLL Clock
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  • Anil
    Posted by Anil
    on May 04 2012 05:53 AM
    Expert6655 points

    Hi Mastupristi,

    All the values are "AUDIO_*" but not "AUDIO_*+1"

    If we are not following the limits of the FAPLL then PLL output frequency is not stable and most of the times PLL will not lock.

    Below example gives you on how the values are used in frequency calculation:

    MPU frequency (default values) N = 64, P = 1, FREQ = 14, M = 1 we get:

      fo =  [(64 * 8)/(14 * 1 * 1)] * 27 =  987.4286MHz

    Regards

    AnilKumar

    Please mark this Forum post as answered via the Verify Answer button below if it helps answer your question.  Thanks!

    PSP dm8168 FAPLL
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