A DM8168 DVO2 VOUT0 port is configured for 480i and DVO_FMT is set to 001: two 10-bit wide video streams in CCIR656 format. DM8168 VOUT0 port is interfaced to a SD-SDI Serializer device which is controlled via embedded syncs (SAV/EAV). A problem seen here is that the starting line of active video in Field Two begins two lines later when compared to the starting line of active video in Field One. Is there any way to adjust at which line the V bit changes state (V = 0) in the second field, via a register setting?
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