This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DM8168 AACLC encoder efficiency is poor

Other Parts Discussed in Thread: SYSBIOS

when use DM8168 AACLC encode one 48KHz stereo audio, I find the DSP CPU Load up to 50%,the efficiency is poor.where is wrong?

  • Hello Feng,

    Could you provide more details about this problem?

    Best Regards,

    Margarita

  • Hello,

    The aaclc-enc codec version is "c674x_aaclcenc_01_00_01_00_elf", My app is based on DVRRDK 2.80, use RPE call interface.

    It get audio data from alsa sound interface, the encoded data stream send to network realtime.

    If only encode one 48KHz stereo audio data, it work good but i see the dsp's cpu load is about 50%.

    If I encode two 48KHz stereo audio data stream, the dsp's cpu load up to 90%,the dsp will cannot to do other work.

    I see the aaclc-enc codec "c674x_aaclcenc_01_00_01_00_elf" too slow to work.Where is wrong?

    Best Regards

  • Looks like caching is disabled for input and output buffers. Have you modified the DSP MAR bits by any chance.If not pls share your memory map file for further analysis.

  • Can you copy-paste the code in file:

    /dvr_rdk/mcfw/src_bios6/links_c6xdsp/system/system_c6xdsp.c

    Int32 System_init()

    {

    status = RpeServer_init(WHAT IS THIS PARAM IN YOUR CODEBASE);

  • Is this issue resolved?

    i Meet the same problem。

    I use DVRRDK_03.50.00.05 and hardware  is DM816X.

    i use the demo "dvr_rdk_demo_mcfw_api.out",for test " 7: Audio encode demo <File In/Out>" ,

     i use aac -lc ,the dsp load is 65%,samplerate is 48000,bitrate is 128000,channel is 2,

    [c6xdsp ]
    [c6xdsp ] 119678: LOAD: CPU: 71.4% HWI: 2.4%, SWI:2.8%
    [c6xdsp ]
    [c6xdsp ] 119678: LOAD: TSK: MISC : 66.2%
    [c6xdsp ]

    if is use g7111,the dsp load is only 0.3%

    [c6xdsp ]
    [c6xdsp ] 3757680: LOAD: CPU: 0.2% HWI: 0.0%, SWI:0.0%
    [c6xdsp ]
    [c6xdsp ] 3757680: LOAD: TSK: MISC : 0.2%
    [c6xdsp ]

  • Yes the issue is resolved. How many channels of AAC are you encoding ? You should be able to encode 16 channels.Which memory configuration are you using .i.e 2G or 1G build ?

  •   DVR_RDK_BOARD_TYPE := DM816X_TI_EVM

      DDR_MEM := DDR_MEM_1024M

      LINUX_MEM := LINUX_MEM_256M

    i use the demo ,just only one.the demo read pcm from file ,and encode aac to write in a file .

  • 8284.Rules_make.txt
    # Copyright Texas Instruments
    ifeq ($(dvr_rdk_PATH), )
    
    # Board type can be one of the following
    #	1. DM816X_UD_DVR
    #	2. DM816X_TI_EVM
    #	3. DM814X_TI_EVM
    #	4. DM810X_TI_EVM
    #	5. DM810X_UD_DVR
    #	6. DM810X_BCH_120_DVR
    
    ifeq ($(DVR_RDK_BOARD_TYPE ), )
      DVR_RDK_BOARD_TYPE := DM816X_TI_EVM
    endif
    
    # Default build environment, windows or linux
    ifeq ($(OS), )
      OS := Linux
    endif
    
    dvr_rdk_RELPATH = dvr_rdk
    
    ifeq ($(OS),Windows_NT)
      dvr_rdk_BASE     := $(CURDIR)/..
      TI_SW_ROOT       := D:/ti_software
    endif
    
    ifeq ($(OS),Linux)
      dvr_rdk_BASE     := $(shell pwd)/..
      TI_SW_ROOT       := $(dvr_rdk_BASE)/ti_tools
    endif
    
    dvr_rdk_PATH     := $(dvr_rdk_BASE)/$(dvr_rdk_RELPATH)
    
    # Code gen tools
    CODEGEN_PATH_A8  :=/opt/arm-2009q1/
    #CODEGEN_PATH_A8  := /opt/CodeSourcery/Sourcery_G++_Lite
    CODEGEN_PATH_DSP := $(TI_SW_ROOT)/cgt_dsp/cgt6x_7_3_5/
    CODEGEN_PATH_M3  := $(TI_SW_ROOT)/cgt_m3/cgt470_4_9_5/
    CODEGEN_PREFIX   := $(CODEGEN_PATH_A8)/bin/arm-none-linux-gnueabi-
    
    
    # BIOS side tools
    xdc_PATH         := $(TI_SW_ROOT)/xdc/xdctools_3_23_03_53
    bios_PATH        := $(TI_SW_ROOT)/bios/bios_6_33_05_46
    ipc_PATH         := $(TI_SW_ROOT)/ipc/ipc_1_24_03_32
    fc_PATH          := $(TI_SW_ROOT)/framework_components/framework_components_3_22_02_08_patched
    edma3lld_PATH    := $(TI_SW_ROOT)/edma3lld/edma3_lld_02_11_06_01
    iss_PATH         := $(TI_SW_ROOT)/iss/iss_02_00_00_08
    
    hdvpss_PATH      := $(dvr_rdk_BASE)/ti_tools/hdvpss/dvr_rdk_hdvpss
    
    # Codecs
    xdais_PATH       := $(TI_SW_ROOT)/xdais/xdais_7_22_00_03
    hdvicplib_PATH   := $(TI_SW_ROOT)/ivahd_hdvicp/hdvicp20
    h264dec_DIR      := $(TI_SW_ROOT)/codecs/REL.500.V.H264AVC.D.HP.IVAHD.02.00.08.00
    h264enc_DIR      := $(TI_SW_ROOT)/codecs/REL.500.V.H264AVC.E.IVAHD.02.00.04.01
    h264dec_PATH     := $(h264dec_DIR)/500.V.H264AVC.D.HP.IVAHD.02.00/IVAHD_001
    h264enc_PATH     := $(h264enc_DIR)/500.V.H264AVC.E.IVAHD.02.00/IVAHD_001
    jpegdec_DIR      := $(TI_SW_ROOT)/codecs/REL.500.V.MJPEG.D.IVAHD.01.00.06.00
    jpegenc_DIR      := $(TI_SW_ROOT)/codecs/REL.500.V.MJPEG.E.IVAHD.01.00.04.00
    jpegdec_PATH     := $(jpegdec_DIR)/500.V.MJPEG.D.IVAHD.01.00/IVAHD_001
    jpegenc_PATH     := $(jpegenc_DIR)/500.V.MJPEG.E.IVAHD.01.00/IVAHD_001
    mpeg4dec_DIR     := $(TI_SW_ROOT)/codecs/REL.500.V.MPEG4.D.IVAHD.01.00.11.00
    mpeg4dec_PATH    := $(mpeg4dec_DIR)/500.V.MPEG4.D.ASP.IVAHD.01.00/IVAHD_001
    
    # Audio framework (RPE) and Codecs
    rpe_PATH         := $(TI_SW_ROOT)/rpe/remote-processor-execute
    aaclcdec_PATH    := $(TI_SW_ROOT)/codecs/c674x_aaclcdec_01_41_00_00_elf
    aaclcenc_PATH    := $(TI_SW_ROOT)/codecs/c674x_aaclcenc_01_00_01_00_elf_patched
    
    # Linux side tools
    syslink_PATH     := $(TI_SW_ROOT)/syslink/syslink_2_20_02_20
    linuxdevkit_PATH := $(TI_SW_ROOT)/linux_devkit/arm-none-linux-gnueabi
    KERNELDIR        := $(TI_SW_ROOT)/linux_lsp/kernel/linux-dvr-rdk
    UBOOTDIR         := $(TI_SW_ROOT)/linux_lsp/uboot/u-boot-dvr-rdk
    LSP_COLLATERALS  := $(TI_SW_ROOT)/linux_lsp/collaterals
    
    # DVR Qt GUI Application tools
    ifeq ($(DVR_RDK_BOARD_TYPE),DM810X_UD_DVR)
    dvrapp_PATH      := $(dvr_rdk_PATH)/dvrapp/ti810x
    endif
    
    ifeq ($(DVR_RDK_BOARD_TYPE),DM816X_UD_DVR)
    dvrapp_PATH      := $(dvr_rdk_PATH)/dvrapp/ti816x
    endif
    
    live555_PATH     := $(dvr_rdk_PATH)/module/live555
    qt_PATH          := /usr/local/Trolltech/QtEmbedded-4.8.1-arm
    
    # filesystem related paths
    mtdutils_PATH    := $(TI_SW_ROOT)/mtd_utils
    
    TFTP_HOME     := $(dvr_rdk_BASE)/tftphome
    TARGET_FS     := $(dvr_rdk_BASE)/target/rfs
    TARGET_FS_DIR := $(dvr_rdk_PATH)/bin/ti816x
    TARGET_EXE_DIR := opt/dvr_rdk/ti816x
    
    ROOTDIR := $(dvr_rdk_PATH)
    
    ifeq ($(DVR_RDK_BOARD_TYPE),DM814X_TI_EVM)
    TARGET_FS_DIR := $(dvr_rdk_PATH)/bin/ti814x
    TARGET_FS     := $(dvr_rdk_BASE)/target/rfs_814x
    TARGET_EXE_DIR := opt/dvr_rdk/ti814x
    endif
    
    ifeq ($(DVR_RDK_BOARD_TYPE),DM814X_BCH_DVR)
    TARGET_FS_DIR := $(dvr_rdk_PATH)/bin/ti814x
    TARGET_FS     := $(dvr_rdk_BASE)/target/rfs_814x
    TARGET_EXE_DIR := opt/dvr_rdk/ti814x
    endif
    
    ifeq ($(DVR_RDK_BOARD_TYPE),DM816X_TI_EVM)
    TARGET_FS_DIR := $(dvr_rdk_PATH)/bin/ti816x
    TARGET_FS     := $(dvr_rdk_BASE)/target/rfs_816x
    TARGET_EXE_DIR := opt/dvr_rdk/ti816x
    endif
    
    ifeq ($(DVR_RDK_BOARD_TYPE),DM816X_UD_DVR)
    TARGET_FS_DIR := $(dvr_rdk_PATH)/bin/ti816x
    TARGET_FS     := $(dvr_rdk_BASE)/target/rfs_816x
    TARGET_EXE_DIR := opt/dvr_rdk/ti816x
    endif
    
    ifeq ($(DVR_RDK_BOARD_TYPE),DM810X_TI_EVM)
    TARGET_FS_DIR := $(dvr_rdk_PATH)/bin/ti810x
    TARGET_FS     := $(dvr_rdk_BASE)/target/rfs_810x
    TARGET_EXE_DIR := opt/dvr_rdk/ti810x
    endif
    
    ifeq ($(DVR_RDK_BOARD_TYPE),DM810X_BCH_DVR)
    TARGET_FS_DIR := $(dvr_rdk_PATH)/bin/ti810x
    TARGET_FS     := $(dvr_rdk_BASE)/target/rfs_810x
    TARGET_EXE_DIR := opt/dvr_rdk/ti810x
    endif
    
    ifeq ($(DVR_RDK_BOARD_TYPE),DM810X_UD_DVR)
    TARGET_FS_DIR := $(dvr_rdk_PATH)/bin/ti810x
    TARGET_FS     := $(dvr_rdk_BASE)/target/rfs_810x
    TARGET_EXE_DIR := opt/dvr_rdk/ti810x
    endif
    
    ifeq ($(DVR_RDK_BOARD_TYPE),DM810X_BCH_120_DVR)
    TARGET_FS_DIR := $(dvr_rdk_PATH)/bin/ti810x
    TARGET_FS     := $(dvr_rdk_BASE)/target/rfs_810x
    TARGET_EXE_DIR := opt/dvr_rdk/ti810x
    endif
    
    # Default DDR Size
    ifeq ($(DVR_RDK_BOARD_TYPE),DM816X_UD_DVR)
    ifeq ($(DDR_MEM), )
      DDR_MEM := DDR_MEM_1024M
    #  DDR_MEM := DDR_MEM_2048M
    endif
    endif
    
    ifeq ($(DVR_RDK_BOARD_TYPE),DM816X_UD_DVR)
    ifeq ($(DEMOTYPE), )
    #  DEMOTYPE := link_api_sd_demo
    endif
    endif
    
    # set to TRUE to enable standalone RTSP demo
    DEMO_RTSP_ENABLE := FALSE
    
    DVR_RDK_BOARD := DVR_RDK_BOARD_TYPE
    ifeq ($(DVR_RDK_BOARD_TYPE),DM816X_DVR)
      DVR_RDK_BOARD := ud816x_dvr
    endif
    ifeq ($(DVR_RDK_BOARD_TYPE),DM810X_DVR)
      DVR_RDK_BOARD := ud810x_dvr
    endif
    
    ifeq ($(CORE), )
      CORE := m3vpss
    endif
    
    # Default platform
    ifeq ($(PLATFORM), )
      PLATFORM := ti816x-evm
    ifeq ($(DVR_RDK_BOARD_TYPE),DM814X_TI_EVM)
      PLATFORM := ti814x-evm
    endif
    ifeq ($(DVR_RDK_BOARD_TYPE),DM814X_BCH_DVR)
      PLATFORM := ti814x-evm
    endif
    ifeq ($(DVR_RDK_BOARD_TYPE),DM810X_TI_EVM)
      PLATFORM := ti810x-evm
    endif
    ifeq ($(DVR_RDK_BOARD_TYPE),DM810X_BCH_DVR)
      PLATFORM := ti810x-evm
    endif
    ifeq ($(DVR_RDK_BOARD_TYPE),DM810X_UD_DVR)
      PLATFORM := ti810x-evm
    endif
    ifeq ($(DVR_RDK_BOARD_TYPE),DM810X_BCH_120_DVR)
      PLATFORM := ti810x-evm
    endif
    endif
    
    ###########################
    # DDR_MEM and LINUX_MEM set.
    ###########################
    # TI816X: 1G,256M; 2G,512M;
    # TI814X: 512M,128M;
    # TI810X: 256M,90M; 512M,128M; 512,192M;
    
    ifeq ($(PLATFORM), ti816x-evm)
    ifeq ($(DDR_MEM), )
      DDR_MEM := DDR_MEM_1024M
    #  DDR_MEM := DDR_MEM_2048M
    endif
    ifeq ($(LINUX_MEM),)
    #  LINUX_MEM := LINUX_MEM_128M
      LINUX_MEM := LINUX_MEM_256M
    endif
    #  VS_CARD := WITH_VS_CARD
      VS_CARD := WITHOUT_VS_CARD
    endif
    
    ifeq ($(PLATFORM), ti814x-evm)
    ifeq ($(DDR_MEM), )
      DDR_MEM := DDR_MEM_512M
    endif
    ifeq ($(LINUX_MEM),)
      LINUX_MEM := LINUX_MEM_128M
    endif
      VS_CARD := WITH_VS_CARD
    #  VS_CARD := WITHOUT_VS_CARD
    endif
    
    ifeq ($(PLATFORM), ti810x-evm)
    ifeq ($(DDR_MEM), )
      DDR_MEM := DDR_MEM_512M
    #  DDR_MEM := DDR_MEM_256M
    endif
    ifeq ($(LINUX_MEM),)
    #  LINUX_MEM := LINUX_MEM_90M
       LINUX_MEM := LINUX_MEM_128M
    #  LINUX_MEM := LINUX_MEM_192M
    endif
      VS_CARD := WITH_VS_CARD
    #  VS_CARD := WITHOUT_VS_CARD
    endif
    
    ##########################################################################
    #Set String Format when use LINUX_MEM and DDR_MEM as suffix of filenames.
    ##########################################################################
    #Prefix of size
    DDR_SIZE_PREFIX :=
    LINUX_SIZE_PREFIX :=
    #Will be used as filename suffix.
    DDR_SUFFIX := $(subst DDR_MEM_,$(DDR_SIZE_PREFIX),$(DDR_MEM))
    
    # Default profile
    ifeq ($(PROFILE_m3video), )
      PROFILE_m3video := release
    #  PROFILE_m3video := debug
    endif
    
    ifeq ($(PROFILE_m3vpss), )
      PROFILE_m3vpss := release
    #  PROFILE_m3vpss := debug
    endif
    
    ifneq ($(PLATFORM), ti810x-evm)
    ifeq ($(PROFILE_c6xdsp), )
      PROFILE_c6xdsp := debug
    endif
    endif
    
    # Default klockwork build flag
    ifeq ($(KW_BUILD), )
      KW_BUILD := no
    endif
    
    USE_SYSLINK_NOTIFY=0
    
    XDCPATH = $(bios_PATH)/packages;$(xdc_PATH)/packages;$(ipc_PATH)/packages;$(hdvpss_PATH)/packages;$(fc_PATH)/packages;$(dvr_rdk_PATH);$(syslink_PATH)/packages;$(xdais_PATH)/packages;$(edma3lld_PATH)/packages;
    
    
    
    # Default klockwork build flag
    ifeq ($(DISABLE_AUDIO), )
      DISABLE_AUDIO := no
    endif
    
    #Power Optimization based profile use for 810x-evm
    810X_SAVE_POWER_MODE=no
    
    TREAT_WARNINGS_AS_ERROR=no
    
    BUILD_BIOS6_FIRMWARE=yes
    SYSTEM_ETH_OFFLOAD_ENABLE=no
    
    ifeq ($(SYSTEM_ETH_OFFLOAD_ENABLE),yes)
    # since ethernet offload module is still in development stage, disable warnings as error flag
    TREAT_WARNINGS_AS_ERROR=no 
    endif
    
    
    DVR_RDK_ISS_LIB_PATH=$(dvr_rdk_PATH)/mcfw/src_bios6/alg/simcop/lib
    DVR_RDK_ISS_INC_PATH=$(dvr_rdk_PATH)/mcfw/src_bios6/alg/simcop/inc
    
    endif
    
    RPE_BUILD_VARS = ipc_PATH="${ipc_PATH}" \
    	bios_PATH="${bios_PATH}" \
    	xdc_PATH="${xdc_PATH}" \
    	xdais_PATH="${xdais_PATH}" \
    	syslink_PATH="${syslink_PATH}" \
    	kernel_PATH="${KERNELDIR}" \
    	CODESOURCERY_PATH="${CODEGEN_PATH_A8}" \
    	CGT_ARM_PREFIX="${CSTOOL_PREFIX}" \
    	CODEGEN_PATH_DSP="${CODEGEN_PATH_DSP}" \
    	CODEGEN_PATH_DSPELF="${CODEGEN_PATH_DSP}" \
    	ROOTDIR="${rpe_PATH}" \
    	aaclcdec_PATH="${aaclcdec_PATH}" \
    	aaclcenc_PATH="${aaclcenc_PATH}" 
    
    include $(ROOTDIR)/makerules/build_config.mk
    include $(ROOTDIR)/makerules/env.mk
    include $(ROOTDIR)/makerules/platform.mk
    include $(dvr_rdk_PATH)/component.mk
    
    LINUX_SUFFIX :=$(shell cat ${CONFIG_BLD_XDC_m3}|sed -n 's/.*LINUX_SIZE\s*=\s*\([0-9]*\)\s*\*\s*MB/\1M/p')
    LINUX_SUFFIX := $(subst ;,$(LINUX_SIZE_PREFIX),$(LINUX_SUFFIX))
    
    export OS
    export PLATFORM
    export CORE
    export PROFILE_m3vpss
    export PROFILE_m3video
    export PROFILE_c6xdsp
    export CODEGEN_PATH_M3
    export CODEGEN_PREFIX
    export CODEGEN_PATH_A8
    export CODEGEN_PATH_DSP
    export bios_PATH
    export xdc_PATH
    export hdvpss_PATH
    export dvr_rdk_PATH
    export ipc_PATH
    export fc_PATH
    export xdais_PATH
    export h264dec_DIR
    export h264enc_DIR
    export jpegdec_DIR
    export mpeg4dec_DIR
    export jpegenc_DIR
    export h264dec_PATH
    export h264enc_PATH
    export jpegdec_PATH
    export mpeg4dec_PATH
    export jpegenc_PATH
    export hdvicplib_PATH
    export linuxdevkit_PATH
    export edma3lld_PATH
    export ROOTDIR
    export XDCPATH
    export KW_BUILD
    export syslink_PATH
    export KERNELDIR
    export TARGET_FS_DIR
    export TARGET_EXE_DIR
    export UBOOTDIR
    export DVR_RDK_BOARD_TYPE
    export DVR_RDK_BOARD
    export USE_SYSLINK_NOTIFY
    export DEST_ROOT
    export dvr_rdk_BASE
    export TFTP_HOME
    export LINUX_MEM
    export DDR_MEM
    export DISABLE_AUDIO 
    export dvrapp_PATH
    export qt_PATH
    export 810X_SAVE_POWER_MODE
    export TREAT_WARNINGS_AS_ERROR
    export VS_CARD
    export SC_SCRIPTS_BASE_DIR
    export iss_PATH
    export SYSTEM_VCOP_ENABLE
    export SYSTEM_VCOP_VIDEOM3
    export DVR_RDK_ISS_LIB_PATH
    export DVR_RDK_ISS_INC_PATH
    export DEMOTYPE
    export rpe_PATH    
    export RPE_BUILD_VARS
    export aaclcdec_PATH    
    export aaclcenc_PATH    
    export mtdutils_PATH
    export DDR_SUFFIX
    export LINUX_SUFFIX
    export TI_SW_ROOT
    export DEMO_RTSP_ENABLE
    export LSP_COLLATERALS
    
    
    I directly use the original test procedure, without any modifications.
    i use the demo "dvr_rdk_demo_mcfw_api.out", for test "7: Audio encode demo <File In/Out>",


    The application encodes only one audio。


    My platform 1G environment


    The annex is "Rules.make"

  • Audio encode demo file in / out is in free run mode. So, dsp will show loading based how fast data is given / processed. This doesnt mean that encode performance is poor.

    For the other issue reported - In real time mode (alsa capture / network out), there is no reason for increase in load for 48KHz alone. We have tested 16channels of 16KHz, mono working with video usecase. There is no drastic increase in cpu load.

    This 2x, 3x increase in load can occur only if input / output buffers are cached. Please verify cache settings for input / output buffers.

  • I check input / output buffers setting,i can't find where is wrong.

    the input /output buff use shareregion buff ,the id is UTILS_MEM_VID_BITS_BUF_HEAP  (1).

    out platform is DM8168,

    our Memory Map is  1GB DDR  and 256 linux.

    the attachment is "config_1G_256MLinux.bld

    7455.config_1G_256MLinux.bld.txt
    /*
     *  ======== config.bld ========
     *  Build configuration script for HDVPSS drivers
     */
    
    /* load the required modules for the configuration */
    
    var M3 = xdc.useModule('ti.targets.arm.elf.M3');
    var C674 = xdc.useModule('ti.targets.elf.C674');
    
    var buildReleaseConfig = true;
     
    /* configure  the options for the M3 targets     */
    
    /* M3 compiler directory path                    */
    M3.rootDir = java.lang.System.getenv("CGTOOLS");
    
    /* linker options */
    
    M3.lnkOpts.suffix += " --zero_init=off ";
    M3.lnkOpts.suffix += " --dynamic --retain=_Ipc_ResetVector";
    
    /* compiler options                                */
    M3.ccOpts.suffix += " --gcc -DTI_816X_BUILD -DPLATFORM_EVM_SI -DSYSLINK_BUILD_RTOS -DUSE_SYSLINK_NOTIFY=0 -DUTILS_ASSERT_ENABLE";
    
    /* set default platform and list of all interested
     * platforms for M3
     */
    M3.platforms = [
                            "ti.platforms.evmTI816X:core0",
                            "ti.platforms.evmTI816X:core1",
                   ];
    
    /* Select the default platform
     *
     * Making core1 as defualt core configuration to be used
     *  Core 0 ==    Ducati.M3.VIDEO
     *  Core 1 ==    Ducati.M3.VPS
     */
    M3.platform = M3.platforms[1];
    
    /* configure  the options for the C674 targets     */
    
    /* C674 compiler directory path                    */
    C674.rootDir = java.lang.System.getenv("CGTOOLS_DSP");
    
    /* linker options */
    
    C674.lnkOpts.suffix += " --zero_init=off ";
    C674.lnkOpts.suffix += " --dynamic --retain=_Ipc_ResetVector";
    
    /* compiler options                                */
    C674.ccOpts.suffix += " -DTI_816X_BUILD -DPLATFORM_EVM_SI -DSYSLINK_BUILD_RTOS -DUSE_SYSLINK_NOTIFY=0";
    
    C674.platforms = ["ti.platforms.evmTI816X:plat"];
    C674.platform = C674.platforms[0];
    
    /* list interested targets in Build.targets array  */
    Build.targets = [
                        M3,
                        C674,
                    ];
    
    var KB=1024;
    var MB=KB*KB;
    
    var DDR3_ADDR;
    var DDR3_SIZE;
    
    var OCMC0_ADDR;
    var OCMC1_ADDR;
    var OCMC_SIZE;
    
    var LINUX_ADDR;
    var LINUX_SIZE;
    
    var SR0_ADDR;
    var SR0_SIZE;
    
    var SR1_ADDR;
    var SR1_SIZE;
    
    var SR3_INTRADUCATI_IPC_ADDR;
    var SR3_INTRADUCATI_IPC_SIZE;
    
    var VIDEO_M3_CODE_ADDR;
    var VIDEO_M3_CODE_SIZE;
    
    var VIDEO_M3_DATA_ADDR;
    var VIDEO_M3_DATA_SIZE;
    
    var SR2_FRAME_BUFFER_ADDR;
    var SR2_FRAME_BUFFER_SIZE;
    
    var DSS_M3_CODE_ADDR;
    var DSS_M3_CODE_SIZE;
    
    var DSS_M3_DATA_ADDR;
    var DSS_M3_DATA_SIZE;
    
    var DSP_CODE_ADDR;
    var DSP_CODE_SIZE;
    
    var DSP_M3_DATA_ADDR;
    var DSP_M3_DATA_SIZE;
    
    var TILER_ADDR;
    var TILER_SIZE;
    
    var HDVPSS_DESC_ADDR;
    var HDVPSS_DESC_SIZE;
    
    var HDVPSS_SHARED_ADDR;
    var HDVPSS_SHARED_SIZE;
    
    var NOTIFY_SHARED_ADDR;
    var NOTIFY_SHARED_SIZE;
    
    var REMOTE_DEBUG_ADDR;
    var REMOTE_DEBUG_SIZE;
    
    DDR3_ADDR                  = 0x80000000;
    DDR3_SIZE                  = 1024*MB;
    
    OCMC0_ADDR                 = 0x40300000;
    OCMC1_ADDR                 = 0x40400000;
    OCMC0_RUN_ADDR             = 0x00300000;
    OCMC1_RUN_ADDR             = 0x00400000;
    OCMC_SIZE                  = 256*KB;
    
    L2_SRAM_ADDR               = 0x55024000;
    L2_SRAM_SIZE               = 128*KB;
    L2_SRAM_RUN_ADDR           = 0x20004000;
    
    DUCATI_WB_WA_ADDR          = 0x20000000;
    
    var TOTAL_MEM_SIZE             = 1024*MB;
    
    /* first 512MB */
    LINUX_SIZE                 = 256*MB;
    SR1_SIZE                   = 202*MB;
    SR3_INTRADUCATI_IPC_SIZE   =          124*KB;
    VIDEO_M3_CODE_SIZE         =  2*MB  + 512*KB;
    VIDEO_M3_BSS_SIZE          = 10*MB  + 512*KB;
    VIDEO_M3_DATA_SIZE         =  2*MB  + 512*KB;
    DSS_M3_CODE_SIZE           =  1*MB  + 512*KB;
    DSS_M3_BSS_SIZE            = 16*MB  + 512*KB;
    DSS_M3_DATA_SIZE           =  5*MB  + 512*KB;
    DSP_CODE_SIZE              =  1*MB;
    DSP_DATA_SIZE              = 13*MB  + 900*KB;
    
    
    /* second 512MB */
    /* Tiler Buffers in the bottom 512MB */
    TILER_SIZE                  = 256*MB; /* (128+128) - MUST be aligned on 128MB boundary */
    SR2_FRAME_BUFFER_SIZE       = 234*MB - 256*KB;
    SR0_SIZE                    = 15*MB;
    VIDEO_M3_EXCEPTION_CTX_SIZE = 128*KB;
    VPSS_M3_EXCEPTION_CTX_SIZE  = 128*KB;
    HDVPSS_DESC_SIZE            = 2*MB;
    HDVPSS_SHARED_SIZE          = 2*MB;
    NOTIFY_SHARED_SIZE          = 2*MB;
    REMOTE_DEBUG_SIZE           = 1*MB;
    
    
    print ("Memory Map - 1GB DDR, upto 256MB Linux");
    
    print ("  0x80000000     +-------------------+");
    print ("         ^       |                   |");
    print ("         |       |  " + (LINUX_SIZE / MB) + " MB           | Linux");
    print ("         |       |                   |");
    print ("         |       +-------------------+");
    print ("         |       |  " + (SR1_SIZE / MB) + "MB            | (SR1) Bitstream buffer");
    print ("         |       |                   | Cached on A8. Cached on M3, although access by DMAs");
    print ("         |       +-------------------+ ");
    print ("         |       |   " + (SR3_INTRADUCATI_IPC_SIZE / KB) + " KB          | (SR3)InterDucati IPC ListMP .Cached on M3 ");
    print ("         |       +-------------------+  ");          
    print ("         +       |   " + (VIDEO_M3_CODE_SIZE / MB) + " MB          | Video M3 Code");
    print ("       512 MB    +-------------------+");
    print ("         +       |   " + (VIDEO_M3_BSS_SIZE / MB) + " MB         | Video M3 BSS");
    print ("         |       +-------------------+");
    print ("         |       |   " + (VIDEO_M3_DATA_SIZE / MB) + " MB          | Video  M3 Data");
    print ("         |       +-------------------+");
    print ("         |       |   " + (DSS_M3_CODE_SIZE/ MB) + " MB          | VPSS  M3 Code");
    print ("         |       +-------------------+");
    print ("         |       |   " + (DSS_M3_BSS_SIZE/ MB) + " MB         | VPSS  M3 BSS");
    print ("         |       +-------------------+");
    print ("         |       |   " + (DSS_M3_DATA_SIZE/ MB) + " MB          | VPSS  M3 Data");
    print ("         |       +-------------------+");
    print ("         |       |   " + ( DSP_CODE_SIZE / KB) + " KB          | DSP Code");
    print ("         |       +-------------------+");
    print ("         v       |   " + (DSP_DATA_SIZE / MB) + " MB         | DSP Data");
    print ("  0xA0000000     +-------------------+");
    print ("         ^       |   " + (TILER_SIZE / MB) + " MB          | Tiled 8-bit + 16-bit region");
    print ("         |       +-------------------+");
    print ("         |       |  " + (SR2_FRAME_BUFFER_SIZE / MB) + " MB        | (SR2) Frame Buffer Region - <VPSS - Video M3 Frame Buf>");
    print ("         |       +-------------------+  ");
    print ("         +       |                   |");
    print ("       512 MB    |  " + (SR0_SIZE / MB) + " MB            | (SR0) Syslink MsgQ/IPC List MP - <Non-cached on M3>");
    print ("         +       +-------------------+");
    print ("         |       |  " + (VIDEO_M3_EXCEPTION_CTX_SIZE / KB) + " KB           | Video M3 exception context");
    print ("         |       +-------------------+  ");
    print ("         |       |  " + (VPSS_M3_EXCEPTION_CTX_SIZE / KB) + "KB            | Vpss M3 exception context");
    print ("         |       +-------------------+  ");
    print ("         |       |  " + (HDVPSS_DESC_SIZE / MB) + " MB             | VPSS M3 - VPDMA Descriptor");
    print ("         |       +-------------------+");
    print ("         |       |  " + (HDVPSS_SHARED_SIZE / MB) + " MB             | VPSS M3 - FBDev Shared Memory");
    print ("         |       +-------------------+");
    print ("         |       |  " + (NOTIFY_SHARED_SIZE / MB) + " MB             | Host - VPSS M3 Notify(For FBDev)");
    print ("         |       +-------------------+");
    print ("         v       |  " + (REMOTE_DEBUG_SIZE / MB) + " MB             | Remote Debug Print");
    print ("   0xBFFFFFFF    +-------------------+");
    
    
    
    
    
    /* first 512MB */
    LINUX_ADDR                 = DDR3_ADDR;
    SR1_ADDR                   = LINUX_ADDR						 + LINUX_SIZE;
    SR3_INTRADUCATI_IPC_ADDR   = SR1_ADDR						 + SR1_SIZE;
    VIDEO_M3_CODE_ADDR         = SR3_INTRADUCATI_IPC_ADDR		 + SR3_INTRADUCATI_IPC_SIZE;
    VIDEO_M3_DATA_ADDR         = VIDEO_M3_CODE_ADDR				 + VIDEO_M3_CODE_SIZE;
    VIDEO_M3_BSS_ADDR          = VIDEO_M3_DATA_ADDR				 + VIDEO_M3_DATA_SIZE;
    VIDEO_M3_BSS_MAPPED_ADDR   = (VIDEO_M3_BSS_ADDR - DDR3_ADDR) + DUCATI_WB_WA_ADDR;
    DSS_M3_CODE_ADDR           = VIDEO_M3_BSS_ADDR				 + VIDEO_M3_BSS_SIZE;
    DSS_M3_DATA_ADDR           = DSS_M3_CODE_ADDR				 + DSS_M3_CODE_SIZE;
    DSS_M3_BSS_ADDR            = DSS_M3_DATA_ADDR				 + DSS_M3_DATA_SIZE;
    DSS_M3_BSS_MAPPED_ADDR     = (DSS_M3_BSS_ADDR - DDR3_ADDR)	 + DUCATI_WB_WA_ADDR;
    DSP_CODE_ADDR              = DSS_M3_BSS_ADDR				 + DSS_M3_BSS_SIZE;
    DSP_DATA_ADDR              = DSP_CODE_ADDR					 + DSP_CODE_SIZE;
    
    /* second 512MB */
    /* Tiler Buffers in the bottom 512MB */
    TILER_ADDR                  = DDR3_ADDR						+ DDR3_SIZE/2;
    SR2_FRAME_BUFFER_ADDR       = TILER_ADDR					+ TILER_SIZE;
    VIDEO_M3_EXCEPTION_CTX_ADDR = SR2_FRAME_BUFFER_ADDR			+ SR2_FRAME_BUFFER_SIZE;
    VPSS_M3_EXCEPTION_CTX_ADDR  = VIDEO_M3_EXCEPTION_CTX_ADDR	+ VIDEO_M3_EXCEPTION_CTX_SIZE;
    HDVPSS_DESC_ADDR            = VPSS_M3_EXCEPTION_CTX_ADDR	+ VPSS_M3_EXCEPTION_CTX_SIZE;
    HDVPSS_SHARED_ADDR          = HDVPSS_DESC_ADDR				+ HDVPSS_DESC_SIZE;
    NOTIFY_SHARED_ADDR          = HDVPSS_SHARED_ADDR			+ HDVPSS_SHARED_SIZE;
    REMOTE_DEBUG_ADDR           = NOTIFY_SHARED_ADDR			+ NOTIFY_SHARED_SIZE;
    SR0_ADDR                    = REMOTE_DEBUG_ADDR			    + REMOTE_DEBUG_SIZE;
    
    if ((DSP_DATA_ADDR + DSP_DATA_SIZE) > TILER_ADDR)
    {
      throw xdc.$$XDCException("MEMORY_MAP OVERFLOW ERROR ",
                               "\nRegion End: " + "0x" + java.lang.Long.toHexString(TILER_ADDR) + 
                               "\nActual End: " + "0x" + java.lang.Long.toHexString(DSP_DATA_ADDR + DSP_DATA_SIZE ));
    }
    
    if ((SR0_ADDR + SR0_SIZE) > DDR3_ADDR + DDR3_SIZE)
    {
      throw xdc.$$XDCException("MEMORY_MAP OVERFLOW ERROR ",
                               "\nRegion End: " + "0x" + java.lang.Long.toHexString(DDR3_ADDR + DDR3_SIZE) + 
                               "\nActual End: " + "0x" + java.lang.Long.toHexString(SR0_ADDR + SR0_SIZE)
    						  );
    }
    
    Build.platformTable["ti.platforms.evmTI816X:core1"] =
    {
        externalMemoryMap:
        [
            ["DDR3_RAM", {
                comment: "DDR3_RAM",
                name: "DDR3_RAM",
                base: DDR3_ADDR,
                len:  DDR3_SIZE
            }],
            ["OCMC1_RAM", {
                comment: "OCMC1_RAM",
                name: "OCMC1_RAM",
                base: OCMC1_ADDR,
                len:  OCMC_SIZE
            }],
            ["VIDEO_M3_BSS_MAPPED_MEM", {
                comment : "VIDEO_M3_BSS_MAPPED_MEM",
                name    : "VIDEO_M3_BSS_MAPPED_MEM",
                base    : VIDEO_M3_BSS_MAPPED_ADDR,
                len     : VIDEO_M3_BSS_SIZE
            }],
            ["DSS_M3_BSS_MAPPED_MEM", {
                comment : "DSS_M3_BSS_MAPPED_MEM",
                name    : "DSS_M3_BSS_MAPPED_MEM",
                base    : DSS_M3_BSS_MAPPED_ADDR,
                len     : DSS_M3_BSS_SIZE
            }],
        ],
        customMemoryMap:
        [
            ["LINUX_MEM", {
                comment : "LINUX_MEM",
                name    : "LINUX_MEM",
                base    : LINUX_ADDR,
                len     : LINUX_SIZE
            }],
            ["SR1", {
                comment : "SR1",
                name    : "SR1",
                base    : SR1_ADDR,
                len     : SR1_SIZE
            }],
            ["SR3_INTRADUCATI_IPC", {
                comment : "SR3_INTRADUCATI_IPC",
                name    : "SR3_INTRADUCATI_IPC",
                base    : SR3_INTRADUCATI_IPC_ADDR,
                len     : SR3_INTRADUCATI_IPC_SIZE
            }],
            ["VIDEO_M3_CODE_MEM", {
                comment : "VIDEO_M3_CODE_MEM",
                name    : "VIDEO_M3_CODE_MEM",
                base    : VIDEO_M3_CODE_ADDR,
                len     : VIDEO_M3_CODE_SIZE
            }],
            ["VIDEO_M3_DATA_MEM", {
                comment : "VIDEO_M3_DATA_MEM",
                name    : "VIDEO_M3_DATA_MEM",
                base    : VIDEO_M3_DATA_ADDR,
                len     : VIDEO_M3_DATA_SIZE
            }],
            ["VIDEO_M3_BSS_MEM", {
                comment : "VIDEO_M3_BSS_MEM",
                name    : "VIDEO_M3_BSS_MEM",
                base    : VIDEO_M3_BSS_ADDR,
                len     : VIDEO_M3_BSS_SIZE
            }],
            ["VIDEO_M3_BSS_MAPPED_MEM", {
                comment : "VIDEO_M3_BSS_MAPPED_MEM",
                name    : "VIDEO_M3_BSS_MAPPED_MEM",
                base    : VIDEO_M3_BSS_MAPPED_ADDR,
                len     : VIDEO_M3_BSS_SIZE
            }],
            ["DSS_M3_CODE_MEM", {
                comment : "DSS_M3_CODE_MEM",
                name    : "DSS_M3_CODE_MEM",
                base    : DSS_M3_CODE_ADDR,
                len     : DSS_M3_CODE_SIZE
            }],
            ["DDR3_M3", {
                comment : "DDR3_M3",
                name    : "DDR3_M3",
                base    : DSS_M3_DATA_ADDR,
                len     : DSS_M3_DATA_SIZE
            }],
            ["DSS_M3_BSS_MEM", {
                comment : "DSS_M3_BSS_MEM",
                name    : "DSS_M3_BSS_MEM",
                base    : DSS_M3_BSS_ADDR,
                len     : DSS_M3_BSS_SIZE
            }],
            ["DSS_M3_BSS_MAPPED_MEM", {
                comment : "DSS_M3_BSS_MAPPED_MEM",
                name    : "DSS_M3_BSS_MAPPED_MEM",
                base    : DSS_M3_BSS_MAPPED_ADDR,
                len     : DSS_M3_BSS_SIZE
            }],
            ["DSP_CODE_MEM", {
                comment : "DSP_CODE_MEM",
                name    : "DSP_CODE_MEM",
                base    : DSP_CODE_ADDR,
                len     : DSP_CODE_SIZE
            }],
            ["DSP_DATA_MEM", {
                comment : "DSP_DATA_MEM",
                name    : "DSP_DATA_MEM",
                base    : DSP_DATA_ADDR,
                len     : DSP_DATA_SIZE
            }],
            ["TILER_MEM", {
                comment : "TILER_MEM",
                name    : "TILER_MEM",
                base    : TILER_ADDR,
                len     : TILER_SIZE
            }],
            ["SR2_FRAME_BUFFER_MEM", {
                comment : "SR2_FRAME_BUFFER_MEM",
                name    : "SR2_FRAME_BUFFER_MEM",
                base    : SR2_FRAME_BUFFER_ADDR,
                len     : SR2_FRAME_BUFFER_SIZE
            }],
            ["SR0", {
                comment : "SR0",
                name    : "SR0",
                base    : SR0_ADDR,
                len     : SR0_SIZE
            }],
            ["VIDEO_M3_EXCEPTION_CTX", {
                comment : "VIDEO_M3_EXCEPTION_CTX",
                name    : "VIDEO_M3_EXCEPTION_CTX",
                base    : VIDEO_M3_EXCEPTION_CTX_ADDR,
                len     : VIDEO_M3_EXCEPTION_CTX_SIZE
            }],
            ["VPSS_M3_EXCEPTION_CTX", {
                comment : "VPSS_M3_EXCEPTION_CTX",
                name    : "VPSS_M3_EXCEPTION_CTX",
                base    : VPSS_M3_EXCEPTION_CTX_ADDR,
                len     : VPSS_M3_EXCEPTION_CTX_SIZE
            }],
            ["HDVPSS_DESC_MEM", {
                comment : "HDVPSS_DESC_MEM",
                name    : "HDVPSS_DESC_MEM",
                base    : HDVPSS_DESC_ADDR,
                len     : HDVPSS_DESC_SIZE
            }],
            ["HDVPSS_SHARED_MEM", {
                comment : "HDVPSS_SHARED_MEM",
                name    : "HDVPSS_SHARED_MEM",
                base    : HDVPSS_SHARED_ADDR,
                len     : HDVPSS_SHARED_SIZE
            }],
            ["HOST_VPSS_NOTIFYMEM", {
                comment : "HOST_VPSS_NOTIFYMEM",
                name    : "HOST_VPSS_NOTIFYMEM",
                base    : NOTIFY_SHARED_ADDR,
                len     : NOTIFY_SHARED_SIZE
            }],
            ["REMOTE_DEBUG_MEM", {
                comment : "REMOTE_DEBUG_MEM",
                name    : "REMOTE_DEBUG_MEM",
                base    : REMOTE_DEBUG_ADDR,
                len     : REMOTE_DEBUG_SIZE
            }],
            ["L2_ROM", {
                comment: "L2_ROM",
                name: "L2_ROM",
                base: 0x00000000,
                len:  0x00004000
            }],
            ["OCMC1_RAM", {
                comment: "OCMC1_RAM",
                name: "OCMC1_RAM",
                base: OCMC1_ADDR,
                len:  OCMC_SIZE
            }],
            ["OCMC1_RAM_MAPPED", {
                comment: "OCMC1_RAM",
                name: "OCMC1_RAM_MAPPED",
                base: OCMC1_RUN_ADDR,
                len:  OCMC_SIZE
            }],
        ]
    };
    
    Build.platformTable["ti.platforms.evmTI816X:core0"] =
    {
        externalMemoryMap:
        [
            ["DDR3_RAM", {
                comment: "DDR3_RAM",
                name: "DDR3_RAM",
                base: DDR3_ADDR,
                len:  DDR3_SIZE
            }],
            ["OCMC0_RAM", {
                comment: "OCMC0_RAM",
                name: "OCMC0_RAM",
                base: OCMC0_ADDR,
                len:  OCMC_SIZE
            }],
            ["VIDEO_M3_BSS_MAPPED_MEM", {
                comment : "VIDEO_M3_BSS_MAPPED_MEM",
                name    : "VIDEO_M3_BSS_MAPPED_MEM",
                base    : VIDEO_M3_BSS_MAPPED_ADDR,
                len     : VIDEO_M3_BSS_SIZE
            }],
            ["DSS_M3_BSS_MAPPED_MEM", {
                comment : "DSS_M3_BSS_MAPPED_MEM",
                name    : "DSS_M3_BSS_MAPPED_MEM",
                base    : DSS_M3_BSS_MAPPED_ADDR,
                len     : DSS_M3_BSS_SIZE
            }],
            ["L2_SRAM", {
                comment: "L2_SRAM",
                name: "L2_SRAM",
                base: L2_SRAM_ADDR,
                len:  L2_SRAM_SIZE
            }],
            ["L2_SRAM_RUN", {
                comment: "L2_SRAM_RUN",
                name: "L2_SRAM_RUN",
                base: L2_SRAM_RUN_ADDR,
                len:  L2_SRAM_SIZE
            }],
        ],
        customMemoryMap:
        [
            ["LINUX_MEM", {
                comment : "LINUX_MEM",
                name    : "LINUX_MEM",
                base    : LINUX_ADDR,
                len     : LINUX_SIZE
            }],
            ["SR1", {
                comment : "SR1",
                name    : "SR1",
                base    : SR1_ADDR,
                len     : SR1_SIZE
            }],
            ["SR3_INTRADUCATI_IPC", {
                comment : "SR3_INTRADUCATI_IPC",
                name    : "SR3_INTRADUCATI_IPC",
                base    : SR3_INTRADUCATI_IPC_ADDR,
                len     : SR3_INTRADUCATI_IPC_SIZE
            }],
            ["VIDEO_M3_CODE_MEM", {
                comment : "VIDEO_M3_CODE_MEM",
                name    : "VIDEO_M3_CODE_MEM",
                base    : VIDEO_M3_CODE_ADDR,
                len     : VIDEO_M3_CODE_SIZE
            }],
            ["DDR_M3", {
                comment : "DDR3_M3",
                name    : "DDR3_M3",
                base    : VIDEO_M3_DATA_ADDR,
                len     : VIDEO_M3_DATA_SIZE
            }],
            ["VIDEO_M3_BSS_MEM", {
                comment : "VIDEO_M3_BSS_MEM",
                name    : "VIDEO_M3_BSS_MEM",
                base    : VIDEO_M3_BSS_ADDR,
                len     : VIDEO_M3_BSS_SIZE
            }],
            ["VIDEO_M3_BSS_MAPPED_MEM", {
                comment : "VIDEO_M3_BSS_MAPPED_MEM",
                name    : "VIDEO_M3_BSS_MAPPED_MEM",
                base    : VIDEO_M3_BSS_MAPPED_ADDR,
                len     : VIDEO_M3_BSS_SIZE
            }],
            ["DSS_M3_CODE_MEM", {
                comment : "DSS_M3_CODE_MEM",
                name    : "DSS_M3_CODE_MEM",
                base    : DSS_M3_CODE_ADDR,
                len     : DSS_M3_CODE_SIZE
            }],
            ["DSS_M3_BSS_MEM", {
                comment : "DSS_M3_BSS_MEM",
                name    : "DSS_M3_BSS_MEM",
                base    : DSS_M3_BSS_ADDR,
                len     : DSS_M3_BSS_SIZE
            }],
            ["DSS_M3_BSS_MAPPED_MEM", {
                comment : "DSS_M3_BSS_MAPPED_MEM",
                name    : "DSS_M3_BSS_MAPPED_MEM",
                base    : DSS_M3_BSS_MAPPED_ADDR,
                len     : DSS_M3_BSS_SIZE
            }],
            ["DSS_M3_DATA_MEM", {
                comment : "DSS_M3_DATA_MEM",
                name    : "DSS_M3_DATA_MEM",
                base    : DSS_M3_DATA_ADDR,
                len     : DSS_M3_DATA_SIZE
            }],
            ["DSP_CODE_MEM", {
                comment : "DSP_CODE_MEM",
                name    : "DSP_CODE_MEM",
                base    : DSP_CODE_ADDR,
                len     : DSP_CODE_SIZE
            }],
            ["DSP_DATA_MEM", {
                comment : "DSP_DATA_MEM",
                name    : "DSP_DATA_MEM",
                base    : DSP_DATA_ADDR,
                len     : DSP_DATA_SIZE
            }],
            ["TILER_MEM", {
                comment : "TILER_MEM",
                name    : "TILER_MEM",
                base    : TILER_ADDR,
                len     : TILER_SIZE
            }],
            ["SR2_FRAME_BUFFER_MEM", {
                comment : "SR2_FRAME_BUFFER_MEM",
                name    : "SR2_FRAME_BUFFER_MEM",
                base    : SR2_FRAME_BUFFER_ADDR,
                len     : SR2_FRAME_BUFFER_SIZE
            }],
            ["SR0", {
                comment : "SR0",
                name    : "SR0",
                base    : SR0_ADDR,
                len     : SR0_SIZE
            }],
            ["VIDEO_M3_EXCEPTION_CTX", {
                comment : "VIDEO_M3_EXCEPTION_CTX",
                name    : "VIDEO_M3_EXCEPTION_CTX",
                base    : VIDEO_M3_EXCEPTION_CTX_ADDR,
                len     : VIDEO_M3_EXCEPTION_CTX_SIZE
            }],
            ["VPSS_M3_EXCEPTION_CTX", {
                comment : "VPSS_M3_EXCEPTION_CTX",
                name    : "VPSS_M3_EXCEPTION_CTX",
                base    : VPSS_M3_EXCEPTION_CTX_ADDR,
                len     : VPSS_M3_EXCEPTION_CTX_SIZE
            }],
            ["HDVPSS_DESC_MEM", {
                comment : "HDVPSS_DESC_MEM",
                name    : "HDVPSS_DESC_MEM",
                base    : HDVPSS_DESC_ADDR,
                len     : HDVPSS_DESC_SIZE
            }],
            ["HDVPSS_SHARED_MEM", {
                comment : "HDVPSS_SHARED_MEM",
                name    : "HDVPSS_SHARED_MEM",
                base    : HDVPSS_SHARED_ADDR,
                len     : HDVPSS_SHARED_SIZE
            }],
            ["HOST_VPSS_NOTIFYMEM", {
                comment : "HOST_VPSS_NOTIFYMEM",
                name    : "HOST_VPSS_NOTIFYMEM",
                base    : NOTIFY_SHARED_ADDR,
                len     : NOTIFY_SHARED_SIZE
            }],
            ["REMOTE_DEBUG_MEM", {
                comment : "REMOTE_DEBUG_MEM",
                name    : "REMOTE_DEBUG_MEM",
                base    : REMOTE_DEBUG_ADDR,
                len     : REMOTE_DEBUG_SIZE
            }],
            ["L2_SRAM", {
                comment: "L2_SRAM",
                name: "L2_SRAM",
                base: L2_SRAM_ADDR,
                len:  L2_SRAM_SIZE
            }],
            ["L2_SRAM_RUN", {
                comment: "L2_SRAM_RUN",
                name: "L2_SRAM_RUN",
                base: L2_SRAM_RUN_ADDR,
                len:  L2_SRAM_SIZE
            }],
            ["L2_ROM", {
                comment: "L2_ROM",
                name: "L2_ROM",
                base: 0x00000000,
                len:  0x00004000
            }],
            ["OCMC0_RAM", {
                comment: "OCMC0_RAM",
                name: "OCMC0_RAM",
                base: OCMC0_ADDR,
                len:  OCMC_SIZE
            }],
            ["OCMC0_RAM_MAPPED", {
                comment: "OCMC0_RAM",
                name: "OCMC0_RAM_MAPPED",
                base: OCMC0_RUN_ADDR,
                len:  OCMC_SIZE
            }],
        ]
    };
    
    Build.platformTable["ti.platforms.evmTI816X:plat"] =
    {
        externalMemoryMap:
        [
            ["DDR3_RAM", {
                comment: "DDR3_RAM",
                name: "DDR3_RAM",
                base: DDR3_ADDR,
                len:  DDR3_SIZE
            }],
            ["OCMC0_RAM", {
                comment: "OCMC0_RAM",
                name: "OCMC0_RAM",
                base: OCMC0_ADDR,
                len:  OCMC_SIZE
            }],
            ["OCMC1_RAM", {
                comment: "OCMC1_RAM",
                name: "OCMC1_RAM",
                base: OCMC1_ADDR,
                len:  OCMC_SIZE
            }],
        ],
        customMemoryMap:
        [
            ["LINUX_MEM", {
                comment : "LINUX_MEM",
                name    : "LINUX_MEM",
                base    : LINUX_ADDR,
                len     : LINUX_SIZE
            }],
            ["SR1", {
                comment : "SR1",
                name    : "SR1",
                base    : SR1_ADDR,
                len     : SR1_SIZE
            }],
            ["SR3_INTRADUCATI_IPC", {
                comment : "SR3_INTRADUCATI_IPC",
                name    : "SR3_INTRADUCATI_IPC",
                base    : SR3_INTRADUCATI_IPC_ADDR,
                len     : SR3_INTRADUCATI_IPC_SIZE
            }],
            ["VIDEO_M3_CODE_MEM", {
                comment : "VIDEO_M3_CODE_MEM",
                name    : "VIDEO_M3_CODE_MEM",
                base    : VIDEO_M3_CODE_ADDR,
                len     : VIDEO_M3_CODE_SIZE
            }],
            ["VIDEO_M3_DATA_MEM", {
                comment : "VIDEO_M3_DATA_MEM",
                name    : "VIDEO_M3_DATA_MEM",
                base    : VIDEO_M3_DATA_ADDR,
                len     : VIDEO_M3_DATA_SIZE
            }],
            ["VIDEO_M3_BSS_MEM", {
                comment : "VIDEO_M3_BSS_MEM",
                name    : "VIDEO_M3_BSS_MEM",
                base    : VIDEO_M3_BSS_ADDR,
                len     : VIDEO_M3_BSS_SIZE
            }],
            ["DSS_M3_CODE_MEM", {
                comment : "DSS_M3_CODE_MEM",
                name    : "DSS_M3_CODE_MEM",
                base    : DSS_M3_CODE_ADDR,
                len     : DSS_M3_CODE_SIZE
            }],
            ["DSS_M3_DATA_MEM", {
                comment : "DSS_M3_DATA_MEM",
                name    : "DSS_M3_DATA_MEM",
                base    : DSS_M3_DATA_ADDR,
                len     : DSS_M3_DATA_SIZE
            }],
            ["DSS_M3_BSS_MEM", {
                comment : "DSS_M3_BSS_MEM",
                name    : "DSS_M3_BSS_MEM",
                base    : DSS_M3_BSS_ADDR,
                len     : DSS_M3_BSS_SIZE
            }],
            ["DSP_CODE_MEM", {
                comment : "DSP_CODE_MEM",
                name    : "DSP_CODE_MEM",
                base    : DSP_CODE_ADDR,
                len     : DSP_CODE_SIZE
            }],
            ["DSP_DATA_MEM", {
                comment : "DDR3_DSP",
                name    : "DDR3_DSP",
                base    : DSP_DATA_ADDR,
                len     : DSP_DATA_SIZE
            }],
            ["TILER_MEM", {
                comment : "TILER_MEM",
                name    : "TILER_MEM",
                base    : TILER_ADDR,
                len     : TILER_SIZE
            }],
            ["SR2_FRAME_BUFFER_MEM", {
                comment : "SR2_FRAME_BUFFER_MEM",
                name    : "SR2_FRAME_BUFFER_MEM",
                base    : SR2_FRAME_BUFFER_ADDR,
                len     : SR2_FRAME_BUFFER_SIZE
            }],
            ["SR0", {
                comment : "SR0",
                name    : "SR0",
                base    : SR0_ADDR,
                len     : SR0_SIZE
            }],
            ["VIDEO_M3_EXCEPTION_CTX", {
                comment : "VIDEO_M3_EXCEPTION_CTX",
                name    : "VIDEO_M3_EXCEPTION_CTX",
                base    : VIDEO_M3_EXCEPTION_CTX_ADDR,
                len     : VIDEO_M3_EXCEPTION_CTX_SIZE
            }],
            ["VPSS_M3_EXCEPTION_CTX", {
                comment : "VPSS_M3_EXCEPTION_CTX",
                name    : "VPSS_M3_EXCEPTION_CTX",
                base    : VPSS_M3_EXCEPTION_CTX_ADDR,
                len     : VPSS_M3_EXCEPTION_CTX_SIZE
            }],
            ["HDVPSS_DESC_MEM", {
                comment : "HDVPSS_DESC_MEM",
                name    : "HDVPSS_DESC_MEM",
                base    : HDVPSS_DESC_ADDR,
                len     : HDVPSS_DESC_SIZE
            }],
            ["HDVPSS_SHARED_MEM", {
                comment : "HDVPSS_SHARED_MEM",
                name    : "HDVPSS_SHARED_MEM",
                base    : HDVPSS_SHARED_ADDR,
                len     : HDVPSS_SHARED_SIZE
            }],
            ["HOST_VPSS_NOTIFYMEM", {
                comment : "HOST_VPSS_NOTIFYMEM",
                name    : "HOST_VPSS_NOTIFYMEM",
                base    : NOTIFY_SHARED_ADDR,
                len     : NOTIFY_SHARED_SIZE
            }],
            ["REMOTE_DEBUG_MEM", {
                comment : "REMOTE_DEBUG_MEM",
                name    : "REMOTE_DEBUG_MEM",
                base    : REMOTE_DEBUG_ADDR,
                len     : REMOTE_DEBUG_SIZE
            }],
            ["OCMC0_RAM", {
                comment: "OCMC0_RAM",
                name: "OCMC0_RAM",
                base: OCMC0_ADDR,
                len:  OCMC_SIZE
            }],
            ["OCMC1_RAM", {
                comment: "OCMC1_RAM",
                name: "OCMC1_RAM",
                base: OCMC1_ADDR,
                len:  OCMC_SIZE
            }],
            ["DSP_L2_RAM", {
                comment: "DSP_L2_RAM",
                name: "DSP_L2_RAM",
                base: 0x10800000,
                len:  0x00020000
            }],
        ],
        l1PMode: "32k",
        l1DMode: "32k",
        l2Mode:  "128k"
    };
    
    var addrFileGenerated = false;
    if (addrFileGenerated == false)
    {
        xdc.loadCapsule("genaddrinfo.xs").GenAddrFile();
        addrFileGenerated = true;
    }
    
    
    
    "

    in system_c6xdsp.c ,

    #ifdef DSP_RPE_AUDIO_ENABLE
    extern int32_t RpeServer_init (void *heapHdl);

    status = RpeServer_init(Utils_getAlgMemoryHeapHandle());
    Vps_printf(" %d: SYSTEM : RpeServer_init() done... Ret Val %d!!!\n",
    Clock_getTicks(), status);
    #endif

    /* Used for RPE - ENSURE that this is cached as this is used for alg memtab allocation */
    void* Utils_getAlgMemoryHeapHandle (void)
    {
    return ((void*) gUtils_heapMemHandle[UTILS_MEM_VID_BITS_BUF_HEAP]);

    }

  • I enabled 48KHz stereo capture with AIC, enabled 2 ch AAC-LC encode (with L & R of stereo).

    This is the loading (before enabling audio capture / encode)

    [c6xdsp ]  5812226: LOAD: CPU: 54.6% HWI: 0.5%, SWI:0.3%
     [c6xdsp ]
     [c6xdsp ]  5812226: LOAD: TSK: IPC_FRAMES_IN0      : 1.8%
     [c6xdsp ]  5812226: LOAD: TSK: ALG0                : 34.3%
     [c6xdsp ]  5812226: LOAD: TSK: ALG1                : 0.4%
     [c6xdsp ]  5812226: LOAD: TSK: SCD_PROCESS_TSK1    : 16.7%
     [c6xdsp ]  5812226: LOAD: TSK: MISC                : 0.6%
     

    After enabling audio capture / encode

    [c6xdsp ]  5889225: LOAD: CPU: 65.6% HWI: 1.1%, SWI:0.9%
     [c6xdsp ]
     [c6xdsp ]  5889225: LOAD: TSK: IPC_FRAMES_IN0      : 1.9%
     [c6xdsp ]  5889225: LOAD: TSK: IPC_BITS_OUT0       : 0.1%
     [c6xdsp ]  5889225: LOAD: TSK: ALG0                : 36.0%
     [c6xdsp ]  5889225: LOAD: TSK: ALG1                : 0.5%
     [c6xdsp ]  5889225: LOAD: TSK: SCD_PROCESS_TSK1    : 17.8%
     [c6xdsp ]  5889225: LOAD: TSK: MISC                : 7.3%

     Is this in sync with your observation?

  • It maybe not a same  problem?

    in my testing ,

    if i can't encode the aac ,just read pcm,

    [c6xdsp ] CH | In Recv In Process User Skip Process Skip In Process Time
    [c6xdsp ] Num | FPS FPS FPS FPS per frame (msec)
    [c6xdsp ] ----------------------------------------------------------------
    [c6xdsp ]
    [c6xdsp ]
    [c6xdsp ] 51645: LOAD: CPU: 0.2% HWI: 0.0%, SWI:0.0%
    [c6xdsp ]
    [c6xdsp ] 51645: LOAD: TSK: MISC : 0.2%
    [c6xdsp ]

    if i encode the pcm to G711,

    [c6xdsp ] 
    [c6xdsp ] 3757680: LOAD: CPU: 0.2% HWI: 0.0%, SWI:0.0% 
    [c6xdsp ] 
    [c6xdsp ] 3757680: LOAD: TSK: MISC : 0.2% 
    [c6xdsp ]


    and if i encode the pcm to aaclc,

    [c6xdsp ] 
    [c6xdsp ] 119678: LOAD: CPU: 71.4% HWI: 2.4%, SWI:2.8% 
    [c6xdsp ] 
    [c6xdsp ] 119678: LOAD: TSK: MISC : 66.2% 
    [c6xdsp ]


    i also test the aaclc by samplerate 44.1kHZ,

    the dsp load is also more than 50%.

  • G711 encode happens from A8 side.

    You can enable function profiling of DSP side to see if RPE_process() takes longer time.

    In src_bios6/Makefile.mk, set DO_DSP_FXN_PROFILE to true.

    Recompile the code and execute the application. Note that the profiling is started in algLink in RDK code. If your use case doesnt use algLink, then you have to call Profile control code somewhere in your dsp side code for several times to enable profiling.

    The output will be something like this -

    [c6xdsp ]  FXNADDR #  COUNT 
     [c6xdsp ]  9efbc9a0#       304
     [c6xdsp ]  9efbca80#       442
     [c6xdsp ]  9efa7120#        44
     [c6xdsp ]  9efa2a00#        65
     [c6xdsp ]  9efb00c0#       142
     [c6xdsp ]  9ef77ae0#        65
     

    [c6xdsp ]   FXNHOOKOVERHEAD:356
     [c6xdsp ]   CPU_FREQ:1000000000
     [c6xdsp ]   TIMER_FREQ:1000000000
     [c6xdsp ]   FXNADDR #COUNT#MAXCYCLES#TOTALCYCLES
     [c6xdsp ]  9ef81a00# 3395#    35093#   29637967
     [c6xdsp ]  9efa9300# 3395#     6909#    1459229
     [c6xdsp ]  9efb0220# 4172#    17998#    2312489
     [c6xdsp ]  9efb7120#  298#    27377#    2737599
     [c6xdsp ]  9efbcb60#  469#    11576#     905340
     [c6xdsp ]  9efc6d60#  467#  6963640#   13316258
     [c6xdsp ]  9efbc9a0# 3869#     7262#    1849805

    Later you can mapp the function address to find the function taking most of the execution time. Again if its RPE process taking time nowhere closer to encoder data sheet number, its definitely due to caching issue.

  • I change the src_bios6/Makefile,mak,only set DO_DSP_FXN_PROFILE =true,

    and i rebuild the bios6,

    Some error has occurred

    the error log:

    /home/3.5/dvr_rdk/../ti_tools/cgt_dsp/cgt6x_7_3_5//bin/lnk6x --emit_warnings_as_errors --diag_warning=10063-D --display_error_number --warn_sections -q --silicon_version=6740 -c --dynamic -o2 -x --zero_init=off --retain=_Ipc_ResetVector /home/3.5/dvr_rdk/../dvr_rdk/build/dvr_rdk/obj/ti816x-evm/c6xdsp/release/main_c6xdsp.oe674 /home/3.5/dvr_rdk/../dvr_rdk/build/dvr_rdk/obj/ti816x-evm/c6xdsp/release/MAIN_APP_c6xdsp_pe674.oe674 /home/3.5/dvr_rdk/../dvr_rdk/build/dvr_rdk/obj/ti816x-evm/c6xdsp/release/dvr_rdk_configuro/linker_mod.cmd -o /home/3.5/dvr_rdk/../dvr_rdk/build/dvr_rdk/bin/ti816x-evm/dvr_rdk_c6xdsp_release_1024M_256M.xe674 -m /home/3.5/dvr_rdk/../dvr_rdk/build/dvr_rdk/bin/ti816x-evm/dvr_rdk_c6xdsp_release_1024M_256M.xe674.map -l/home/3.5/dvr_rdk/../dvr_rdk/build/mcfw/src_bios6/lib/ti816x-evm/c6xdsp/release/dvr_rdk_bios6.ae674 -l/home/3.5/dvr_rdk/../ti_tools/cgt_dsp/cgt6x_7_3_5//lib/rts6740_elf.lib -l/home/3.5/dvr_rdk/../ti_tools/framework_components/framework_components_3_22_02_08_patched/packages/ti/sdo/fc/ecpy/lib/debug/ecpy.ae674 -l/home/3.5/dvr_rdk/../dvr_rdk/mcfw/src_bios6/alg/scd/lib/scd.ae674 -l/home/3.5/dvr_rdk/../dvr_rdk/mcfw/src_bios6/alg/va/lib/vlib.ae674 -l/home/3.5/dvr_rdk/../dvr_rdk/mcfw/src_bios6/alg/va/lib/analytics.ae674 -l/home/3.5/dvr_rdk/../ti_tools/rpe/remote-processor-execute/lib/lib/c674/debug/rpe.ae674 -l/home/3.5/dvr_rdk/../ti_tools/codecs/c674x_aaclcdec_01_41_00_00_elf/packages/ti/sdo/codecs/aaclcdec/lib/aacdec_tii_lc_elf.l64P -l/home/3.5/dvr_rdk/../ti_tools/codecs/c674x_aaclcenc_01_00_01_00_elf_patched/packages/ti/sdo/codecs/aaclcenc/lib/mp4aacenc_tij_lc_elf.l67 /home/3.5/dvr_rdk/../dvr_rdk/mcfw/src_bios6/cfg/ti816x/link_algs.cmd
    "/home/3.5/dvr_rdk/../dvr_rdk/build/dvr_rdk/obj/ti816x-evm/c6xdsp/release/dvr_rdk_configuro/linker_mod.cmd", line 246: error #10099-D:
    run placement fails for object ".far", size 0x4dfd77 (page 0). Available
    ranges:
    DDR3_DSP size: 0xde1000 unused: 0x47c max hole: 0x478
    "/home/3.5/dvr_rdk/../dvr_rdk/build/dvr_rdk/obj/ti816x-evm/c6xdsp/release/dvr_rdk_configuro/linker_mod.cmd", line 241: error #10099-D:
    placement fails for object ".const", size 0x21ba8 (page 0). Available
    ranges:
    DDR3_DSP size: 0xde1000 unused: 0x4 max hole: 0x4
    "/home/3.5/dvr_rdk/../dvr_rdk/build/dvr_rdk/obj/ti816x-evm/c6xdsp/release/dvr_rdk_configuro/linker_mod.cmd", line 243: error #10099-D:
    placement fails for object ".fardata", size 0x30e2 (page 0). Available
    ranges:
    DDR3_DSP size: 0xde1000 unused: 0x4 max hole: 0x4
    "/home/3.5/dvr_rdk/../dvr_rdk/build/dvr_rdk/obj/ti816x-evm/c6xdsp/release/dvr_rdk_configuro/linker_mod.cmd", line 255: error #10099-D:
    run placement fails for object ".bss:taskStackSection", size 0xa6155 (page
    0). Available ranges:
    DDR3_DSP size: 0xde1000 unused: 0x4 max hole: 0x4
    "/home/3.5/dvr_rdk/../dvr_rdk/build/dvr_rdk/obj/ti816x-evm/c6xdsp/release/dvr_rdk_configuro/linker_mod.cmd", line 231: error #10099-D:
    run placement fails for object ".stack", size 0x4000 (page 0). Available
    ranges:
    DDR3_DSP size: 0xde1000 unused: 0x4 max hole: 0x4
    "/home/3.5/dvr_rdk/../dvr_rdk/build/dvr_rdk/obj/ti816x-evm/c6xdsp/release/dvr_rdk_configuro/linker_mod.cmd", line 252: error #10099-D:
    placement fails for object ".vecs", size 0x5ff (page 0). Available ranges:

    DDR3_DSP size: 0xde1000 unused: 0x4 max hole: 0x4
    "/home/3.5/dvr_rdk/../dvr_rdk/build/dvr_rdk/obj/ti816x-evm/c6xdsp/release/dvr_rdk_configuro/linker_mod.cmd", line 256: error #10099-D:
    placement fails for object "ti_sdo_ipc_init", size 0x44b (page 0).
    Available ranges:
    DDR3_DSP size: 0xde1000 unused: 0x4 max hole: 0x4
    "/home/3.5/dvr_rdk/../dvr_rdk/build/dvr_rdk/obj/ti816x-evm/c6xdsp/release/dvr_rdk_configuro/linker_mod.cmd", line 248: error #10099-D:
    placement fails for object ".cio", size 0x3c2 (page 0). Available ranges:
    DDR3_DSP size: 0xde1000 unused: 0x4 max hole: 0x4
    "/home/3.5/dvr_rdk/../dvr_rdk/build/dvr_rdk/obj/ti816x-evm/c6xdsp/release/dvr_rdk_configuro/linker_mod.cmd", line 244: error #10099-D:
    placement fails for object ".switch", size 0x37c (page 0). Available
    ranges:
    DDR3_DSP size: 0xde1000 unused: 0x4 max hole: 0x4
    "/home/3.5/dvr_rdk/../dvr_rdk/build/dvr_rdk/obj/ti816x-evm/c6xdsp/release/dvr_rdk_configuro/linker_mod.cmd", line 232: error #10099-D:
    placement fails for object "GROUP_1", size 0x154 (page 0). Available
    ranges:
    DDR3_DSP size: 0xde1000 unused: 0x4 max hole: 0x4
    warning #10063-D: entry-point symbol other than "_c_int00" specified:
    "ti_sysbios_family_c64p_Hwi0"
    error #10010: errors encountered during linking;
    "/home/3.5/dvr_rdk/../dvr_rdk/build/dvr_rdk/bin/ti816x-evm/dvr_rdk_c6xdsp_re
    lease_1024M_256M.xe674" not built
    make[2]: *** [/home/3.5/dvr_rdk/../dvr_rdk/build/dvr_rdk/bin/ti816x-evm/dvr_rdk_c6xdsp_release_1024M_256M.xe674] Error 1
    make[2]: Leaving directory `/home/3.5/dvr_rdk/mcfw/src_bios6/main_app'
    make[1]: *** [apps] Error 2
    make[1]: Leaving directory `/home/3.5/dvr_rdk/mcfw/src_bios6'
    make: *** [dvr_rdk_bios6] Error 2
    root@ubuntu:dvr_rdk#

  • You have to do some adjustment in memory configuration. In my case, reducing DSS_M3_BSS_SIZE by 2MB & increasing DSP_DATA_SIZE by 2MB worked.

    Try to build  with DO_DSP_FXN_PROFILE = false, check the map files to see unused memory sections & increase DSP_DATA_SIZE accordingly. In my case, there was more than 2MB unused in DSS_M3_BSS_SIZE.

  • please ,check my cache setting,is there any problem??

    int test programe,audio in/out buffer  user  sharedregion buffer  SR1(Bitstream buffer ).

    and in src_bios6/cfg/config_1g_128mlinux.bld, my memory map is :

    /* first 512MB */
    LINUX_SIZE = 128*MB;
    SR1_SIZE = 337.5*MB;
    SR3_INTRADUCATI_IPC_SIZE = 124*KB;
    VIDEO_M3_CODE_SIZE = 2.5*MB;
    VIDEO_M3_BSS_SIZE = 11.5*MB;
    VIDEO_M3_DATA_SIZE = 0.5*MB;
    DSS_M3_CODE_SIZE = 1.5*MB;
    DSS_M3_BSS_SIZE = 14.1*MB;
    DSS_M3_DATA_SIZE = 1.9*MB;
    DSP_CODE_SIZE = 900*KB;
    DSP_DATA_SIZE = 13.5*MB;

    /*

    Memory Map - 1GB DDR, upto 128MB DDR.

    +-0x80000000-+ +-------------------+
    ^ | |
    | | |
    | | 128 MB | Linux
    | | |
    | +-------------------+
    | | 337.5 MB | (SR1) Bitstream buffer
    | | | Cached on A8. Cached on M3, although access by DMAs
    | +-------------------+
    | | 1 MB | (SR3)InterDucati IPC ListMP .Cached on M3
    | +-------------------+
    + | 2.5 MB | Video M3 Code
    512 MB +-------------------+
    + | 10 MB | Video M3 Data
    | +-------------------+
    | | 2 MB | VPSS M3 Code
    | +-------------------+
    | | 15.5 MB | VPSS M3 Data
    | +-------------------+
    | | 1.5 MB | DSP Code
    | +-------------------+
    v | 14 MB | DSP Data
    +-0xA0000000-+ +-------------------+
    ^ | | Tiled 8-bit region
    | | 128 MB |
    | +-------------------+
    | | 128 MB | Tiled 16-bit region
    | | |
    | +-------------------+
    | | |
    | | 233 MB | (SR2) Frame Buffer Region
    | | | VPSS - Video M3 Frame Buf
    | +-------------------+
    + | |
    512 MB | 16 MB | (SR0) Syslink MsgQ/IPC List MP
    + | | Non-cached on M3
    | +-------------------+
    | | 2 MB | VPSS M3 - VPDMA Descriptor
    | +-------------------+
    | | 2 MB | VPSS M3 - FBDev Shared Memory
    | +-------------------+
    | | 2 MB | Host - VPSS M3 Notify(For FBDev)
    | +-------------------+
    v | 1 MB | Remote Debug Print
    +-0xBFFFFFFF-+ +-------------------+
    */

    i also set the FC_RMAN_IRES_C6Xdsp.cfg,set the cache config:

    var Cache = xdc.useModule('ti.sysbios.family.c64p.Cache');
    /* Disable caching for HWspinlock addresses */
    Cache.MAR0_31 = 0x00000000;
    Cache.MAR32_63 = 0x00000000;
    /* Config/EDMA registers cache disabled */
    Cache.MAR64_95 = 0x00000000;
    Cache.MAR96_127 = 0x00000000;

    /* add by zhangmin ,set cache*/
    Cache.MAR128_159 = 0xffffffff

    /* TILER memory cache disabled - 0xA0000000*/
    Cache.MAR160_191 = 0x00000000;
    /* memory cache disabled - 0xC0000000*/
    Cache.MAR192_223 = 0x00000000;
    /* memory cache disabled - 0xE0000000*/
    Cache.MAR224_255 = 0x00000000;

  • This problem has been solved。

    set the SR1 buffer is cached .

    Thanks .

  • SR1 buffer was already cached in DVR RDK code.Did you change it to non-cached initially

  • in dvr_rdk 2.8,the cache is closed.

  • Dear Zhang,

    I am using VCSDK, it is based  on RDK2.8 version.

    I have same issue with you, but I don't know how to enable the cache for DSP.

    Can you tell me how to enable the cache?!

    note: my ram is 2GB. I modified the memory map.

    thx ~

    HB