DM8168 McFW/Link API with one HDMI and two channel SD outputs

Trading Hawk

Hi!

We are planning a system based on the DM8168 DVR_RDK from UDworks.
For our use case we need to connect one HDMI and two SD CVBS (D1 480i/576i) output interfaces to the DM8168.
Our plans are to use the on-chip HDMI and on-chip SD DAC as in the DVR_RDK and replace the external HDMI encoder with another external SD DAC (e.g. ADV7343 or SAA7129AH) attached to VOUT0 or VOUT1.

What kind of changes do we need to support one HDMI and two SD outs beneath McFW and/or Link API?
Do we need to adapt e.g. the HDVPSS M3 code or will this use case be supported via Link API setup changes only?
Any recommendations on selecting VOUT0 vs VOUT1?

On-chip HDMI is connected to HD_VENC_D and associated Link API node name is HDCOMP?
So HDCOMP and SD should stay as they are and we'd need to change node HDMI (DVO1/VOUT1) or DVO2 (DV2/VOUT0)
to support a second FVID2_STD_NTSC/FVID2_STD_PAL capable Link API node?

Hope we get some help from you as the whole material seems to be quite complex with lots of acronyms with little documentation about the inner workings.

Thank you in advance

Tr.Hawk

over 11 years ago

0 Margarita Gashova over 11 years ago

TI__Guru* 80190 points

Hello,

l'll try to involve someone to help here.

Best Regards,

Margarita

0 Shiju Sivasankaran over 11 years ago in reply to Margarita Gashova

TI__Genius 13395 points

PFA the info that can be used to set 2 SD displays with Netra. Please see the attachemnts for the same and see if that helps

regards, shiju

3288.mod.zip

0068.readme.txt

I tried to configure 576i output on HDCOMP.  We couldn�t use DVO2 here as EVM or DVR board does not support this mode, due to this we choose HDCOMP for the validation.  Our main intention is to verify the SWMS output and the necessary changes required in the HDVPSS driver to support PAL on HDCOMP or DVO1/2.

 

The HDCOMP is working fine for PAL mode.  I have used two displays, HDCOMP and SD-VENC

Configured the HDCOMP output as 576i (PAL display) 
Set the swMsInstId as SYSTEM_SW_MS_SC_INST_DEIHQ_SC_NO_DEI for SWMS instance connected to HDCOMP display 
Configured the SD output as NTSC 
Set the swMsInstId as SYSTEM_SW_MS_SC_INST_SC5 for SWMS instance connected to SD display 
Input of both the displays are switched between 420SP & 422I data format 
Both HDCOMP & SD displays worked well (NO green patches, No artifacts, No video rolling) 
The above test validates our SWMS outputs and HDVPSS driver changes 
 

To get this working, first of all we need to apply the attached patch on top of hdvpss_01_00_01_36 driver. Steps to apply the patch

Copy HDVENC_PAL.patch into hdvpss_01_00_01_36 directory 
Run �patch -p2 < HDVENC_PAL.patch� 
Please note that this patch is only for testing the PAL output on DVO2, we will make the official release later

Apart from the patch we need to make a couple of changes in RDK to support PAL output on HDCOMP, mainly the changes are in 

 

demos/mcfw_api_demos/mcfw_demo/demo_vcap_venc_vdec_vdis.c � Both HDMI & HDCOMP resolution is set to VSYS_STD_PAL (both are changes because of tiled VENC, no need to change both if VENCs are not tied. This is an application level change, so do the same change in App 
mcfw/src_bios6/links_m3vpss/display/displayLink_drv.c � modify the scan format of SYSTEM_LINK_ID_DISPLAY_0 as FVID2_SF_INTERLACED 
mcfw/src_bios6/links_m3vpss/system/system_dctrl.c � modified the display controller mesh setting and added a new entry for PAL in System_getClk() 
mcfw/src_linux/mcfw_api/ti_vdis.c � Modified the DVO format & scan format as VDIS_DVOFMT_SINGLECHAN and SYSTEM_DF_YUV422SP_UV respectively 
 

I am also attached the original & modified RDK files, so that you will be able to see the exact changes  

Please note that we have done changes to configure HDCOMP output, so appropriate changes needs to be done for DVO2

2605.HDVENC_PAL.zip

0804.ori.zip

0 Trading Hawk over 11 years ago in reply to Shiju Sivasankaran

Prodigy 155 points

Thank you all for your prompt replies. We need some time to check your advices. I will come back here soon with the results and/or further questions... ;-)

0 Piero Madar over 11 years ago in reply to Trading Hawk

Prodigy 10 points

Hi Trading Hawk,

Was just reading this thread and wondering what your result or outcome was? We have a similar design requirement.

0 Trading Hawk over 11 years ago in reply to Piero Madar

Prodigy 155 points

Hi Piero,

the patches look promising, though I found no time yet to try to compile them myself.

We are heading for one SD converter on VOUT0/DVO2.

And we are adding an optional clock inverter because of errata "Advisory 2.1.47 HDVPSS VOUT[x]_CLK: Does Not Support Positive-Edge Clocking".

So, sorry, I'm still unable to give a final answer. This has to wait until we get the prototype.

HTH

Hawk

0 Holger Eberhard102906 over 10 years ago in reply to Trading Hawk

Genius 4570 points

Currently we do a rework of our DM8168 based system.
The system is based on Udworks design and DVRRDK 03.00.00.00.
We try to use SAA7129 on DV02 for a second CVBS video output.
The DV02 is tied to HDCOMP.
Output format of DV02 and HDCOMP is 720x576 progressive.
I get some problems with SAA7129 to encode PAL from progressive
input to interlaced output.
One solution may be to set 720x576 interlaced output to DV02.
Is it possible to use the changes from Shiju Sivasankaran to achieve
this in DVRRDK 03.00.00.00 ?

0 Brijesh Jadav over 10 years ago in reply to Holger Eberhard102906

TI__Guru**** 399120 points

yes

0 Holger Eberhard102906 over 9 years ago in reply to Brijesh Jadav

Genius 4570 points

Ok, I have added the changes, but I am not sure what is to be modified for DVO2 for PAL 720x576@30..

We have tied HDCOMP to DVO2, the external encoder SAA7129 is connected to DVO2.

What else is to do to get interlaced PAL at DVO2 ?

0 Brijesh Jadav over 9 years ago in reply to Holger Eberhard102906

TI__Guru**** 399120 points

Hi,

Can you first try enabling internal color bar and see if it is correct? You can enable internal color bar by setting bit 15 at the offset 0x4810a000.

Regards,

Brijesh

0 Holger Eberhard102906 over 9 years ago in reply to Brijesh Jadav

Genius 4570 points

The problem seems to be another.
SAA7129 expects a clock of 27 MHz.
But the timing setting for interlaced PAL is:
VDIS_TIMINGS_PAL "216000,720/16/58/64,576/6/31/6,0"

In progressive mode I can see colorbars but the colors are not right and the bars
are 2 times in a frame.
In this case we use:
VDIS_TIMINGS_576P "27000,720/12/68/64,576/5/39/5,1"

0 Brijesh Jadav over 9 years ago in reply to Holger Eberhard102906

TI__Guru**** 399120 points

In progressive mode, pixel clock should be set to 54MHz and it should be in bt1120 mode.

In interlaced mode, can you try below timings?

VDIS_TIMINGS_576P "27000,720/12/69/63,576/2/19/3,1"

Regards,

Brijesh

0 Holger Eberhard102906 over 9 years ago in reply to Brijesh Jadav

Genius 4570 points

PFA snapshots of DVO2 colorbars interlaced and progessive mode via SAA7129. I have used the following values: #define VDIS_TIMINGS_PAL "27000,720/12/69/63,576/2/19/3,0" and #define VDIS_TIMINGS_576P "27000,720/12/69/63,576/2/19/3,1"

Another problem is, that I can not initialize the following: vdisParams.deviceParams[VDIS_DEV_HDCOMP].resolution = VSYS_STD_PAL; Vdis_tiedVencInit(VDIS_DEV_HDCOMP, VDIS_DEV_DVO2, &vdisParams); In this case I get no clock at DVO2.

instead I use: vdisParams.deviceParams[VDIS_DEV_HDCOMP].resolution = VSYS_STD_1080P_60; and later I set the resolution to VSYS_STD_PAL.

Interlaced:

Progressive:

0 Holger Eberhard102906 over 9 years ago in reply to Holger Eberhard102906

Genius 4570 points

I have some questions:
1.)
Is it possible to use PAL 576p resolution in VDIS_DVOFMT_SINGLECHAN mode ?
I did read that only 16/24 bit mode is supported in this case.
This would force us to use interlaced mode for SAA7129 because it is connected via 8 bit.

2.)
I have added some debug trace to watch if the patch for vpshal_hdvenc.c does work.
Interlaced mode for DVO2 seems no work now in my hdvpss.
I could see that the following part was not executed:

if (FVID2_STD_PAL == vencCfg->hdVencMode)
        {
            *(volatile unsigned int *)0x48100114 = 0x8000E;
            regsOvly->CFG1 = 0x003F0275u;
            regsOvly->CFG2 = 0x1EA500BBu;
            regsOvly->CFG3 = 0x1F9901C2u;
            regsOvly->CFG4 = 0x1FD71E67u;
            regsOvly->CFG5 = 0x304001C2u;
            regsOvly->CFG6 = 0xFF200200u;
            regsOvly->CFG7 = 0x1B6C0B35u;
            regsOvly->CFG8 = 0x1C0C0C30u;
            regsOvly->CFG9 = 0x1C0C0C30u;
            regsOvly->CFG10 = 0x00271360u;
            regsOvly->CFG11 = 0x3F150018u;
            regsOvly->CFG12 = 0x3F2D0089u;
            regsOvly->CFG13 = 0x00000139u;
            regsOvly->CFG14 = 0x0003F32Du;
            regsOvly->CFG15 = 0x042D008Au;
            regsOvly->CFG16 = 0x00019008u;
            regsOvly->CFG17 = 0x01120151u;
            regsOvly->CFG18 = 0x01001120u;
            regsOvly->CFG19 = 0x0100213Au;
            regsOvly->CFG20 = 0x0013913Bu;
            regsOvly->CFG21 = 0x042D0082u;
            regsOvly->CFG22 = 0x00019008u;
            regsOvly->CFG23 = 0x01120152u;
            regsOvly->CFG24 = 0x01001120u;
            regsOvly->CFG25 = 0x0100013Au;
        }

If I force the execution - than I get problems when we want to access I2C.
*(volatile unsigned int *)0x48100114 = 0x8000E; is the reason for this.
Is this register OK for DM8168 ?

Best regards

Holger

0 Brijesh Jadav over 9 years ago in reply to Holger Eberhard102906

TI__Guru**** 399120 points

Hi,

0x48100114 is a HDVPSS register, it should not at all affect I2C. This register settings are correct and validated by other customers, instead of trying with complete dvr-rdk, can you try with the hdvpss first and see if it works fine.

Regarding color bar, it looks like height is getting programmed correctly, i will relook into settings.

Rgds,

Brijesh

0 Holger Eberhard102906 over 9 years ago in reply to Brijesh Jadav

Genius 4570 points

Thanks for Your reply,
I will be not in my office for some days, if I am back I will connect a evaluation board
with a well working encoder via 8 bit port.
Next step will be to run HDVPSS standalone with this external encoder,
if this is running - I will add SAA7129 and last step will be the complete application I hope.

Best regards
Holger

0 Brijesh Jadav over 9 years ago in reply to Holger Eberhard102906

TI__Guru**** 399120 points

ok, that looks correct, please make sure you are using the settings that has been shared on that link.

Rgds,

Brijesh

0 Holger Eberhard102906 over 9 years ago in reply to Brijesh Jadav

Genius 4570 points

I have checked again the settings that has been shared from Shiju Sivasankaran. The difference to the source of Shiju is that this was made for HDCOMP output. Currently for me it's not clear what I must do to get interlaced PAL at DVO2 with tied HDCOMP.

I have attached a summary of my changes and vpshal_hdvenc.c. Every change is marked by //>> <<//.

7674.changes.txt





Changes in demo_vcap_venc_vdec_vdis.c
##########################################################################################


    /* Setup Vdis context */
    vdisParams.deviceParams[VDIS_DEV_HDMI].resolution = VSYS_STD_1080P_60;

//20140519heb- Changed for HDCOMP / DVO2 interlaced mode
//>>
         vdisParams.deviceParams[VDIS_DEV_HDCOMP].resolution = VSYS_STD_PAL;
//         vdisParams.deviceParams[VDIS_DEV_HDCOMP].resolution = VSYS_STD_1080P_60;
//<<
         /* If HDCOMP and DVO2 are tied together they must have same resolution */
        vdisParams.deviceParams[VDIS_DEV_DVO2].resolution = vdisParams.deviceParams[VDIS_DEV_HDCOMP].resolution;
        /* This call will set tiedDevicesMask internally in VDIS to tie HDCOMP and DVO2 together.
           This call will also set resolution for the tied vencs. Please note resolution for the tied vencs should be same. */
        Vdis_tiedVencInit(VDIS_DEV_HDCOMP, VDIS_DEV_DVO2, &vdisParams);

    vdisParams.deviceParams[VDIS_DEV_SD].resolution = VSYS_STD_PAL;





Changes in ti_vdis.c.c
##########################################################################################

 in Void Vdis_params_init(VDIS_PARAMS_S * pContext):



    pContext->tiedDevicesMask = VDIS_VENC_HDMI | VDIS_VENC_DVO2;
//20140519heb- Replaced SII9022 by SAA7129
//>>
//   pContext->enableConfigExtVideoEncoder = TRUE;
    pContext->enableConfigExtVideoEncoder = FALSE;
//<<

#if defined(TI814X_DVR) || defined(TI810X_DVR)
    pContext->enableConfigExtVideoEncoder = FALSE;
#endif

    pContext->deviceParams[VDIS_DEV_DVO2].enable = TRUE;
    pContext->deviceParams[VDIS_DEV_DVO2].outputInfo.vencNodeNum = VDIS_VENC_DVO2;
    pContext->deviceParams[VDIS_DEV_DVO2].outputInfo.aFmt = VDIS_A_OUTPUT_COMPOSITE;
    pContext->deviceParams[VDIS_DEV_DVO2].outputInfo.dvoFidPolarity = VDIS_POLARITY_ACT_HIGH;
    pContext->deviceParams[VDIS_DEV_DVO2].outputInfo.dvoVsPolarity = VDIS_POLARITY_ACT_HIGH;
    pContext->deviceParams[VDIS_DEV_DVO2].outputInfo.dvoHsPolarity = VDIS_POLARITY_ACT_HIGH;
    pContext->deviceParams[VDIS_DEV_DVO2].outputInfo.dvoActVidPolarity = VDIS_POLARITY_ACT_HIGH;
//20140519heb- Replaced SII9022 by SAA7129
//>>
//    pContext->deviceParams[VDIS_DEV_DVO2].outputInfo.dvoFmt = VDIS_DVOFMT_DOUBLECHAN;
    pContext->deviceParams[VDIS_DEV_DVO2].outputInfo.dvoFmt = VDIS_DVOFMT_SINGLECHAN;
//<<
    pContext->deviceParams[VDIS_DEV_DVO2].outputInfo.dataFormat = SYSTEM_DF_YUV422SP_UV;

    pContext->deviceParams[VDIS_DEV_HDMI].enable = TRUE;
    pContext->deviceParams[VDIS_DEV_HDMI].outputInfo.vencNodeNum = VDIS_VENC_HDMI;
    pContext->deviceParams[VDIS_DEV_HDMI].outputInfo.aFmt = VDIS_A_OUTPUT_COMPOSITE;
    pContext->deviceParams[VDIS_DEV_HDMI].outputInfo.dvoFmt = VDIS_DVOFMT_TRIPLECHAN_EMBSYNC;
    pContext->deviceParams[VDIS_DEV_HDMI].outputInfo.dataFormat = SYSTEM_DF_RGB24_888;

    pContext->deviceParams[VDIS_DEV_SD].enable = TRUE;
    pContext->deviceParams[VDIS_DEV_SD].outputInfo.vencNodeNum = VDIS_VENC_SD;
    pContext->deviceParams[VDIS_DEV_SD].outputInfo.aFmt = VDIS_A_OUTPUT_COMPOSITE;
    pContext->deviceParams[VDIS_DEV_SD].outputInfo.dvoFmt = VDIS_DVOFMT_TRIPLECHAN_DISCSYNC;
    pContext->deviceParams[VDIS_DEV_SD].outputInfo.dataFormat = SYSTEM_DF_RGB24_888;

#if defined(TI_816X_BUILD) || defined (TI_8107_BUILD)
    pContext->deviceParams[VDIS_DEV_HDCOMP].enable = TRUE;
    pContext->deviceParams[VDIS_DEV_HDCOMP].outputInfo.vencNodeNum = VDIS_VENC_HDCOMP;
    pContext->deviceParams[VDIS_DEV_HDCOMP].outputInfo.aFmt = VDIS_A_OUTPUT_COMPONENT;
    pContext->deviceParams[VDIS_DEV_HDCOMP].outputInfo.dvoFmt = VDIS_DVOFMT_TRIPLECHAN_EMBSYNC;
#if defined (TI_8107_BUILD)
    pContext->deviceParams[VDIS_DEV_HDCOMP].outputInfo.dvoFmt = VDIS_DVOFMT_TRIPLECHAN_DISCSYNC;
#endif
#if defined(TI816X_DVR) || defined(TI8107_DVR) || defined(TI8107_EVM)
        pContext->deviceParams[VDIS_DEV_HDCOMP].outputInfo.dataFormat = SYSTEM_DF_RGB24_888;
#endif
#if defined (TI816X_EVM)
        pContext->deviceParams[VDIS_DEV_HDCOMP].outputInfo.dataFormat = SYSTEM_DF_YUV444P;
#endif
    pContext->tiedDevicesMask = VDIS_VENC_HDCOMP | VDIS_VENC_DVO2;
    pContext->enableEdgeEnhancement = TRUE;

#endif





Changes in displayLink_drv.c
##########################################################################################

 in Int32 DisplayLink_drvDisplayCreate(DisplayLink_Obj * pObj):

    switch (pObj->tskId)
    {
        default:
        case SYSTEM_LINK_ID_DISPLAY_0:
            pObj->displayInstId = VPS_DISP_INST_BP0;
//20140519heb- Added / changed for HDCOMP / DVO2 interlaced mode
//>>
            pFormat->scanFormat = FVID2_SF_INTERLACED;
//            pFormat->scanFormat = FVID2_SF_PROGRESSIVE;
//<<
            break;

        case SYSTEM_LINK_ID_DISPLAY_1:
            pObj->displayInstId = VPS_DISP_INST_BP1;
            pFormat->scanFormat = FVID2_SF_PROGRESSIVE;
            break;

        case SYSTEM_LINK_ID_DISPLAY_2:
            pObj->displayInstId = VPS_DISP_INST_SEC1;
            pFormat->scanFormat = FVID2_SF_INTERLACED;
            break;
    }





Changes in system_dctrl.c
##########################################################################################


Vps_DcConfig gSystem_dctrlTriDisplayConfigDvo2 = {
    VPS_DC_USERSETTINGS,                                   /* Use Case */
    /* Edge information */
    {
//20140519heb- Changed for HDCOMP / DVO2 interlaced mode
//>>
//     {VPS_DC_BP0_INPUT_PATH, VPS_DC_VCOMP_MUX}     ,
     {VPS_DC_BP1_INPUT_PATH, VPS_DC_VCOMP_MUX}     ,
//<<
     {VPS_DC_VCOMP_MUX, VPS_DC_VCOMP}     ,
     {VPS_DC_CIG_NON_CONSTRAINED_OUTPUT, VPS_DC_HDMI_BLEND}     ,
//20140519heb- Changed for HDCOMP / DVO2 interlaced mode
//>>
//     {VPS_DC_BP1_INPUT_PATH, VPS_DC_HDCOMP_MUX}     ,
     {VPS_DC_BP0_INPUT_PATH, VPS_DC_HDCOMP_MUX}     ,
//<<
     {VPS_DC_HDCOMP_MUX, VPS_DC_CIG_PIP_INPUT}     ,
     {VPS_DC_CIG_PIP_OUTPUT, VPS_DC_DVO2_BLEND}     ,
     {VPS_DC_CIG_PIP_OUTPUT, VPS_DC_HDCOMP_BLEND}     ,
     {VPS_DC_SEC1_INPUT_PATH, VPS_DC_SDVENC_MUX}     ,
     {VPS_DC_SDVENC_MUX, VPS_DC_SDVENC_BLEND}     ,
     {VPS_DC_GRPX0_INPUT_PATH, VPS_DC_HDMI_BLEND}     ,
     {VPS_DC_GRPX1_INPUT_PATH, VPS_DC_HDCOMP_BLEND}     ,
     {VPS_DC_GRPX1_INPUT_PATH, VPS_DC_DVO2_BLEND}
     }
    ,
    12,
    /* VENC information */
    {
     /* Mode information */
     {
      {VPS_DC_VENC_HDMI, {FVID2_STD_1080P_60}
       }
      ,                                                    /* 1080p30 is mode
                                                            * is overwritten
                                                            * later inside
                                                            * System_displayCtrlInit
                                                            */
//20140519heb- Changed for HDCOMP / DVO2 interlaced mode
//>>
//      {VPS_DC_VENC_HDCOMP, {FVID2_STD_1080P_60}
      {VPS_DC_VENC_HDCOMP, {FVID2_STD_PAL}

//<<
       }
      ,                                                    /* 1080p30 is mode
                                                            * is overwritten
                                                            * later inside
                                                            * System_displayCtrlInit
                                                            */
//20140519heb- Changed for HDCOMP / DVO2 interlaced mode
//>>
//      {VPS_DC_VENC_DVO2, {FVID2_STD_1080P_60}
      {VPS_DC_VENC_DVO2, {FVID2_STD_PAL}

//<<
       }
      ,                                                    /* 1080p30 is mode
                                                            * is overwritten
                                                            * later inside
                                                            * System_displayCtrlInit
                                                            */
      {VPS_DC_VENC_SD, {FVID2_STD_NTSC}
       }
      }
     ,
     (VPS_DC_VENC_DVO2 | VPS_DC_VENC_HDCOMP),              /* Tied VENC bit
                                                            * mask */
     4u                                                    /* Number of VENCs
                                                            */
     }
};



Int32 System_getClk(UInt32 displayRes)
{
    Int32 clkValue = VSYS_STD_MAX;
    switch(displayRes) {
        case VSYS_STD_1080P_30:
        case VSYS_STD_1080I_60:
            clkValue = 74250u;
        break;
        case VSYS_STD_720P_60:
            clkValue = 74250;
        break;
        case VSYS_STD_1080P_60:
        case VSYS_STD_1080P_50:
            clkValue = 148500u;
        break;
        case VSYS_STD_XGA_60:
            clkValue = 65000u;
        break;
        case VSYS_STD_SXGA_60:
            clkValue = 108000u;
        break;
//20140519heb- Added for HDCOMP / DVO2 interlaced mode
//>>
        case VSYS_STD_PAL:
            clkValue = 27000u;
        break;
//<<
        
        default:
            UTILS_assert(0);
        break;
    }
    return(clkValue);
}

8357.vpshal_hdvenc.c

0 Badri Narayanan over 9 years ago in reply to Holger Eberhard102906

TI__Guru 59700 points

Pls check if this post helps http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/717/p/268949/983511.aspx#983511

0 Holger Eberhard102906 over 9 years ago in reply to Badri Narayanan

Genius 4570 points

Thanks for the advice, currently I am not sure where my problem is.

To be safe I applied the patch to vpshal_hdvenc.c from version hdvpss_01_00_00_01_36. Otherwise I use version hdvpss_01_00_00_01_37_patched from DVRRDK 03.00.00.00. and added the patch manually.

The behavior currently is as following:

if *(volatile unsigned int *)0x48100114 = 0x8000E; is executed in vpshal_hdvenc.c than we do not have 27 MHz clock at VOUT0_CLK. In this case the 27 MHz clock only occurs if I set vdisParams.deviceParams[VDIS_DEV_HDCOMP].resolution = VSYS_STD_1080P_60; and later during initialization I change the format to VSYS_STD_PAL.

The color bars are visible 4 times in the display, (if I show OSD it is better visible that the display contains the same 4 times like in a 2x2 mosaic).

Initialization seems to be ok, but a warning occurs "[m3vpss ] PLATFORM: UNKNOWN CPU detected, defaulting to VPS_PLATFORM_CPU_REV_2_0" (attached teraterm.log).

6866.teraterm.log


U-Boot 2010.06-svn616 (Apr 25 2014 - 10:27:19)

TI8168-GP rev 2.1

ARM clk: 1000MHz
DDR clk: 796MHz
HDVICP clk: 600MHz
L3 Fast clk: 560MHz
HDVPSS clk: 280MHz
Ducati M3 clk: 280MHz
DSP clk: 800MHz

I2C:   ready
DRAM:  2 GiB
NAND:  HW ECC BCH8 Selected
1024 MiB
MMC:   OMAP SD/MMC: 0
Net:   Ethernet PHY: GENERIC @ 0x01
DaVinci EMAC
Initializing USB ...
musb-hdrc: ConfigData=0xde (UTMI-8, dyn FIFOs, bulk combine, bulk split, HB-ISO Rx, HB-ISO Tx, SoftConn)
musb-hdrc: MHDRC RTL version 2.0 
musb-hdrc: setup fifo_mode 4
musb-hdrc: 28/31 max ep, 16384/16384 memory
USB Host mode controller at 47401000 using PIO, IRQ 0
Hit any key to stop autoboot:  1  0 

Read WEB update notify area
NAND read: 0x80757B84 device 0 offset 0xcf60000, size 0x8
 8 bytes read: OK

NO firmware update via WEB interface was launched, continue...
USB0:   scanning bus 0 for devices... 2 USB Device(s) found
0 Storage Device(s) found

NO USB device found
NO USB storage device attachedConnect speed 100M Full
Using DaVinci EMAC device
host 192.168.72.100 is alive
Connect speed 100M Full
Using DaVinci EMAC device
TFTP from server 192.168.72.100; our IP address is 192.168.72.200
Filename 'uImage_DM816X_DVR'.
Load address: 0x81000000
Loading: *#################################################################
	 #################################################################
	 ##########################################
done
Bytes transferred = 2519704 (0x267298)
## Booting kernel from Legacy Image at 81000000 ...
   Image Name:   Linux-2.6.37+
   Created:      2014-04-24  15:36:49 UTC
   Image Type:   ARM Linux Kernel Image (uncompressed)
   Data Size:    2519640 Bytes = 2.4 MiB
   Load Address: 80008000
   Entry Point:  80008000
   Verifying Checksum ... OK
   Loading Kernel Image ... OK
OK

Starting kernel ...

Linux version 2.6.37+ (heb@heb) (gcc version 4.3.3 (Sourcery G++ Lite 2009q1-203) ) #1 Thu Apr 24 17:36:40 CEST 2014
CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c53c7f
CPU: VIPT nonaliasing data cache, VIPT aliasing instruction cache
Machine: ti8168_dvr
vram size = 20971520 at 0x0
reserved size = 20971520 at 0x0
FB: Reserving 20971520 bytes SDRAM for VRAM
Memory policy: ECC disabled, Data cache writeback
OMAP chip is TI8168 2.0
Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 145488
Kernel command line: rootdelay=2 console=ttyO2,115200n8 init=/linuxrc root=/dev/nfs rw nfsroot=192.168.72.100:/home/heb/tftpboot/rfs_816x ip=192.168.72.200:192.168.72.100:192.168.1.1:255.255.255.0::eth0:off vram=20M notifyk.vpssm3_sva=0xBEE00000 mem=128M mem=472M@0xC0000000 vmalloc=580M
PID hash table entries: 2048 (order: 1, 8192 bytes)
Dentry cache hash table entries: 65536 (order: 6, 262144 bytes)
Inode-cache hash table entries: 32768 (order: 5, 131072 bytes)
Memory: 128MB 452MB = 580MB total
Memory: 583264k/583264k available, 31136k reserved, 139264K highmem
Virtual kernel memory layout:
    vector  : 0xffff0000 - 0xffff1000   (   4 kB)
    fixmap  : 0xfff00000 - 0xfffe0000   ( 896 kB)
    DMA     : 0xffc00000 - 0xffe00000   (   2 MB)
    vmalloc : 0xd4000000 - 0xf8000000   ( 576 MB)
    lowmem  : 0x80000000 - 0xd3c00000   (1340 MB)
    pkmap   : 0x7fe00000 - 0x80000000   (   2 MB)
    modules : 0x7f000000 - 0x7fe00000   (  14 MB)
      .init : 0x80008000 - 0x8003a000   ( 200 kB)
      .text : 0x8003a000 - 0x804c2000   (4640 kB)
      .data : 0x804c2000 - 0x8050e000   ( 304 kB)
SLUB: Genslabs=11, HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
NR_IRQS:407
IRQ: Found an INTC at 0xfa200000 (revision 5.0) with 128 interrupts
Total of 128 interrupts on 1 active controller
GPMC revision 6.0
Trying to install interrupt handler for IRQ400
Trying to install interrupt handler for IRQ401
Trying to install interrupt handler for IRQ402
Trying to install interrupt handler for IRQ403
Trying to install interrupt handler for IRQ404
Trying to install interrupt handler for IRQ405
Trying to install interrupt handler for IRQ406
Trying to install type control for IRQ407
Trying to set irq flags for IRQ407
OMAP clockevent source: GPTIMER1 at 27000000 Hz
Console: colour dummy device 80x30
Calibrating delay loop... 999.42 BogoMIPS (lpj=4997120)
pid_max: default: 32768 minimum: 301
Security Framework initialized
Mount-cache hash table entries: 512
CPU: Testing write buffer coherency: ok
devtmpfs: initialized
omap_voltage_early_init: voltage driver support not added
regulator: core version 0.5
regulator: dummy: 
NET: Registered protocol family 16
omap_voltage_domain_lookup: Voltage driver init not yet happened.Faulting!
omap_voltage_add_dev: VDD specified does not exist!
OMAP GPIO hardware version 0.1
OMAP GPIO hardware version 0.1

 drivers/spi/spi.c spi_init 
omap_mux_init: Add partition: #1: core, flags: 0
3-wired eeprom init done. (H/W ver:ffff)
_omap_mux_get_by_name: Could not find signal i2c2_scl.i2c2_scl
_omap_mux_get_by_name: Could not find signal i2c2_sda.i2c2_sda
registered ti816x_sr device
pm_dbg_init: only OMAP3 supported
registered ti81xx_vpss device
registered ti81xx_vidout device
registered ti81xx on-chip HDMI device
registered ti81xx_fb device
ti81xx_pcie: Invoking PCI BIOS...
ti81xx_pcie: Setting up Host Controller...
ti81xx_pcie: Register base mapped @0xd4020000
ti81xx_pcie: Starting PCI scan...
PCI: bus0: Fast back to back transfers disabled
PCI: bus1: Fast back to back transfers disabled
pci 0000:00:00.0: BAR 8: assigned [mem 0x20000000-0x200fffff]
pci 0000:01:00.0: BAR 0: assigned [mem 0x20000000-0x20001fff 64bit]
pci 0000:01:00.0: BAR 0: set to [mem 0x20000000-0x20001fff 64bit] (PCI address [0x20000000-0x20001fff])
pci 0000:00:00.0: PCI bridge to [bus 01-01]
pci 0000:00:00.0:   bridge window [io  disabled]
pci 0000:00:00.0:   bridge window [mem 0x20000000-0x200fffff]
pci 0000:00:00.0:   bridge window [mem pref disabled]
PCI: enabling device 0000:00:00.0 (0140 -> 0143)
bio: create slab <bio-0> at 0
vgaarb: loaded
SCSI subsystem initialized
usbcore: registered new interface driver usbfs
usbcore: registered new interface driver hub
usbcore: registered new device driver usb
USBSS revision 4ea20809
registerd cppi-dma Intr @ IRQ 17
Cppi41 Init Done
omap_i2c omap_i2c.1: bus 1 rev4.0 at 400 kHz
regulator: pmbus_vr: 800 <--> 1050 mV at 1000 mV 
regulator: tps40400 probe done.
omap_i2c omap_i2c.2: bus 2 rev4.0 at 400 kHz
Advanced Linux Sound Architecture Driver Version 1.0.23.
Switching to clocksource gp timer
musb-hdrc: version 6.0, host, debug=0
musb-hdrc musb-hdrc.0: dma type: dma-cppi41
MUSB controller-0 revision 4ea20800
musb-hdrc musb-hdrc.0: MUSB HDRC host driver
musb-hdrc musb-hdrc.0: new USB bus registered, assigned bus number 1
usb usb1: New USB device found, idVendor=1d6b, idProduct=0002
usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1
usb usb1: Product: MUSB HDRC host driver
usb usb1: Manufacturer: Linux 2.6.37+ musb-hcd
usb usb1: SerialNumber: musb-hdrc.0
hub 1-0:1.0: USB hub found
hub 1-0:1.0: 1 port detected
musb-hdrc musb-hdrc.0: USB Host mode controller at d401e000 using DMA, IRQ 18
musb-hdrc musb-hdrc.1: dma type: dma-cppi41
MUSB controller-1 revision 4ea20800
musb-hdrc musb-hdrc.1: MUSB HDRC host driver
musb-hdrc musb-hdrc.1: new USB bus registered, assigned bus number 2
usb usb2: New USB device found, idVendor=1d6b, idProduct=0002
usb usb2: New USB device strings: Mfr=3, Product=2, SerialNumber=1
usb usb2: Product: MUSB HDRC host driver
usb usb2: Manufacturer: Linux 2.6.37+ musb-hcd
usb usb2: SerialNumber: musb-hdrc.1
hub 2-0:1.0: USB hub found
hub 2-0:1.0: 1 port detected
musb-hdrc musb-hdrc.1: USB Host mode controller at d4026800 using DMA, IRQ 19
NET: Registered protocol family 2
IP route cache hash table entries: 16384 (order: 4, 65536 bytes)
TCP established hash table entries: 65536 (order: 7, 524288 bytes)
TCP bind hash table entries: 65536 (order: 6, 262144 bytes)
TCP: Hash tables configured (established 65536 bind 65536)
TCP reno registered
UDP hash table entries: 256 (order: 0, 4096 bytes)
UDP-Lite hash table entries: 256 (order: 0, 4096 bytes)
NET: Registered protocol family 1
RPC: Registered udp transport module.
RPC: Registered tcp transport module.
RPC: Registered tcp NFSv4.1 backchannel transport module.
NetWinder Floating Point Emulator V0.97 (double precision)
PMU: registered new PMU device of type 0
omap-iommu omap-iommu.0: ducati registered
omap-iommu omap-iommu.1: sys registered
highmem bounce pool size: 64 pages
JFFS2 version 2.2. (NAND) © 2001-2006 Red Hat, Inc.
msgmni has been set to 867
io scheduler noop registered
io scheduler deadline registered
io scheduler cfq registered (default)
Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
omap_uart.0: ttyO0 at MMIO 0x48020000 (irq = 72) is a OMAP UART0
omap_uart.1: ttyO1 at MMIO 0x48022000 (irq = 73) is a OMAP UART1
omap_uart.2: ttyO2 at MMIO 0x48024000 (irq = 74) is a OMAP UART2
console [ttyO2] enabled
brd: module loaded
loop: module loaded
omap2-nand driver initializing
ONFI flash detected
NAND device: Maf ID: 0x2c, Chip ID: 0xb3 (Micron, )
 erasesize: 0x20000, writesize: 2048, oobsize: 64
Creating 11 MTD partitions on "omap2-nand.0":
0x000000000000-0x000000240000 : "U-Boot"
0x000000240000-0x000000280000 : "U-Boot Env"
0x000000280000-0x000000580000 : "Boot Splash"
0x000000580000-0x0000009c0000 : "Kernel"
0x0000009c0000-0x0000086c0000 : "File System"
0x0000086c0000-0x00000cee0000 : "Firmware Upload"
0x00000cee0000-0x00000cf20000 : "BOP Keys"
0x00000cf20000-0x00000cf60000 : "BOP Config"
0x00000cf60000-0x00000cfa0000 : "Web update notify"
0x00000cfa0000-0x00000d2c0000 : "Update header"
0x00000d2c0000-0x000040000000 : "Reserved"
davinci_mdio davinci_mdio.0: davinci mdio revision 1.6
davinci_mdio davinci_mdio.0: detected phy mask fffffffd
usb 1-1: new high speed USB device using musb-hdrc and address 2
davinci_mdio.0: probed
davinci_mdio davinci_mdio.0: phy[1]: device 0:01, driver unknown
usbcore: registered new interface driver cdc_ether
usbcore: registered new interface driver dm9601
Initializing USB Mass Storage driver...
usbcore: registered new interface driver usb-storage
USB Mass Storage support registered.
usbcore: registered new interface driver usbserial
USB Serial support registered for generic
usb 1-1: New USB device found, idVendor=0409, idProduct=005a
usb 1-1: New USB device strings: Mfr=0, Product=0, SerialNumber=0
hub 1-1:1.0: USB hub found
hub 1-1:1.0: 4 ports detected
usbcore: registered new interface driver usbserial_generic
usbserial: USB Serial Driver core
USB Serial support registered for FTDI USB Serial Device
usbcore: registered new interface driver ftdi_sio
ftdi_sio: v1.6.0:USB FTDI Serial Converters Driver
USB Serial support registered for pl2303
usbcore: registered new interface driver pl2303
pl2303: Prolific PL2303 USB to serial adaptor driver
mice: PS/2 mouse device common for all mice
rtc-ds1307 1-0068: rtc core: registered ds1337 as rtc0
omap_rtc omap_rtc: rtc core: registered omap_rtc as rtc1
i2c /dev entries driver
Linux video capture interface: v2.00
usbcore: registered new interface driver uvcvideo
USB Video Class driver (v1.0.0)
OMAP Watchdog Timer Rev 0x00: initial timeout 60 sec
usbcore: registered new interface driver usbhid
usbhid: USB HID core driver
notify_init : notify drivercreated  for  remote proc id 2 at physical Address 0xbee00000
usbcore: registered new interface driver snd-usb-audio
Registered tvp5158 audio codec
asoc: tvp5158-hifi <-> davinci-mcasp.0 mapping ok
asoc: tlv320aic3x-hifi <-> davinci-mcasp.2 mapping ok
asoc: HDMI-DAI-CODEC <-> hdmi-dai mapping ok
ALSA device list:
  #0: TI81XX DVR
TCP cubic registered
NET: Registered protocol family 17
VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
omap_voltage_late_init: Voltage driver support not added
Power Management for TI81XX.
smartreflex-ti816x: ti816x_sr_probe done!
rtc-ds1307 1-0068: setting system clock to 2014-05-20 11:43:54 UTC (1400586234)
usb 1-1.4: new high speed USB device using musb-hdrc and address 3
usb 1-1.4: New USB device found, idVendor=0b95, idProduct=772a
usb 1-1.4: New USB device strings: Mfr=1, Product=2, SerialNumber=3
usb 1-1.4: Product: AX88772 
usb 1-1.4: Manufacturer: ASIX Elec. Corp.
usb 1-1.4: SerialNumber: 000001
davinci_mdio davinci_mdio.0: resetting idled controller
net eth0: attached PHY driver [Generic PHY] (mii_bus:phy_addr=0:01, id=2430d91)
IP-Config: Gateway not on directly connected network.
Waiting 2sec before mounting root device...
PHY: 0:01 - Link is Up - 100/Full
VFS: Mounted root (nfs filesystem) on device 0:15.
devtmpfs: mounted
Freeing init memory: 200K
###################################
#### -- rc.sh - start -------------
lrwxrwxrwx    1 root     root            17 May 20 11:44 /var/log -> /var/volatile/log
lrwxrwxrwx    1 root     root            17 May 20 11:44 /mnt/hdd/log -> /var/volatile/log
#### -- ready: temporary create logger files in /var/log
###################################
 Mounting /proc             : [SUCCESS]
 Mounting /sys              : [SUCCESS]
 Mounting /dev              : [SUCCESS]
 Mounting /dev/pts          : [SUCCESS]
 Populating /dev            : [SUCCESS]
lrwxrwxrwx    1 review   1000            12 May 20 11:33 /var/tmp -> volatile/tmp

May 20 13:44:08 192 user.notice root: #### -- init_816x.sh - START
*** Bootargs Validated for mem param ***
*** Bootargs Validated for notifyk.vpssm3 params ***
Kernel bootargs validated
numid=101,iface=MIXER,name='Left DAC Mux'
  ; type=ENUMERATED,access=rw------,values=1,items=3
  ; Item #0 'DAC_L1'
  ; Item #1 'DAC_L3'
  ; Item #2 'DAC_L2'
  : values=2
numid=99,iface=MIXER,name='Right DAC Mux'
  ; type=ENUMERATED,access=rw------,values=1,items=3
  ; Item #0 'DAC_R1'
  ; Item #1 'DAC_R3'
  ; Item #2 'DAC_R2'
  : values=2
 [c6xdsp ] Remote Debug Shared Memory @ 0xbf000000
 [m3video] Remote Debug Shared Memory @ 0xbf005020
 [m3vpss ] Remote Debug Shared Memory @ 0xbf00a040
May 20 13:44:10 192 user.notice root: DMP ./init.sh - insmod syslink.ko
SysLink version : 2.10.02.17
SysLink module created on Date:Apr 24 2014 Time:17:37:03
Trace enabled
Trace SetFailureReason enabled
./init.sh: line 43: LoggerClear: not found
May 20 13:44:12 bd-10310013 syslog.info syslogd started: BusyBox v1.19.4
May 20 13:44:12 bd-10310013 user.notice kernel: klogd started: BusyBox v1.19.4 (2014-04-24 17:46:17 CEST)
 Setting DMM priority for [DUCATI  ] to [0] ( 0x4e000624 = 0x08000000 )
 Setting DMM priority for [HDVICP0 ] to [2] ( 0x4e000634 = 0x0000000a )
 Setting DMM priority for [HDVICP1 ] to [2] ( 0x4e000634 = 0x000a0000 )
 Setting DMM priority for [HDVICP2 ] to [2] ( 0x4e000634 = 0x00a00000 )
Attached to slave procId 2.
Loaded file ../firmware/dvr_rdk_fw_m3vpss.xem3 on slave procId 2.
Started slave procId 2.
After Ipc_loadcallback status [0x00000000]
After Ipc_startcallback status [0x097d2000]
May 20 13:44:13 bd-10310013 user.info : [m3vpss ] ***** SYSTEM  : Frequency <ORG> - 250000000, <NEW> - 250000000
May 20 13:44:13 bd-10310013 user.info : [m3vpss ] notify_attach  rtnVal  0
May 20 13:44:13 bd-10310013 user.info : [m3vpss ] initProxyServer  rtnVal  0
May 20 13:44:13 bd-10310013 user.info : [m3vpss ]  
May 20 13:44:13 bd-10310013 user.info : [m3vpss ]  *** UTILS: CPU KHz = 500000 Khz ***
May 20 13:44:13 bd-10310013 user.info : [m3vpss ]  
May 20 13:44:13 bd-10310013 user.info : [m3vpss ]  48: SYSTEM: IPC init in progress !!!
May 20 13:44:13 bd-10310013 user.info : [m3vpss ]  48: SYSTEM: Attaching to [HOST] ... 
May 20 13:44:13 bd-10310013 user.info : [m3vpss ]  1047: SYSTEM: Attaching to [HOST] ... 
May 20 13:44:13 bd-10310013 user.info : [m3vpss ]  1049: SYSTEM: Attaching to [HOST] ... SUCCESS !!!
May 20 13:44:13 bd-10310013 user.info : [m3vpss ]  1049: SYSTEM: Attaching to [DSP] ... 
Attached to slave procId 1.
Loaded file ../firmware/dvr_rdk_fw_m3video.xem3 on slave procId 1.
Started slave procId 1.
After Ipc_loadcallback status [0x00000000]
After Ipc_startcallback status [0x00000000]
May 20 13:44:15 bd-10310013 user.info : [m3video] ***** SYSTEM  : Frequency <ORG> - 250000000, <NEW> - 250000000
May 20 13:44:15 bd-10310013 user.info : [m3vpss ]  2049: SYSTEM: Attaching to [DSP] ... 
May 20 13:44:15 bd-10310013 user.info : [m3video]  
May 20 13:44:15 bd-10310013 user.info : [m3video]  *** UTILS: CPU KHz = 500000 Khz ***
May 20 13:44:15 bd-10310013 user.info : [m3video]  
May 20 13:44:15 bd-10310013 user.info : [m3video]  1615: SYSTEM: IPC init in progress !!!
May 20 13:44:15 bd-10310013 user.info : [m3video]  1615: SYSTEM: Attaching to [HOST] ... 
May 20 13:44:15 bd-10310013 user.info : [m3video]  2614: SYSTEM: Attaching to [HOST] ... 
May 20 13:44:15 bd-10310013 user.info : [m3video]  2617: SYSTEM: Attaching to [HOST] ... SUCCESS !!!
May 20 13:44:15 bd-10310013 user.info : [m3video]  2617: SYSTEM: Attaching to [DSP] ... 
Attached to slave procId 0.
Loaded file ../firmware/dvr_rdk_fw_c6xdsp.xe674 on slave procId 0.
Started slave procId 0.
After Ipc_loadcallback status [0x00000000]
After Ipc_startcallback status [0x00000000]
May 20 13:44:16 bd-10310013 user.info : [c6xdsp ] ***** SYSTEM  : Frequency <ORG> - 800000000, <NEW> - 800000000
May 20 13:44:16 bd-10310013 user.info : [m3video]  3616: SYSTEM: Attaching to [DSP] ... 
May 20 13:44:16 bd-10310013 user.info : [m3vpss ]  3049: SYSTEM: Attaching to [DSP] ... 
May 20 13:44:16 bd-10310013 user.info : [c6xdsp ]  
May 20 13:44:16 bd-10310013 user.info : [c6xdsp ]  *** UTILS: CPU KHz = 800000 Khz ***
May 20 13:44:16 bd-10310013 user.info : [c6xdsp ]  
May 20 13:44:16 bd-10310013 user.info : [c6xdsp ]  5: SYSTEM: IPC init in progress !!!
May 20 13:44:16 bd-10310013 user.info : [c6xdsp ]  5: SYSTEM: Attaching to [HOST] ... 
May 20 13:44:16 bd-10310013 user.info : [c6xdsp ]  1012: SYSTEM: Attaching to [HOST] ...DMA: Module install successful, device major num = 251 
 
May 20 13:44:DRV: Module install successful
16 bd-10310013 uDRV: Module built on May 19 2014 09:27:32 
ser.info : [c6xdsp ]  1014: SYSTEM: Attaching to [HOST] ... SUCCESS !!!
May 20 13:44:16 bd-10310013 user.info : [c6xdsp ]  1014: SYSTEM: Attaching to [VIDEO-M3] ... 
May 20 13:44:16 bd-10310013 user.info : [m3vpss ]  4049: SYSTEM: Attaching to [DSP] ... 
May 20 13:44:16 bd-10310013 user.info kernel: DMA: Module install successful, device major num = 251 
May 20 13:44:16 bd-10310013 user.info kernel: DRV: Module install successful
May 20 13:44:16 bd-10310013 user.info kernel: DRV: Module built on May 19 2014 09:27:32 
 [c6xdsp ] Remote Debug Shared Memory @ 0xbf000000
 [m3video] Remote Debug Shared Memory @ 0xbf005020
 [m3vpss ] Remote Debug Shared Memory @ 0xbf00a040
May 20 13:44:16 bd-10310013 user.info : [m3video]  4616: SYSTEM: Attaching to [DSP] ... 
May 20 13:44:17 bd-10310013 user.info : [m3vpss ]  5049: SYSTEM: Attaching to [DSP] ... 
May 20 13:44:17 bd-10310013 user.info : [c6xdsp ]  2021: SYSTEM: Attaching to [VIDEO-M3] ... 
May 20 13:44:17 bd-10310013 user.info : [c6xdsp ]  2501: SYSTEM: Attaching to [VIDEO-M3] ... SUCCESS !!!
May 20 13:44:17 bd-10310013 user.info : [m3video]  5616: SYSTEM: Attaching to [DSP] ... 
May 20 13:44:17 bd-10310013 user.info : [c6xdsp ]  2501: SYSTEM: Attaching to [VPSS-M3] ... 
May 20 13:44:17 bd-10310013 user.info : [m3video]  5617: SYSTEM: Attaching to [DSP] ... SUCCESS !!!
May 20 13:44:17 bd-10310013 user.info : [m3video]  5617: SYSTEM: Attaching to [VPSS-M3] ... 
May 20 13:44:18 bd-10310013 user.info : [m3vpss ]  6049: SYSTEM: Attaching to [DSP] ... 
May 20 13:44:18 bd-10310013 user.info : [m3video]  6616: SYSTEM: Attaching to [VPSS-M3] ... 
May 20 13:44:18 bd-10310013 user.info : [c6xdsp ]  3508: SYSTEM: Attaching to [VPSS-M3] ... 
May 20 13:44:19 bd-10310013 user.info : [c6xdsp ]  3780: SYSTEM: Attaching to [VPSS-M3] ... SUCCESS !!!
May 20 13:44:19 bd-10310013 user.info : [m3vpss ]  7049: SYSTEM: Attaching to [DSP] ... 
May 20 13:44:19 bd-10310013 user.info : [c6xdsp ]  3780: SYSTEM: Opening MsgQ Heap [IPC_MSGQ_MSG_HEAP] ...
May 20 13:44:19 bd-10310013 user.info : [m3vpss ]  7049: SYSTEM: Attaching to [DSP] ... SUCCESS !!!
May 20 13:44:19 bd-10310013 user.info : [m3vpss ]  7050: SYSTEM: Attaching to [VIDEO-M3] ... 
May 20 13:44:19 bd-10310013 user.info : [m3video]  7616: SYSTEM: Attaching to [VPSS-M3] ... 
May 20 13:44:20 bd-10310013 user.info : [m3video]  8050: SYSTEM: Attaching to [VPSS-M3] ... SUCCESS !!!
May 20 13:44:20 bd-10310013 user.info : [m3vpss ]  8049: SYSTEM: Attaching to [VIDEO-M3] ... 
May 20 13:44:20 bd-10310013 user.info : [m3video]  8050: SYSTEM: Opening MsgQ Heap [IPC_MSGQ_MSG_HEAP] ...
May 20 13:44:20 bd-10310013 user.info : [m3vpss ]  8050: SYSTEM: Attaching to [VIDEO-M3] ... SUCCESS !!!
May 20 13:44:20 bd-10310013 user.info : [m3video]  8050: SYSTEM: Creating MsgQ [VIDEO-M3_MSGQ] ...
May 20 13:44:20 bd-10310013 user.info : [m3vpss ]  8050: SYSTEM: Creating MsgQ Heap [IPC_MSGQ_MSG_HEAP] ...
May 20 13:44:20 bd-10310013 user.info : [m3video]  8050: SYSTEM: Creating MsgQ [VIDEO-M3_ACK_MSGQ] ...
May 20 13:44:20 bd-10310013 user.info : [m3vpss ]  8050: SYSTEM: Creating MsgQ [VPSS-M3_MSGQ] ...
May 20 13:44:20 bd-10310013 user.info : [m3video]  8052: SYSTEM: Notify register to [HOST] line 0, event 15 ... 
May 20 13:44:20 bd-10310013 user.info : [m3vpss ]  8050: SYSTEM: Creating MsgQ [VPSS-M3_ACK_MSGQ] ...
May 20 13:44:20 bd-10310013 user.info : [m3video]  8052: SYSTEM: Notify register to [DSP] line 0, event 15 ... 
May 20 13:44:20 bd-10310013 user.info : [m3vpss ]  8052: SYSTEM: Notify register to [HOST] line 0, event 15 ... 
May 20 13:44:20 bd-10310013 user.info : [m3video]  8052: SYSTEM: Notify register to [VPSS-M3] line 0, event 15 ... 
May 20 13:44:20 bd-10310013 user.info : [m3vpss ]  8052: SYSTEM: Notify register to [DSP] line 0, event 15 ... 
May 20 13:44:20 bd-10310013 user.info : [m3video]  8052: SYSTEM: IPC init DONE !!!
May 20 13:44:20 bd-10310013 user.info : [m3vpss ]  8052: SYSTEM: Notify register to [VIDEO-M3] line 0, event 15 ... 
May 20 13:44:20 bd-10310013 user.info : [m3vpss ]  8052: SYSTEM: IPC init DONE !!!
May 20 13:44:20 bd-10310013 user.info : [m3vpss ]  8058: MEM: Shared Region 2: Base = 0xb0000000, Length = 0x0e9c0000 (233 MB) 
May 20 13:44:20 bd-10310013 user.info : [m3video]  8059: MEM: Shared Region 2: Base = 0xb0000000, Length = 0x0e9c0000 (233 MB) 
May 20 13:44:20 bd-10310013 user.info : [m3vpss ]  8059: MEM: Shared Region 1: Base = 0x88000000, Length = 0x15000000 (336 MB) 
May 20 13:44:20 bd-10310013 user.info : [m3video]  8059: MEM: Shared Region 1: Base = 0x88000000, Length = 0x15000000 (336 MB) 
May 20 13:44:20 bd-10310013 user.info : [m3vpss ] === HDVPSS Clocks are enabled ===
May 20 13:44:20 bd-10310013 user.info : [m3vpss ] === HDVPSS is fully functional ===
May 20 13:44:20 bd-10310013 user.info : [m3vpss ] === HDVPSS module is not in standby ===
May 20 13:44:20 bd-10310013 user.info : [m3vpss ] === I2C1 Clk is active ===
May 20 13:44:20 bd-10310013 user.info : [m3vpss ] PLATFORM: UNKNOWN CPU detected, defaulting to VPS_PLATFORM_CPU_REV_2_0
May 20 13:44:20 bd-10310013 user.info : [m3video]  8089: HDVICP: Doing PRCM for IVAHD[0] ... 
May 20 13:44:20 bd-10310013 user.info : [m3video]  8089: HDVICP: PRCM for IVAHD[0] ... DONE.
May 20 13:44:20 bd-10310013 user.info : [m3video]  8089: HDVICP: Doing PRCM for IVAHD[1] ... 
May 20 13:44:20 bd-10310013 user.info : [m3video]  8089: HDVICP: PRCM for IVAHD[1] ... DONE.
May 20 13:44:20 bd-10310013 user.info : [m3video]  8089: HDVICP: Doing PRCM for IVAHD[2] ... 
May 20 13:44:20 bd-10310013 user.info : [m3video]  8090: HDVICP: PRCM for IVAHD[2] ... DONE.
May 20 13:44:20 bd-10310013 user.info : [m3video]  8090: SYSTEM  : Initializing Links !!! 
May 20 13:44:20 bd-10310013 user.info : [m3video]  8122: SYSTEM  : Initializing Links ... DONE !!! 
May 20 13:44:20 bd-10310013 user.info : [m3vpss ] initPrms.isI2cInitReq = 0
May 20 13:44:20 bd-10310013 user.info : [c6xdsp ]  4787: SYSTEM: Opening MsgQ Heap [IPC_MSGQ_MSG_HEAP] ...
May 20 13:44:20 bd-10310013 user.info : [m3vpss ] initPrms.isI2cInitReq = 0
May 20 13:44:20 bd-10310013 user.info : [c6xdsp ]  4787: SYSTEM: Creating MsgQ [DSP_MSGQ] ...
May 20 13:44:20 bd-10310013 user.info : [c6xdsp ]  4787: SYSTEM: Creating MsgQ [DSP_ACK_MSGQ] ...
May 20 13:44:20 bd-10310013 user.info : [c6xdsp ]  4787: SYSTEM: Notify register to [HOST] line 0, event 15 ... 
May 20 13:44:20 bd-10310013 user.info : [c6xdsp ]  4787: SYSTEM: Notify register to [VIDEO-M3] line 0, event 15 ... 
May 20 13:44:20 bd-10310013 user.info : [c6xdsp ]  4788: SYSTEM: Notify register to [VPSS-M3] line 0, event 15 ... 
May 20 13:44:20 bd-10310013 user.info : [c6xdsp ]  4788: SYSTEM: IPC init DONE !!!
May 20 13:44:20 bd-10310013 user.info : [c6xdsp ]  4790: MEM: Shared Region 2: Base = 0xb0000000, Length = 0x0e9c0000 (233 MB) 
May 20 13:44:20 bd-10310013 user.info : [c6xdsp ] [module] vpss probe done.
 4790: MEM: Shared Region 1: Base = 0x88000000, Length = 0x15000000 (336 MB) 
May 20 13:44:20 bd-10310013 user.info : [c6xdsp ]  4751: SYSTEM  : RpeServer_init() done... Ret Val 0!!!
May 20 13:44:20 bd-10310013 user.info : [c6xdsp ] !!WARNING.Resource already registered:2
May 20 13:44:20 bd-10310013 user.info : [c6xdsp ]  4757: SYSTEM  : Initializing Links !!! 
May 20 13:44:20 bd-10310013 user.info : [c6xdsp ]  4767: SYSTEM  : Initializing Links ... DONE !!! 
May 20 13:44:20 bd-10310013 user.info : [m3vpss ]  8307: UTILS: DMA: HWI Cr[module] ti81xxfb probe done.
eate for INT63 !!!
May 20 13:44:20 bd-10310013 user.info : [m3vpss ]  8307: SYSTEM  : Initializing Links !!! 
May 20 13:44:20 bd-10310013 user.info : [m3vpss ]  8421: SYSTEM  : Initializing Links ... DONE !!! 
 [m3vpss ] Received character 's'
May 20 13:44:20 bd-10310013 user.info : [m3vpss ]  8422: SYSTEM  : Set SHDMI W1 rev 2.0
tatic L3 pressure for HDVPSS as High
 [c6xdsp ] Remote Debug Shared Memory @ 0xbf000000
 [m3video] Remote Debug Shared Memory @ 0xbf005020
 [[module] ti81xx_hdmi probe done.
m3vpss ] Remote Debug Shared Memory @ 0xbf00a040
 [m3video] Received character 's'
 [c6xdsp ] Remote Debug Shared Memory @ 0xbf000000
 [m3video] Remote Debug Shared Memory @ 0xbf005020
 [m3vpss ] Remote Debug Shared Memory @ 0xbf00a040
 [c6xdsp ] Received character 's'
/opt/ti816x
May 20 13:44:20 bd-10310013 user.warn kernel: [module] vpss probe done.
May 20 13:44:20 bd-10310013 user.warn kernel: [module] ti81xxfb probe done.
May 20 13:44:20 bd-10310013 user.info kernel: HDMI W1 rev 2.0
May 20 13:44:20 bd-10310013 user.warn kernel: [module] ti81xx_hdmi probe done.
May 20 13:44:20 bd-10310013 user.debug kernel: found best resolution: 1400x1050 (30)

May 20 11:45:20 bd-10310013 user.debug SAA7129 : --> saa7129_Initialize
May 20 11:45:20 bd-10310013 user.debug SAA7129 : Configuring SAA7129 encoder...
May 20 11:45:20 bd-10310013 user.debug SAA7129 : saa7127_set_std: Selecting 50 Hz PAL video Standard
May 20 11:45:20 bd-10310013 user.debug SAA7129 : saa7127_set_output_type: Selecting Composite output type
May 20 11:45:20 bd-10310013 user.debug SAA7129 : saa7127_set_input_type: Selecting Normal Encoder Input
May 20 11:45:20 bd-10310013 user.debug SAA7129 : saa7127_set_video_enable: Enable Video Output
May 20 11:45:20 bd-10310013 user.debug SAA7129 : Standard  PAL
May 20 11:45:20 bd-10310013 user.debug SAA7129 : Input:    normal
May 20 11:45:20 bd-10310013 user.debug SAA7129 : Output:   Composite
May 20 11:45:20 bd-10310013 user.debug SAA7129 : WSS:      disabled
May 20 11:45:20 bd-10310013 user.debug SAA7129 : VPS:      disabled
May 20 11:45:20 bd-10310013 user.debug SAA7129 : CC:       disabled
May 20 11:45:20 bd-10310013 user.debug SAA7129 : <-- saa7129_Initialize

May 20 11:45:20 bd-10310013 user.info DMP_VCAP_VENC_VDEC_VDIS : VcapVencVdecVdis_start: Channel details: Capture = 16 / Primary Encoder = 18 / Secondary Encoder = 17 / Decoder = 16 / Display = 32
May 20 11:45:20 bd-10310013 user.notice [host] :  0: SYSTEM: IPC init in progress !!!
May 20 11:45:20 bd-10310013 user.debug [host] : System_ipcMsgQTaskMain: TID=2846
May 20 11:45:20 bd-10310013 user.notice [host] :  27: SYSTEM: Notify register to [DSP] line 0, event 15 ... 
May 20 11:45:20 bd-10310013 user.notice [host] :  27: SYSTEM: Notify register to [VIDEO-M3] line 0, event 15 ... 
May 20 11:45:20 bd-10310013 user.notice [host] :  28: SYSTEM: Notify register to [VPSS-M3] line 0, event 15 ... 
May 20 11:45:20 bd-10310013 user.notice [host] :  29: SYSTEM: IPC init DONE !!!
May 20 11:45:20 bd-10310013 user.debug [host] : IpcBitsInLink_init: Task IpcBitsInLink_tskMain 0 created
May 20 11:45:20 bd-10310013 user.debug [host] : IpcBitsInLink_init: Task IpcBitsInLink_tskMain 1 created
May 20 11:45:20 bd-10310013 user.notice [host] :  31: SYSTEM: Creating ListMP [HOST_IPC_OUT_25] in region 0 ...
May 20 11:45:20 bd-10310013 user.debug [host] : IpcBitsOutLink_init: Task IpcBitsOutLink_tskMain 0 created
May 20 11:45:20 bd-10310013 user.notice [host] :  38: SYSTEM: Creating ListMP [HOST_IPC_OUT_26] in region 0 ...
May 20 11:45:20 bd-10310013 user.debug [host] : IpcBitsOutLink_init: Task IpcBitsOutLink_tskMain 1 created
May 20 11:45:20 bd-10310013 user.debug [host] : IpcFramesInLink_init: Task IpcFramesInLink_tskMain 0 created
May 20 11:45:20 bd-10310013 user.debug [host] : IpcFramesInLink_init: Task IpcFramesInLink_tskMain 1 created
May 20 11:45:20 bd-10310013 user.notice [host] :  50: SYSTEM: Creating ListMP [HOST_IPC_OUT_20] in region 0 ...
May 20 11:45:20 bd-10310013 user.debug [host] : IpcFramesOutLink_init: Task IpcFramesOutLink_tskMain 0 created
May 20 11:45:20 bd-10310013 user.notice [host] :  55: SYSTEM: Creating ListMP [HOST_IPC_OUT_21] in region 0 ...
May 20 11:45:20 bd-10310013 user.debug [host] : IpcFramesOutLink_init: Task IpcFramesOutLink_tskMain 1 created
May 20 11:45:20 bd-10310013 user.notice [host] :  67: SYSTEM: Creating ListMP [HOST_IPC_OUT_22] in region 0 ...
May 20 11:45:20 bd-10310013 user.debug [host] : IpcFramesOutLink_init: Task IpcFramesOutLink_tskMain 2 created
May 20 11:45:20 bd-10310013 user.debug [host] : SystemLink_init: Task SystemLink_tskMain created
May 20 11:45:20 bd-10310013 user.debug TI_VDIS :  Vdis_tiedVencInit: 318:

May 20 11:45:20 bd-10310013 user.debug DMP_VIDEO_RECORD : VcapVenc_Thread: TID=2870
May 20 11:45:20 bd-10310013 user.info MULTICH_PROGRESSIVE_VCAP_VENC_VDEC_VDIS : Entered usecase 16CH Progressive <816x> Cap/Enc/Dec/Dis
May 20 11:45:20 bd-10310013 user.notice TI_VCAP :  Vcap_configVideoDecoder: TVP5158-0 (0x5c): Detected video (720x288@50Hz, 1)
May 20 11:45:20 bd-10310013 user.notice TI_VCAP :  Vcap_configVideoDecoder: TVP5158-1 (0x5d):  NO Video Detected
May 20 11:45:20 bd-10310013 user.notice TI_VCAP :  Vcap_configVideoDecoder: TVP5158-2 (0x5e):  NO Video Detected
May 20 11:45:20 bd-10310013 user.notice TI_VCAP :  Vcap_configVideoDecoder: TVP5158-3 (0x5f):  NO Video Detected
May 20 13:45:25 bd-10310013 user.info : [m3vpss ]  81401: CAPTURE: VIP0 PortA capture mode is [ 8-bit, Pixel-mux Embedded Sync] !!! 
May 20 13:45:25 bd-10310013 user.info : [m3vpss ]  81489: CAPTURE: VIP0 PortB capture mode is [ 8-bit, Pixel-mux Embedded Sync] !!! 
May 20 13:45:25 bd-10310013 user.info : [m3vpss ]  81576: CAPTURE: VIP1 PortA capture mode is [ 8-bit, Pixel-mux Embedded Sync] !!! 
May 20 13:45:25 bd-10310013 user.info : [m3vpss ]  81663: CAPTURE: VIP1 PortB capture mode is [ 8-bit, Pixel-mux Embedded Sync] !!! 
May 20 13:45:25 bd-10310013 user.info : [m3vpss ]  81764: CAPTURE: 0: 0xb48c0c80, 736 x 288, 00067800 B --> Extra Frames 
May 20 13:45:25 bd-10310013 user.info : [m3vpss ]  81764: CAPTURE: 1: 0xb4928480, 736 x 288, 00067800 B --> Extra Frames 
May 20 13:45:25 bd-10310013 user.info : [m3vpss ]  81764: CAPTURE: 2: 0xb498fc80, 736 x 288, 00067800 B --> Extra Frames 
May 20 13:45:25 bd-10310013 user.info : [m3vpss ]  81764: CAPTURE: 3: 0xb49f7480, 736 x 288, 00067800 B --> Extra Frames 
May 20 13:45:25 bd-10310013 user.info : [m3vpss ]  81764: CAPTURE: 4: 0xb4a5ec80, 736 x 288, 00067800 B --> Extra Frames 
May 20 13:45:25 bd-10310013 user.info : [m3vpss ]  81764: CAPTURE: 5: 0xb4ac6480, 736 x 288, 00067800 B --> Extra Frames 
May 20 13:45:25 bd-10310013 user.info : [m3vpss ]  UTILS: DMA: Allocated CH (TCC) = 58 (58)
May 20 13:45:26 bd-10310013 user.info : [m3vpss ]  82120: DEI     : Loading Up-scaling Co-effs
May 20 13:45:26 bd-10310013 user.info : [m3vpss ]  82120: DEI     : Co-effs Loading ... DONE !!!
May 20 13:45:26 bd-10310013 user.info : [m3vpss ]  82471: DEI     : Loading Up-scaling Co-effs
May 20 13:45:26 bd-10310013 user.info : [m3vpss ]  82471: DEI     : Co-effs Loading ... DONE !!!
May 20 13:45:26 bd-10310013 user.info : [c6xdsp ]  71125: SYSTEM: Opening MsgQ [VPSS-M3_MSGQ] ...
May 20 13:45:26 bd-10310013 user.info : [c6xdsp ]  71128: ALG : Create in progress !!!
May 20 13:45:26 bd-10310013 user.info : [c6xdsp ]  71135: ALG : Create Done !!!
May 20 11:45:26 bd-10310013 user.debug [host] : IpcBitsOutLink_tskMain: TID=2850
May 20 11:45:26 bd-10310013 user.debug [host] : IpcBitsOutLink_periodicTaskFxn: TID=3141
May 20 13:45:26 bd-10310013 user.info : [m3video]  82501: SYSTEM: Opening MsgQ [HOST_MSGQ] ...
May 20 13:45:26 bd-10310013 user.info : [m3video]  82529: SYSTEM: Opening MsgQ [VPSS-M3_MSGQ] ...
May 20 13:45:26 bd-10310013 user.info : [m3vpss ]  82976: SYSTEM: Opening MsgQ [VIDEO-M3_MSGQ] ...
May 20 13:45:27 bd-10310013 user.info : [m3vpss ]  UTILS: DMA: Allocated CH (TCC) = 59 (59)
May 20 13:45:27 bd-10310013 user.info : [m3vpss ]  UTILS: DMA: Allocated CH (TCC) = 60 (60)
May 20 13:45:27 bd-10310013 user.info : [m3vpss ] SWMS: instance 0, sc id 5, start win 0 end win 17
May 20 13:45:27 bd-10310013 user.info : [m3vpss ]  UTILS: DMA: Allocated CH (TCC) = 61 (61)
May 20 13:45:27 bd-10310013 user.info : [m3vpss ]  UTILS: DMA: Allocated CH (TCC) = 62 (62)
May 20 13:45:27 bd-10310013 user.info : [m3vpss ] SWMS: instance 0, sc id 5, start win 0 end win 17
May 20 13:45:27 bd-10310013 user.info : [m3video] ENCLINK:INFO: !!!Number of output buffers for ch[35] set to [1]
May 20 13:45:27 bd-10310013 user.info : [m3vpss ] 83392:WARN
May 20 13:45:27 bd-10310013 user.info : [m3vpss ] 83392:TILER AllocFailed:CntMode:0,Width=896,Height=640
May 20 13:45:27 bd-10310013 user.info : [m3vpss ] 83514:WARN
May 20 13:45:27 bd-10310013 user.info : [m3vpss ] 83514:TILER AllocFailed:CntMode:0,Width=896,Height=640
May 20 13:45:27 bd-10310013 user.info : [m3vpss ] 83518:WARN
May 20 13:45:27 bd-10310013 user.info : [m3vpss ] 83518:TILER AllocFailed:CntMode:0,Width=896,Height=640
May 20 13:45:27 bd-10310013 user.info : [m3vpss ] 83525:WARN
May 20 13:45:27 bd-10310013 user.info : [m3vpss ] 83525:TILER AllocFailed:CntMode:0,Width=896,Height=640
May 20 13:45:27 bd-10310013 user.info : [m3vpss ] 83529:WARN
May 20 13:45:27 bd-10310013 user.info : [m3vpss ] 83529:TILER AllocFailed:CntMode:0,Width=896,Height=640
May 20 13:45:27 bd-10310013 user.info : [m3vpss ] 83536:WARN
May 20 13:45:27 bd-10310013 user.info : [m3vpss ] 83536:TILER AllocFailed:CntMode:0,Width=896,Height=640
May 20 11:45:27 bd-10310013 user.debug [host] : IpcBitsInLink_tskMain: TID=2847
May 20 11:45:27 bd-10310013 user.notice [host] :  7312: IPC_BITS_IN   : ListMPOpen start !!!
May 20 13:45:27 bd-10310013 user.info : [m3vpss ] 83540:WARN
May 20 13:45:27 bd-10310013 user.info : [m3vpss ] 83541:TILER AllocFailed:CntMode:0,Width=896,Height=640
May 20 11:45:27 bd-10310013 user.notice [host] :  7316: IPC_BITS_IN   : ListMPOpen done !!!
May 20 11:45:27 bd-10310013 user.notice [host] :  7318: IPC_BITS_IN   : System_linkGetInfo done !!!
May 20 11:45:27 bd-10310013 user.debug [host] : IpcBitsInLink_periodicTaskFxn: TID=3184
May 20 13:45:27 bd-10310013 user.info : [m3vpss ] ==============FVID2_SETFMT STARTING===================
May 20 13:45:27 bd-10310013 user.info : [m3vpss ] ==============FVID2_SETFMT STARTED===================
May 20 13:45:27 bd-10310013 user.info : [m3vpss ] ==============FVID2_SETFMT STARTING===================
May 20 13:45:27 bd-10310013 user.info : [m3vpss ] ==============FVID2_SETFMT STARTED===================
May 20 11:45:27 bd-10310013 user.debug OSD_CAPTURE : OSD_Capture_Process_Thread: TID=3185
May 20 13:45:27 bd-10310013 user.info : [m3vpss ]  83623: DISPLAY: DVO2(BP1)  : 51 fps, Latency (Min / Max) = ( 255 / 0 ), Callback Interval (Min / Max) = ( 255 / 0 ) !!! 
May 20 13:45:27 bd-10310013 user.info : [m3vpss ]  83688: DISPLAY: SDDAC(SEC1): 15 fps, Latency (Min / Max) = ( 255 / 0 ), Callback Interval (Min / Max) = ( 255 / 0 ) !!! 
May 20 11:45:27 bd-10310013 user.info DMP_VCAP_VENC_VDEC_VDIS : Set default encoder sample aspect ratio
May 20 11:45:27 bd-10310013 user.warn DMP_ENCODE : dmp_EncodeSetAspectRatio: Set default SAR for 4:3, channel 16
May 20 11:45:27 bd-10310013 user.debug AUDIO_RECORD : Audio_Record_Thread: TID=3192
May 20 11:45:28 bd-10310013 user.debug DMP_VIDEO_PLAYBACK : VdecVdis_VideoPlayback_Thread: TID=3211
May 20 11:45:28 bd-10310013 user.debug DMP_CAMERA : Camera_Check_Process_Thread: TID=3212
May 20 11:45:28 bd-10310013 user.debug AVSERVER_MAIN_THREAD : AVSERVER_tskMain: TID=3237
May 20 11:45:28 bd-10310013 user.debug AVSERVER_MEM_MANAGER : MemMng_Init: Memory layout done, totalsize 106956928 0x6600880
kernel.shmmax = 0x8000000
May 20 11:45:28 bd-10310013 user.debug AVSERVER_STREAM : Msg_CTRL_Thread: TID=3240
May 20 11:45:28 bd-10310013 user.info AVSERVER_API : AVSERVER_rtspServerStart: Start wis-streamer
May 20 11:45:29 bd-10310013 user.notice WIS_STREAMER : Play stream Channel  5 using URL rtsp://0.0.0.0:8556/h264_ch6
May 20 11:45:29 bd-10310013 user.notice WIS_STREAMER : Play stream Channel  6 using URL rtsp://0.0.0.0:8557/h264_ch7
May 20 11:45:29 bd-10310013 user.notice WIS_STREAMER : Play stream Channel  2 using URL rtsp://0.0.0.0:8553/h264_ch3
May 20 11:45:29 bd-10310013 user.notice WIS_STREAMER : Play stream Channel  9 using URL rtsp://0.0.0.0:8560/h264_ch10
May 20 11:45:29 bd-10310013 user.notice WIS_STREAMER : Play stream Channel  4 using URL rtsp://0.0.0.0:8555/h264_ch5
May 20 11:45:29 bd-10310013 user.notice WIS_STREAMER : Play stream Channel 16 using URL rtsp://0.0.0.0:8567/h264_ch17
May 20 11:45:29 bd-10310013 user.notice WIS_STREAMER : Play stream Channel  8 using URL rtsp://0.0.0.0:8559/h264_ch9
May 20 11:45:29 bd-10310013 user.notice WIS_STREAMER : Play stream Channel 10 using URL rtsp://0.0.0.0:8561/h264_ch11
May 20 11:45:29 bd-10310013 user.notice WIS_STREAMER : Play stream Channel  3 using URL rtsp://0.0.0.0:8554/h264_ch4
May 20 11:45:29 bd-10310013 user.notice WIS_STREAMER : Play stream Channel 13 using URL rtsp://0.0.0.0:8564/h264_ch14
May 20 11:45:29 bd-10310013 user.notice WIS_STREAMER : Play stream Channel  0 using URL rtsp://0.0.0.0:8551/h264_ch1
May 20 11:45:29 bd-10310013 user.notice WIS_STREAMER : Play stream Channel 12 using URL rtsp://0.0.0.0:8563/h264_ch13
May 20 11:45:29 bd-10310013 user.notice WIS_STREAMER : Play stream Channel  7 using URL rtsp://0.0.0.0:8558/h264_ch8
May 20 11:45:29 bd-10310013 user.notice WIS_STREAMER : Play stream Channel 15 using URL rtsp://0.0.0.0:8566/h264_ch16
May 20 11:45:29 bd-10310013 user.notice WIS_STREAMER : Play stream Channel  1 using URL rtsp://0.0.0.0:8552/h264_ch2
May 20 11:45:29 bd-10310013 user.notice WIS_STREAMER : Play stream Channel 11 using URL rtsp://0.0.0.0:8562/h264_ch12
May 20 11:45:29 bd-10310013 user.notice WIS_STREAMER : Play stream Channel 14 using URL rtsp://0.0.0.0:8565/h264_ch15
May 20 11:45:29 bd-10310013 user.info DMP : dmp-module started successfully.
May 20 13:45:29 bd-10310013 user.info : [c6xdsp ]  74007: Core is active
May 20 13:45:29 bd-10310013 user.info : [m3video]  85703: Core is active
May 20 13:45:29 bd-10310013 user.info : [m3vpss ]  85702: Core is active

0 Holger Eberhard102906 over 9 years ago in reply to Holger Eberhard102906

Genius 4570 points

To verify that SAA7129 works correct, we disconnected SAA7129 from DM8168 DVO2 and connected an external video device via the 8-bit data bus to SAA7129.
We inserted video data and 27 MHz clock. Interlaced PAL video output from SAA7129 works fine in this case.
Settings of the SAA7129 encoder are OK.
Now we will reconnect SAA7129 to DM8168 DVO2 and go on solving the problem.

0 Holger Eberhard102906 over 9 years ago in reply to Holger Eberhard102906

Genius 4570 points

I have got the PAL interlaced video output via DVO2 and SAA7129 working. For testing purpose I went back to the demo version DVRRDK_03.00.00.00. With original usecase multich_progressive_vcap_venc_vdec_vdis and with a display combination HDMI/HDCOM/SD-Bypaß I can tie HDCOMP and DVO2. The patch works and PAL interlaced is OK via SAA7129.

In our modified usecase we can select 3 display combination (each combination with 2 independent mosics).

1. HDMI / SD

2. HDCOMP / SD

3. HDMI / HDCOMP /SD-Bypass

Our goal is to get the following display / mosaic combinations:

1. HDMI (1920x1080) / SD (720x576)

2. HDCOMP tied DVO2->SAA7129 (720x576) / SD (720x576)

I did try HDCOMP tied DVO2->SAA7129 / SD combination without success, that is the reason why I went back to the former original demo.

0 Holger Eberhard102906 over 9 years ago in reply to Holger Eberhard102906

Genius 4570 points

Last but not least I have video output running in both variants.
HDMI + SD and SD + SD via SAA7129 can be selected in initialization.
Thanks for the patch, thanks for the support.

0 Holger Eberhard102906 over 9 years ago in reply to Brijesh Jadav

Genius 4570 points

Try to close this post only.

0 Xavier over 7 years ago in reply to Shiju Sivasankaran

Genius 3180 points

Hi :

I want to output 576i video signal through DVO2/VOUT0, RGB 24bit, VDIS_DVOFMT_TRIPLECHAN_DISCSYNC;

in my application i want to dynamically change resolution to 1080p 30hz through DVO2 by fun vdis_setResolution,

I read the HDVENC_PAL.patch,　i have some questions:

1. Can i use this patch on TI81xx- HDVPSS- 01. 00. 01. 37 version as i use dvrrdk4.0 mcfw　？

2. In my application, i think your modified ti_vdis.c not be suitable ,

can i DVO2 with HDCOMP VDIS_DVOFMT_TRIPLECHAN_DISCSYNC, SYSTEM_DF_RGB24_888 instead,as DVO2 and HDCOMP tied together?

3. In displayLink_drv.c modified pFormat->scanFormat = FVID2_SF_INTERLACED;

and in file system_dctrl.c modified, FVID2_STD_PAL instead FVID2_STD_1080P,

after change, can i still dynamically change resolution to 1080p 30hz through DVO2 by fun vdis_setResolution?

best regards

0 Holger Eberhard102906 over 7 years ago in reply to Xavier

Genius 4570 points

Hi,

I did compare /hdvpss/dvr_rdk_hdvpss/packages/ti/psp/vps/hal/src/vpshal_hdvenc.c from DVRRDK 4
and hdvpss/hdvpss_01_00_01_37_patched/packages/ti/psp/vps/hal/src/vpshal_hdvenc.c from DVRRDK 3.
I found that some parts of the patch are already integrated in the DVRRDK 4 Version.

Please apply the patch to hdppss_01_00_01_31 and try to compare both Versions.

BR Holger

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DM8168 McFW/Link API with one HDMI and two channel SD outputs