What does the "AIC audio playback issues with 8168, 8107 DVRs fixed" mean?

SuitJune Young

Other Parts Discussed in Thread: DM8107

AIC audio playback issues with 8168, 8107 DVRs fixed

http://arago-project.org/git/projects/?p=linux-dvr-rdk-dm81xx.git;a=commitdiff;h=e35fe54fda60f15c6f84c95f115511d2ca11a68b

Just like the above link,it says that a issue with 8168 DVR.

What is the detailed issue?

Does it appears in the EVM board?

In the patch,a big change is that modify the clock mode.Make the DM8168 as the clock master.

Why do this change?

over 9 years ago

0 Sivagamy Govindasamy over 9 years ago

TI__Expert 6950 points

This patch is significant for DM8107 DVR - hdmi playback support was added. For DM8168, only some cleanup changes and audio capture related changes are done. Clock related changes are not relevant for playback.

0 SuitJune Young over 9 years ago in reply to Sivagamy Govindasamy

Genius 3985 points

+ /* McASP21_AHCLKX out to feed CODEC CLK*/

+ .clk_input_pin = MCASP_AHCLKX_OUT,

The above change is for AIC3x.

Why change the clock master/slave mode?

I remember that in the former doc,it says aic3x is a master and dm8168 as slave.

0 Sivagamy Govindasamy over 9 years ago in reply to SuitJune Young

TI__Expert 6950 points

Which doc are you referrring to?

I think this change is intentional. Ealier versions (not sure what version you are using) didnt have this variable clk_input_pin, but still internally setting to clock out at mcasp driver.

0 SuitJune Young over 9 years ago in reply to Sivagamy Govindasamy

Genius 3985 points

Clocking related changes

McASP2 on the TI81xx EVMs operates in a slave mode (codec driving the bit clock and the frame sync) and hence nothing specific handling is needed.

http://processors.wiki.ti.com/index.php/TI81xx_PSP_Porting_Guide

It says that DM8168's McASP is slave.

Why add a variable "clk_input_pin",to indicate which one is master/slave and perform the related operation?

0 SuitJune Young over 9 years ago in reply to SuitJune Young

Genius 3985 points

could TIer reply?

0 Steven Weng1 over 9 years ago in reply to SuitJune Young

Expert 2200 points

Hi SuitJune,

I think the "clk_input_pin=MCASP_AHCLKX_OUT" means the high frequency clock from McAsp AHCLKX output to codec MCLK and the codec CLKDIV_IN uses MCLK in codec driver.

The codec BCLK/WCLK is still master mode...(codec driving the bit clock BCLK and the frame sync WCLK)

But I have a question...

Because the codec MCLK in our board only connect to AHCLKR. Is it ok in codec playback mode?

This means that the codec MCLK only use AHCLKR pin as reference clock in the playback and capture mode.

Is it ok?

Thanks!

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What does the "AIC audio playback issues with 8168, 8107 DVRs fixed" mean?

Clocking related changes