DM8168 McASP not generating EDMA events AXEVT0,AREVT0

I'm configuring the McASP in the DM8168 (from the DSP core) to be driven by EDMA, and I don't see it generating any EDMA events.  EDMA is configured first, and is waiting on event triggers.  As soon as I take the McASP FS generators out of reset, the RSTAT and XSTAT registers show ROVRN and XUNDRN respectively, and the EDMA ER register remains all zeroes.  EDMA EER says that AXEVT0 and AREVT0 are enabled. The over/underrun is understandable if EDMA is not moving data.  My McASP and EDMA setup code is below.  Can anyone tell me what I'm missing?  

Thanks in advance,

Stu

void mcasp_init(void)
{

int loop1=0;

// From SPRUGX8, section 14.2.10.2

// step 1: Reset McASP to default values by setting GBLCTL = 0
REG_SETVAL(MCASP_GBLCTL_REG, 0x00000000);
REG_SETVAL(MCASP_RGBLCTL_REG, 0x00000000);
REG_SETVAL(MCASP_XGBLCTL_REG, 0x00000000);

// step 2a: Configure Power down and emulation management
REG_SETVAL(MCASP_PWREMUMGT_REG, (REG_GETREG(MCASP_PWREMUMGT_REG) | (
(0x1 <<1) // MCASP_SOFT = 1
)));

// step 2b: Configure Receive registers
REG_SETVAL(MCASP_RMASK_REG, 0xffffffff);

REG_SETVAL(MCASP_RFMT_REG, (
(0x0 <<0) + // RROT = 0
(0x0 <<3) + // RBUSEL = 0 (********Note: Use RBUSEL=1(ConfigBus) for Ready Bit Polling case only) || (Note: Use RBUSEL=0(DataPort) for EDMA/CpuInterrupt case only)
(0xF <<4) + // RSSZ = 0xF (32-bits)
(0x1 <<15) + // RRVRS = 1
(0x1 <<16) // RDATDLY = 1
));

REG_SETVAL(MCASP_AFSRCTL_REG, (
(0x1 <<0) + // FSRP = 1
(0x1 <<1) + // FSRM = 1
(0x1 <<4) + // FRWID = 1
(0x2 <<7) // RMOD = 2
));

REG_SETVAL(MCASP_ACLKRCTL_REG, (
(0x3 <<0) + //CLKRDIV = 3
(0x1 <<5) + // CLKRM = 1
(0x1 <<7) // CLKXP = 1
));

REG_SETVAL(MCASP_AHCLKRCTL_REG, (
(0xF <<0) + // HCLKRDIV = 15
(0x0 <<14) + // HCLKRP = 0
(0x1 <<15) // HCLKRM = 1
));

REG_SETVAL(MCASP_RTDM_REG, 0x3); // RTDMS = 3

REG_SETVAL(MCASP_RINTCTL_REG, (
(0x0 <<5) // RDATA = 0
));

REG_SETVAL(MCASP_RCLKCHK_REG, 0x00ff0000);

// step 2c: Configure Transmit registers

REG_SETVAL(MCASP_XMASK_REG, 0xffffffff); // //verify

REG_SETVAL(MCASP_XFMT_REG, (
(0x0 <<0) + // XROT = 0
(0x0 <<3) + // XBUSEL = 0 (********Note: Use XBUSEL=1(ConfigBus) for Ready Bit Polling case only) || (Note: Use XBUSEL=0(DataPort) for EDMA/CpuInterrupt case only)
(0xF <<4) + // XSSZ = 0xF (32-bits)
(0x1 <<15) + // XRVRS = 1
(0x1 <<16) // XDATDLY = 1
));

REG_SETVAL(MCASP_AFSXCTL_REG, (
(0x1 <<0) + // FSXP = 1
(0x1 <<1) + // FSXM = 1
(0x1 <<4) + // FXWID = 1
(0x2 <<7) // XMOD = 2
));

REG_SETVAL(MCASP_ACLKXCTL_REG, (
(0x3 <<0) + //CLKXDIV = 3
(0x1 <<5) + //CLKXM = 1
(0x0 <<6) + // ASYNC = 0
(0x1 <<7) // CLKXP = 1
));

REG_SETVAL(MCASP_AHCLKXCTL_REG, (
(0xF <<0) + // HCLKXDIV = 15
(0x0 <<14) + // HCLKXP = 0
(0x1 <<15) // HCLKXM = 1
));

REG_SETVAL(MCASP_XTDM_REG, 0x3); // XTDMS = 3

REG_SETVAL(MCASP_XINTCTL_REG, 0x0);

REG_SETVAL(MCASP_XCLKCHK_REG, 0x00ff0000);

// step 2d: Configure Serializer registers

REG_SETVAL(MCASP_SRCTL0_REG, (
(0x2 <<0) // SRMOD = 2 (Rx)
));

REG_SETVAL(MCASP_SRCTL1_REG, (
(0x0 <<0) // SRMOD = 0 (Inactive)
));

REG_SETVAL(MCASP_SRCTL2_REG, (
(0x0 <<0) // SRMOD = 0 (Inactive)
));

REG_SETVAL(MCASP_SRCTL3_REG, (
(0x0 <<0) // SRMOD = 0 (Inactive)
));

REG_SETVAL(MCASP_SRCTL4_REG, (
(0x0 <<0) // SRMOD = 0 (Inactive)
));

REG_SETVAL(MCASP_SRCTL5_REG, (
(0x1 <<0) // SRMOD = 1 (Tx)
));

// step 2e: Configure Global registers

REG_SETVAL(MCASP_PFUNC_REG, (0x1 << 25)); // AMUTE is GPIO

REG_SETVAL(MCASP_PDIR_REG, (
(0x0 <<0) + // AXR0 = 0 // Inputs (Rx)
(0x0 <<1) + // AXR1 = 0
(0x0 <<2) + // AXR2 = 0
(0x1 <<3) + // AXR3 = 1 // Outputs (Tx)
(0x1 <<4) + // AXR4 = 1
(0x1 <<5) + // AXR5 = 1
(0x1 <<25) + // AMUTE = 1
(0x1 <<26) + // ACLKX = 1
(0x1 <<27) + // AHCLKX = 1
(0x1 <<28) + // AFSX = 1
(0x0 <<29) + // ACLKR = 0
(0x0 <<30) + // AHCLKR = 0
(0x0 <<31) // AFSR = 0
));

// step 2f: Configure DIT registers
REG_SETVAL(MCASP_DITCTL_REG, (
(0x0 <<0) // DITEN = 0
));

REG_SETVAL(MCASP_DLBCTL_REG, 0x0);

REG_SETVAL(MCASP_PDOUT_REG, (0x1 <<25)); // assert AMUTE

// step 3a: Take high-freq clock dividers out of reset

REG_SETVAL(MCASP_GBLCTL_REG, (
(0x1 <<1) + // RHCLKRST = 1
(0x1 <<9) // XHCLKRST = 1
));

// step 3b: Wait for GBLCTL bits to latch

loop1=0;
while((REG_READBITS(MCASP_GBLCTL_REG, 0x202) != 0x202) && (loop1 < 100000)) // check for RHCLKRST=1 and XHCLKRST=1
loop1++;

if(loop1 == 100000)
{
hprintf(LOG_DEBUG,"\n McASP init failed to get RHCLKRST or XHCLKRST");
return;
}

// step 4a: Take internal serial clock dividers out of reset

REG_SETVAL(MCASP_GBLCTL_REG, (REG_GETREG(MCASP_GBLCTL_REG) | (
(0x1 <<0) + // RCLKRST = 1
(0x1 <<8) // XCLKRST = 1
)));

// step 4b: Wait for GBLCTL bits to latch

loop1=0;
while((REG_READBITS(MCASP_GBLCTL_REG, 0x101) != 0x101) && (loop1 < 100000)) // check for RCLKRST=1 and XCLKRST=1
loop1++;

if(loop1 == 100000)
{
hprintf(LOG_DEBUG,"\n McASP init failed to get RCLKRST or XCLKRST");
return;
}

//*************************************************************************************************//
// DO NOT DO this step-5 for ready bit polling case (meaning no-EDMA/no-CpuInterrupts). ignore Step-5 completely
// Step 5. Setup data acquisition as required: (Do below settings in this step only for EDMA case).
//NOTE: The WNUMEVT/RNUMEVT and WNUMDMA/RNUMDMA values must be set prior to enabling the Write FIFO/Read FIFO.
//If the Write FIFO/Read FIFO is to be enabled, it must be enabled prior to taking the McASP out of
//reset.

REG_SETVAL(MCASP_WFIFOCTL_REG, (
(0x1 <<0) + // WNUMDMA = 1 Tx serializers in sequoia
(0x20 <<8) // WNUMEVT = 32_words (256_bytes/(2_bytes * 1_serializers * 2_LRslots) = 64_words max depth available for FIFO. So 32 is chosen as optimal for EDMA) (Note: FIFO size=256 bytes, 1_words=NoOfSerializers)
));

REG_SETVAL(MCASP_WFIFOCTL_REG, (REG_GETREG(MCASP_WFIFOCTL_REG) | (
(0x1 <<16) // WENA = 1
)));

REG_SETVAL(MCASP_RFIFOCTL_REG, (
(0x1 <<0) + // RNUMDMA = 1_words Rx serializers in sequoia
(0x20 <<8) // RNUMEVT = 32_words (256_bytes/(2_bytes * 1_serializers * 2_LRslots) = 64_words max depth available for FIFO. So 32 is chosen as optimal for EDMA) (Note: FIFO size=256 bytes, 1_words=NoOfSerializers)
));

REG_SETVAL(MCASP_RFIFOCTL_REG, (REG_GETREG(MCASP_RFIFOCTL_REG) | (
(0x1 <<16) // RENA = 1
)));

//*************************************************************************************************//

//Step 6. Activate serializers.

// Step 6a: clear status regs
REG_SETVAL(MCASP_XSTAT_REG, 0x000001FF);
REG_SETVAL(MCASP_RSTAT_REG, 0x000001FF);

// Step 6b: take serializers out of reset

REG_SETVAL(MCASP_GBLCTL_REG, (REG_GETREG(MCASP_GBLCTL_REG) | (
(0x1 <<2) + // RSRCLR = 1
(0x1 <<10) // XSRCLR = 1
)));

// Step 6c: wait for GBLCTL bits to latch

loop1=0;
while((REG_READBITS(MCASP_GBLCTL_REG, 0x404) != 0x404) && (loop1 < 100000)) // check for RSRCLR=1 and XSRCLR=1
loop1++;

if(loop1 == 100000)
{
hprintf(LOG_DEBUG,"\n McASP init failed to get RSRCLR or XSRCLR");
return;
}

// Step 7: Verify that all transmit buffers are serviced

// Step 7a: clear XDATA bit in XSTAT
REG_SETVAL(MCASP_XSTAT_REG, REG_GETREG(MCASP_XSTAT_REG)); // note this reg is W1C (write 1 to clear)

// Step 7c: if polling, write to XBUF
// REG_SETVAL(MCASP_XBUF5_REG, 0x5555); // Do this for polling only

// Step 8a: take state machines out of reset

REG_SETVAL(MCASP_GBLCTL_REG, (REG_GETREG(MCASP_GBLCTL_REG) | (
(0x1 <<3) + // RSMRST = 1
(0x1 <<11) // XSMRST = 1
)));

// Step 8b: wait for GBLCTL bits to latch

loop1=0;
while((REG_READBITS(MCASP_GBLCTL_REG, 0x808) != 0x808) && (loop1 < 100000)) // check for RSMRST = 1 and XSMRST=1
loop1++;

if(loop1 == 100000)
{
hprintf(LOG_DEBUG,"\n McASP init failed to get RSMRST or XSMRST");
return;
}

// Step 9a: take frame sync generators out of reset

REG_SETVAL(MCASP_GBLCTL_REG, (REG_GETREG(MCASP_GBLCTL_REG) | (
(0x1 <<4) + // RFRST = 1
(0x1 <<12) // XFRST = 1
)));

// Step 9b: wait for GBLCTL bits to latch

loop1=0;
while((REG_READBITS(MCASP_GBLCTL_REG, 0x1010) != 0x1010) && (loop1 < 100000)) // check for RFRST = 1 and XFRST=1
loop1++;

if(loop1 == 100000)
{
hprintf(LOG_DEBUG,"\n McASP init failed to get RFRST or XFRST");
return;
}

hprintf(LOG_DEBUG,"McASP init completed");

}

void edma_init(void)

{

chNumMcASPRx = CSL_EDMA3_CHA_AREVT0;
chNumMcASPTx = CSL_EDMA3_CHA_AXEVT0;

tccMcASPRxPing = TCC_NUM_0;
tccMcASPRxPong = TCC_NUM_1;
tccMcASPTxPing = TCC_NUM_2;
tccMcASPTxPong = TCC_NUM_3;

ParamNumMcASPRxBasic = chNumMcASPRx;
ParamNumMcASPRxLinkPing = PARAM_NUM_72;
ParamNumMcASPRxLinkPong = PARAM_NUM_73;
ParamNumMcASPTxBasic = chNumMcASPTx;
ParamNumMcASPTxLinkPing = PARAM_NUM_74;
ParamNumMcASPTxLinkPong = PARAM_NUM_75;

CSL_edma3MapDMAChannelToParamBlock(hModule, chNumMcASPRx, ParamNumMcASPRxBasic);
CSL_edma3MapDMAChannelToParamBlock(hModule, chNumMcASPTx, ParamNumMcASPTxBasic);
CSL_edma3MapDMAChannelToEventQueue (hModule, chNumMcASPRx, CSL_EDMA3_QUE_2);
CSL_edma3MapDMAChannelToEventQueue (hModule, chNumMcASPTx, CSL_EDMA3_QUE_2);

EdmaEventHook(tccMcASPTxPing, edmaMcaspIsrFrameRxTxPing);
EdmaEventHook(tccMcASPTxPong, edmaMcaspIsrFrameRxTxPing);

regionAccess.region = EDMA_REGION ;
ullTemp = (unsigned long long)1 << chNumMcASPRx;
ullTemp |= (unsigned long long)1 << chNumMcASPTx;
ullTemp |= (unsigned long long)1 << tccMcASPRxPing;
ullTemp |= (unsigned long long)1 << tccMcASPRxPong;
ullTemp |= (unsigned long long)1 << tccMcASPTxPing;
ullTemp |= (unsigned long long)1 << tccMcASPTxPong;
regionAccess.drae = _loll(ullTemp);
regionAccess.draeh = _hill(ullTemp);

statusMcASP = CSL_edma3HwControl(hModule,CSL_EDMA3_CMD_DMAREGION_ENABLE, &regionAccess);
if (statusMcASP != CSL_SOK) {
Sys_CountMcASP ++;
return;
}

hModule->regs->TPCC_EMCR |= _loll(ullTemp);
hModule->regs->TPCC_EMCRH |= _hill(ullTemp);

chAttr.regionNum = EDMA_REGION;
chAttr.chaNum = chNumMcASPRx;
hChannelMcASPRx = CSL_edma3ChannelOpen(&chObjMcASPRx, CSL_EDMA3, &chAttr, &statusMcASP);
if ( (hChannelMcASPRx == NULL) || (statusMcASP != CSL_SOK)) {
Sys_CountMcASP ++;
return;
}
statusMcASP = CSL_edma3GetHwChannelSetupParam(hChannelMcASPRx,&ParamNumMcASPRxBasic);
if (statusMcASP != CSL_SOK) {
Sys_CountMcASP ++;
return;
}
hParamMcASPRxBasic = CSL_edma3GetParamHandle(hChannelMcASPRx,ParamNumMcASPRxBasic,&statusMcASP);
if (hParamMcASPRxBasic == NULL) {
Sys_CountMcASP ++;
return;
}
hParamMcASPRxLinkPing = CSL_edma3GetParamHandle(hChannelMcASPRx,ParamNumMcASPRxLinkPing,&statusMcASP);
if (hParamMcASPRxLinkPing == NULL) {
Sys_CountMcASP ++;
return;
}
hParamMcASPRxLinkPong = CSL_edma3GetParamHandle(hChannelMcASPRx,ParamNumMcASPRxLinkPong,&statusMcASP);
if (hParamMcASPRxLinkPong == NULL) {
Sys_CountMcASP ++;
return;
}
chAttr.regionNum = EDMA_REGION;
chAttr.chaNum = chNumMcASPTx;
hChannelMcASPTx = CSL_edma3ChannelOpen(&chObjMcASPTx, CSL_EDMA3, &chAttr, &statusMcASP);
if ( (hChannelMcASPTx == NULL) || (statusMcASP != CSL_SOK)) {
Sys_CountMcASP ++;
return;
}
statusMcASP = CSL_edma3GetHwChannelSetupParam(hChannelMcASPTx,&ParamNumMcASPTxBasic);
if (statusMcASP != CSL_SOK) {
Sys_CountMcASP ++;
return;
}
hParamMcASPTxBasic = CSL_edma3GetParamHandle(hChannelMcASPTx,ParamNumMcASPTxBasic,&statusMcASP);
if (hParamMcASPTxBasic == NULL) {
Sys_CountMcASP ++;
return;
}
hParamMcASPTxLinkPing = CSL_edma3GetParamHandle(hChannelMcASPTx,ParamNumMcASPTxLinkPing,&statusMcASP);
if (hParamMcASPTxLinkPing == NULL) {
Sys_CountMcASP ++;
return;
}
hParamMcASPTxLinkPong = CSL_edma3GetParamHandle(hChannelMcASPTx,ParamNumMcASPTxLinkPong,&statusMcASP);
if (hParamMcASPTxLinkPong == NULL) {
Sys_CountMcASP ++;
return;
}
regionIntr.region = EDMA_REGION ;
ullTemp = (unsigned long long)1 << tccMcASPRxPing;
ullTemp |= (unsigned long long)1 << tccMcASPRxPong;
ullTemp |= (unsigned long long)1 << tccMcASPTxPing;
ullTemp |= (unsigned long long)1 << tccMcASPTxPong;
regionIntr.intr = _loll(ullTemp);
regionIntr.intrh = _hill(ullTemp);
statusMcASP = CSL_edma3HwControl(hModule,CSL_EDMA3_CMD_INTR_ENABLE,&regionIntr);
if (statusMcASP != CSL_SOK) {
Sys_CountMcASP ++;
return;
}
myParamSetup.option = CSL_EDMA3_OPT_MAKE(CSL_EDMA3_ITCCH_DIS,
CSL_EDMA3_TCCH_DIS,
CSL_EDMA3_ITCINT_DIS,
CSL_EDMA3_TCINT_EN,
tccMcASPRxPing,
CSL_EDMA3_TCC_NORMAL,
CSL_EDMA3_FIFOWIDTH_NONE,
CSL_EDMA3_STATIC_DIS,
CSL_EDMA3_SYNC_AB,
CSL_EDMA3_ADDRMODE_INCR,
CSL_EDMA3_ADDRMODE_INCR);
myParamSetup.srcAddr = 0x46000000;
myParamSetup.dstAddr = make_l3_target_addr((Uint32)pEdmaRxTxBuffs->edmaRxPingBuffer);

/* Only move the slots with audio data */
myParamSetup.aCntbCnt = CSL_EDMA3_CNT_MAKE(NBYTES2, NUM_SLOTS_MCASP);

myParamSetup.cCnt = SAMPLES_PER_10ms;
myParamSetup.srcDstBidx = CSL_EDMA3_BIDX_MAKE(0, (SAMPLES_PER_10ms*NBYTES2));
myParamSetup.srcDstCidx = CSL_EDMA3_CIDX_MAKE(0, NBYTES2);

myParamSetup.linkBcntrld = CSL_EDMA3_LINKBCNTRLD_MAKE ((Uint32) hParamMcASPRxLinkPong, 0);
statusMcASP = CSL_edma3ParamSetup(hParamMcASPRxBasic,&myParamSetup);
if (statusMcASP != CSL_SOK) {
Sys_CountMcASP ++;
return;
}
statusMcASP = CSL_edma3ParamSetup(hParamMcASPRxLinkPing,&myParamSetup);
if (statusMcASP != CSL_SOK) {
Sys_CountMcASP ++;
return;
}
myParamSetup.option = CSL_EDMA3_OPT_MAKE(CSL_EDMA3_ITCCH_DIS,
CSL_EDMA3_TCCH_DIS,
CSL_EDMA3_ITCINT_DIS,
CSL_EDMA3_TCINT_EN,
tccMcASPRxPong,
CSL_EDMA3_TCC_NORMAL,
CSL_EDMA3_FIFOWIDTH_NONE,
CSL_EDMA3_STATIC_DIS,
CSL_EDMA3_SYNC_AB,
CSL_EDMA3_ADDRMODE_INCR,
CSL_EDMA3_ADDRMODE_INCR);
myParamSetup.srcAddr = (Uint32)0x46000000;
myParamSetup.dstAddr = make_l3_target_addr((UInt32)pEdmaRxTxBuffs->edmaRxPongBuffer);

/* Only move the slots with audio data */
myParamSetup.aCntbCnt = CSL_EDMA3_CNT_MAKE(NBYTES2, NUM_SLOTS_MCASP);

myParamSetup.cCnt = SAMPLES_PER_10ms;
myParamSetup.srcDstBidx = CSL_EDMA3_BIDX_MAKE(0, (SAMPLES_PER_10ms*NBYTES2));
myParamSetup.srcDstCidx = CSL_EDMA3_CIDX_MAKE(0, NBYTES2);

myParamSetup.linkBcntrld = CSL_EDMA3_LINKBCNTRLD_MAKE ((Uint32) hParamMcASPRxLinkPing, 0);
statusMcASP = CSL_edma3ParamSetup(hParamMcASPRxLinkPong,&myParamSetup);
if (statusMcASP != CSL_SOK) {
Sys_CountMcASP ++;
return;
}
myParamSetup.option = CSL_EDMA3_OPT_MAKE(CSL_EDMA3_ITCCH_DIS,
CSL_EDMA3_TCCH_DIS,
CSL_EDMA3_ITCINT_DIS,
CSL_EDMA3_TCINT_EN,
tccMcASPTxPing,
CSL_EDMA3_TCC_NORMAL,
CSL_EDMA3_FIFOWIDTH_NONE,
CSL_EDMA3_STATIC_DIS,
CSL_EDMA3_SYNC_AB,
CSL_EDMA3_ADDRMODE_INCR,
CSL_EDMA3_ADDRMODE_INCR);
myParamSetup.srcAddr = make_l3_target_addr((Uint32)pEdmaRxTxBuffs->edmaTxPingBuffer);
myParamSetup.dstAddr = (Uint32)0x46000000;

myParamSetup.aCntbCnt = CSL_EDMA3_CNT_MAKE(NBYTES2, NUM_SLOTS_MCASP);
myParamSetup.cCnt = SAMPLES_PER_10ms;
myParamSetup.srcDstBidx = CSL_EDMA3_BIDX_MAKE((SAMPLES_PER_10ms*NBYTES2), 0);
myParamSetup.srcDstCidx = CSL_EDMA3_CIDX_MAKE(NBYTES2, 0);

myParamSetup.linkBcntrld = CSL_EDMA3_LINKBCNTRLD_MAKE ((Uint32) hParamMcASPTxLinkPong, 0);
statusMcASP = CSL_edma3ParamSetup(hParamMcASPTxBasic,&myParamSetup);
if (statusMcASP != CSL_SOK) {
Sys_CountMcASP ++;
return;
}
statusMcASP = CSL_edma3ParamSetup(hParamMcASPTxLinkPing,&myParamSetup);
if (statusMcASP != CSL_SOK) {
Sys_CountMcASP ++;
return;
}
myParamSetup.option = CSL_EDMA3_OPT_MAKE(CSL_EDMA3_ITCCH_DIS,
CSL_EDMA3_TCCH_DIS,
CSL_EDMA3_ITCINT_DIS,
CSL_EDMA3_TCINT_EN,
tccMcASPTxPong,
CSL_EDMA3_TCC_NORMAL,
CSL_EDMA3_FIFOWIDTH_NONE,
CSL_EDMA3_STATIC_DIS,
CSL_EDMA3_SYNC_AB,
CSL_EDMA3_ADDRMODE_INCR,
CSL_EDMA3_ADDRMODE_INCR);
myParamSetup.srcAddr = make_l3_target_addr((Uint32)pEdmaRxTxBuffs->edmaTxPongBuffer);
myParamSetup.dstAddr = (Uint32)0x46000000;

myParamSetup.aCntbCnt = CSL_EDMA3_CNT_MAKE(NBYTES2, NUM_SLOTS_MCASP);
myParamSetup.cCnt = SAMPLES_PER_10ms;
myParamSetup.srcDstBidx = CSL_EDMA3_BIDX_MAKE((SAMPLES_PER_10ms*NBYTES2), 0);
myParamSetup.srcDstCidx = CSL_EDMA3_CIDX_MAKE(NBYTES2, 0);

myParamSetup.linkBcntrld = CSL_EDMA3_LINKBCNTRLD_MAKE ((Uint32) hParamMcASPTxLinkPing, 0);
statusMcASP = CSL_edma3ParamSetup(hParamMcASPTxLinkPong,&myParamSetup);
if (statusMcASP != CSL_SOK) {
Sys_CountMcASP ++;
return;
}

statusMcASP = CSL_edma3HwChannelControl(hChannelMcASPRx,CSL_EDMA3_CMD_CHANNEL_ENABLE,NULL);
if (statusMcASP != CSL_SOK)
{
Sys_CountMcASP++;
return;
}
statusMcASP = CSL_edma3HwChannelControl(hChannelMcASPTx,CSL_EDMA3_CMD_CHANNEL_ENABLE,NULL);
if (statusMcASP != CSL_SOK)
{
Sys_CountMcASP++;
return;
}
#endif
return;
}