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DM8168 boot fail from SD

    Hello.

We have our own device on base of DM8168 with DDR2.  We have made all necessary changes to move to the ddr2 memory. We have collected own images of the MLO, u-boot.bin, uImage and file system, and used special ti script to write  all these on SD card. Our debug port is uart2. After powering up there was no any of messages in the console. We  connected through the debugger and verified that MLO uploaded at 0x40400000 address correctly. Moreover, we have written down the own code in the MLO sources and were convinced that he has completed its work correctly. After connecting the debugger, value of PC counter register is 0x20080. Please suggest what could be the problem and what we need to do to solve it.

   Thanks,

     Dmitry

  • Dmitry,

    You need to check whether your boot flow stuck at the ROM code stage or it can proceed further to the u-boot. See the below resources for more info:

    DM816x TRM, sections 25.12 Tracing, 25.3.2.4 Tracing Data, 25.3.2.3 RAM Exception Vectors, 25.3.1.1 ROM Exception Vectors, 25.3.1.3 Dead Loops

    http://processors.wiki.ti.com/index.php/Debug_Tips_for_DM81xx_Boot_Fail

    Regards,
    Pavel

  •   Thank you, Pavel.

    I've been checked the tracing registers (the read value is beetween " ").

    Register          Value           Comments  

    4031 D040h "0000009E" Current tracing vector, word 1
    4031 D044h "00011000" Current tracing vector, word 2
    4031 D048h "00001000" Current tracing vector, word 3
    4031 D04Ch "00000000" Current copy of the PRM_RSTST register (reset reasons)
    4031 D050h "00000000" Cold reset run tracing vector, word 1
    4031 D054h "00000000" Cold reset run tracing vector, word 2
    4031 D058h "00000009" Cold reset run tracing vector, word 3

    I looked at the table Table 25-33. Tracing Vectors, but saw only little information for me.

      Can you help me interprete that values and what i need to do next time?

      I'd like to say additionally that we use lastest EZSDK version and we are sure that UART2 port is workable, because we run the code from BSL on it.

       Dmitry

  • Dmitry,

    dmitry chernov said:
    4031 D048h "00001000" Current tracing vector, word 3

    This value is not good, you have bit [12] = 1, while on DM816x EVM SD boot, I have 0x4031_D048 = 0x80, bit [7] = 1, memory booting device MMC/SD2. Something is not right with the SD controller.

    Can you try put breakpoint into the MLO file (under CCS/JTAG) and see if you can ever reach it? See the below e2e thread for more info:

    http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/716/t/331762.aspx

    Regards,
    Pavel

  • Dmitry,

    dmitry chernov said:
    We have our own device on base of DM8168 with DDR2.  We have made all necessary changes to move to the ddr2 memory.

    Are you aligned with the below wiki page:

    http://processors.wiki.ti.com/index.php/TI81XX_PSP_UBOOT_User_Guide#U-Boot_Support_for_DDR2.2FDDR3_Boards

    Have you perform the DDR2 software leveling? On all silicon revisions (except silicon revision 1.0), DDR2 and DDR3 require software leveling to tune the device IOs to the timing characteristics of a particular board design. Hardware leveling is not supported on these devices. For more information on software leveling, see

    processors.wiki.ti.com/index.php/DM816x_C6A816x_AM389x_DDR3_Init

    dmitry chernov said:
    We have collected own images of the MLO, u-boot.bin, uImage and file system, and used special ti script to write  all these on SD card.

    Is this the ti-ezsdk_dm816x-evm_5_05_02_00/bin/mksdboot.sh script?

    dmitry chernov said:
    Our debug port is uart2

    You mean that you are using UART2 as console?

    http://processors.wiki.ti.com/index.php/TI81xx_PSP_Porting_Guide#Using_different_UART_than_the_default_EVM_configuration_as_console

    Regards,
    Pavel

  •   Hello, Pavel.

    Thank you very much for your help. We have found the error - it was error in file evm.c

    in function

    #ifdef CONFIG_TI816X_EVM_DDR2
    static void ddr_init_settings(int emif)
    {

    in strings as the below

    if(0 == get_cpu_rev())

    So it was incorrectness in identification cpu revision.

    Ok, now is the other problem: after starting uImage it stop as in the attached log file.

    Waiting for your reply. Thanks.

      Dmitry.

    1817.log_01.txt
    U-Boot 2010.06 (Sep 25 2014 - 21:02:31)
    
    DRAM:  2 GiB
    MMC:   OMAP SD/MMC: 0
    Using default environment
    
    Hit any key to stop autoboot:  0
    raise: Signal # 8 caught
    reading u-boot.bin
    
    184588 bytes read
    ## Starting application at 0x80800000 ...
    
    
    U-Boot 2010.06 (Sep 25 2014 - 21:07:43)
    
    TI8168-GP rev 2.1
    
    ARM clk: 987MHz
    DDR clk: 398MHz
    
    I2C:   ready
    DRAM:  2 GiB
    NAND:  HW ECC BCH8 Selected
    128 MiB
    MMC:   OMAP SD/MMC: 0
    raise: Signal # 8 caught
    *** Warning - bad CRC or MMC, using default environment
    
    :,;;:;:;;;;;;;;r;;:,;;:;:;;;;;;;;:,;;:;:;;;;;;;;:,;;:;:;;;;;;;;:;;;;;;;;:,;;:;:
    ;,;:::;;;;r;;;rssiSiS552X5252525259GX2X9hX9X9XX2325S55252i5:,;;:;:;;;;;;;;:,;;:
    ;:;;;;;;;rrssSsS52S22h52299GGAAMHMM#BBH#B#HMM#HMBA&&XX2255S2S5Si:,;;:;:;;;;;;;;
    ;:;;r;;rsrrriiXS5S329&A&MH#BMB#A&9XXA252GXiSXX39AAMMMBB&G22S5i2SSiiiisi:,;;:;:;
    ;;;;;r;rr2iisiih393HB#B#AA99i22irrrX3X52AGsisss2Xii2299HBMA&X2S5S5iSiisSsi:,;;:
    r:r;rrsrsihXSi2&##MHB&Ahh3AGHGA9G9h&#H##@@@##MAMMXXX9SSS29&&HGGX2i5iisiiisisi:,
    ;;rrrrsSiiiA&ABH&A9GAGhAhBAMHA9HM@@@@@@@@@@@@@@@@@@@HHhAh2S2SX9&Gh22SSiisiiisii
    r:rrssisiS2XM##&h3AGAX&3GG3Ssr5H@M#HM2; ;2X&&&MHMB###GBB#B&XXSSs529XX55iSsisisi
    r;rsrisSi2XHAhX99A3XXG&&XS;:,rH#HGhAS   @@@@3rs2XBM@@A552&&AHA2XiisSS252SSsisSs
    r;issi5S22&&3iSSX292&hXsr;;:;h@&G339&S9@@@@2@MA&9&HB##Xris29ABMAAX2ir;rsSi5iss5
    rrsSi2XhG&9GXh399&X99i;;;;;;r#H&293H9X#@@@@@@@B&9GhAH@XrrsrsiXABHB&HG2rr;rrSiSi
    ;:rsisS599&AA9XG&3A35r;:::;,;BMh&&2iX5A@@@@@@@&392X5GB2;;;r;iSX393A##A&Xi:::rsi
    ;:rss552222X553&XHMhir;;::,:,h#HhGSXhG3#@@@@#AXXS2XAHA;::;;;;ss55XShBA3239r:,;;
    r;ii2S5SSi2i53hirsh2srr::,,,,;MMXX359&Ah3h&Si59SX99A#i:,::::;;sri2,.2r;:SGAr;,:
    ;:;rrrrssiriXGSi::shs;;;,,,:,,rBBA9h5s5h5iS5isi2SAHB5:,,,:::;rrs5&SrisSX5Srrr:,
    ;,r;;;;rsriSSrrrr;;5Xrr;;,:,,.,;9AA2SsisS5323XXXG9&i:.,,::;;r;;;srrrrrr;;:;::::
    :,;r;r;rrissrrr;:;::;s;;;;,:,,..,r293h222hXXAAGGGX;:,,,:,:,::;:;::,:,,,,...,,,,
    ;,;;;;rrrrrrrrirr;,.,,:::::::,,,,.,;SX&ABAB2hhXir:,,.,,.,,:,,,,..,,,..,..,,,..:
    :.:;:;;;:;;;;r;rrs;:.. ,,:::::,:,:,,.::rrsrr;;,,.......,..,....,,,,,,,...,.,,:,
    :.:::,::::::;;r;rrr;:.......,.,.,,:::,,...............,,::.,,,,:,::,,:,:,,,:,;:
    ,.::,:,,,,,;;;;;;;;r;;::,..............................;;;:;::::,:::::::,:,:,,,
    : ,,:,,,,,,,,,,,,,:;rrr;;:;,,,,,,,::,.,.:.,.,;s,:;;;;:;:;;;;;::::,:::,:::,:,:,:
    ,.,,,,,,,...,,.,,....................................:,............:,,,:,:,,,,,
    
    Net:   <ethaddr> not set. Reading from E-fuse
    Detected MACID:84:7e:40:f3:55:b8
    No ETH PHY detected!!!
    DaVinci EMAC
    Hit any key to stop autoboot:  0
    raise: Signal # 8 caught
    raise: Signal # 8 caught
    reading boot.scr
    
    354 bytes read
    Running bootscript from MMC/SD to set the ENV...
    ## Executing script at 80900000
    reading ti_logo.bmp
    
    151674 bytes read
    Unknown command 'bmp' - try 'help'
    reading uImage
    
    2566060 bytes read
    ## Booting kernel from Legacy Image at 80009000 ...
       Image Name:   Linux-2.6.37
       Image Type:   ARM Linux Kernel Image (uncompressed)
       Data Size:    2565996 Bytes = 2.4 MiB
       Load Address: 80008000
       Entry Point:  80008000
       Verifying Checksum ... OK
       Loading Kernel Image ... OK
    OK
    
    Starting kernel ...
    
    Uncompressing Linux... done, booting the kernel.
    Linux version 2.6.37 (root@alexeev-desktop) (gcc version 4.3.3 (Sourcery G++ Lite 2009q1-203) ) #1 Mon Oct 6 19:54:08 MSD 2014
    CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c53c7f
    CPU: VIPT nonaliasing data cache, VIPT aliasing instruction cache
    Machine: ti8168evm
    reserved size = 52428800 at 0x0
    FB: Reserving 52428800 bytes SDRAM for VRAM
    Memory policy: ECC disabled, Data cache writeback
    OMAP chip is TI8168 2.0
    Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 160648
    Kernel command line: console=ttyO2,115200n8 rootwait root=/dev/mmcblk0p2 rw mem=364M@0x80000000 mem=320M@0x9FC00000 vmalloc=500M  notifyk.vpssm3_sva=0xBF900000 ip=off noinitrd
    PID hash table entries: 2048 (order: 1, 8192 bytes)
    Dentry cache hash table entries: 65536 (order: 6, 262144 bytes)
    Inode-cache hash table entries: 32768 (order: 5, 131072 bytes)
    Memory: 364MB 270MB = 634MB total
    Memory: 637808k/637808k available, 62608k reserved, 276480K highmem
    Virtual kernel memory layout:
        vector  : 0xffff0000 - 0xffff1000   (   4 kB)
        fixmap  : 0xfff00000 - 0xfffe0000   ( 896 kB)
        DMA     : 0xffc00000 - 0xffe00000   (   2 MB)
        vmalloc : 0xd7000000 - 0xf8000000   ( 528 MB)
        lowmem  : 0xc0000000 - 0xd6c00000   ( 364 MB)
        pkmap   : 0xbfe00000 - 0xc0000000   (   2 MB)
        modules : 0xbf000000 - 0xbfe00000   (  14 MB)
          .init : 0xc0008000 - 0xc003c000   ( 208 kB)
          .text : 0xc003c000 - 0xc04da000   (4728 kB)
          .data : 0xc04da000 - 0xc0522f00   ( 292 kB)
    SLUB: Genslabs=11, HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
    NR_IRQS:407
    IRQ: Found an INTC at 0xfa200000 (revision 5.0) with 128 interrupts
    Total of 128 interrupts on 1 active controller
    GPMC revision 6.0
    Trying to install interrupt handler for IRQ400
    Trying to install interrupt handler for IRQ401
    Trying to install interrupt handler for IRQ402
    Trying to install interrupt handler for IRQ403
    Trying to install interrupt handler for IRQ404
    Trying to install interrupt handler for IRQ405
    Trying to install interrupt handler for IRQ406
    Trying to install type control for IRQ407
    Trying to set irq flags for IRQ407
    OMAP clockevent source: GPTIMER1 at 27000000 Hz
    Console: colour dummy device 80x30
    Calibrating delay loop... 986.31 BogoMIPS (lpj=4931584)
    pid_max: default: 32768 minimum: 301
    Security Framework initialized
    Mount-cache hash table entries: 512
    CPU: Testing write buffer coherency: ok
    devtmpfs: initialized
    omap_voltage_early_init: voltage driver support not added
    regulator: core version 0.5
    regulator: dummy:
    NET: Registered protocol family 16
    omap_voltage_domain_lookup: Voltage driver init not yet happened.Faulting!
    omap_voltage_add_dev: VDD specified does not exist!
    OMAP GPIO hardware version 0.1
    OMAP GPIO hardware version 0.1
    omap_mux_init: Add partition: #1: core, flags: 0
    _omap_mux_get_by_name: Could not find signal i2c2_scl.i2c2_scl
    _omap_mux_get_by_name: Could not find signal i2c2_sda.i2c2_sda
    NOR: Can't request GPMC CS
    registered ti816x_gpio_vr device
    registered ti816x_sr device
    pm_dbg_init: only OMAP3 supported
    registered ti81xx_vpss device
    registered ti81xx_vidout device
    registered ti81xx on-chip HDMI device
    registered ti81xx_fb device
    registered ti81xx_vin device
    ti81xx_pcie: Invoking PCI BIOS...
    ti81xx_pcie: Setting up Host Controller...
    ti81xx_pcie: Register base mapped @0xd7020000
    ti81xx_pcie: Starting PCI scan...
    PCI: bus0: Fast back to back transfers enabled
    bio: create slab <bio-0> at 0
    regulator: VFB: 800 <--> 1025 mV at 860 mV
    vgaarb: loaded
    SCSI subsystem initialized
    usbcore: registered new interface driver usbfs
    usbcore: registered new interface driver hub
    usbcore: registered new device driver usb
    USBSS revision 4ea20809
    registerd cppi-dma Intr @ IRQ 17
    Cppi41 Init Done
    omap_i2c omap_i2c.1: bus 1 rev4.0 at 100 kHz
    omap_i2c omap_i2c.2: bus 2 rev4.0 at 100 kHz
    Advanced Linux Sound Architecture Driver Version 1.0.23.
    Switching to clocksource gp timer
    musb-hdrc: version 6.0, host, debug=0
    musb-hdrc musb-hdrc.0: dma type: dma-cppi41
    MUSB controller-0 revision 4ea20800
    musb-hdrc musb-hdrc.0: MUSB HDRC host driver
    musb-hdrc musb-hdrc.0: new USB bus registered, assigned bus number 1
    usb usb1: New USB device found, idVendor=1d6b, idProduct=0002
    usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1
    usb usb1: Product: MUSB HDRC host driver
    usb usb1: Manufacturer: Linux 2.6.37 musb-hcd
    usb usb1: SerialNumber: musb-hdrc.0
    hub 1-0:1.0: USB hub found
    hub 1-0:1.0: 1 port detected
    musb-hdrc musb-hdrc.0: USB Host mode controller at d701e000 using DMA, IRQ 18
    musb-hdrc musb-hdrc.1: dma type: dma-cppi41
    MUSB controller-1 revision 4ea20800
    musb-hdrc musb-hdrc.1: MUSB HDRC host driver
    musb-hdrc musb-hdrc.1: new USB bus registered, assigned bus number 2
    usb usb2: New USB device found, idVendor=1d6b, idProduct=0002
    usb usb2: New USB device strings: Mfr=3, Product=2, SerialNumber=1
    usb usb2: Product: MUSB HDRC host driver
    usb usb2: Manufacturer: Linux 2.6.37 musb-hcd
    usb usb2: SerialNumber: musb-hdrc.1
    hub 2-0:1.0: USB hub found
    hub 2-0:1.0: 1 port detected
    musb-hdrc musb-hdrc.1: USB Host mode controller at d7026800 using DMA, IRQ 19
    NET: Registered protocol family 2
    IP route cache hash table entries: 16384 (order: 4, 65536 bytes)
    TCP established hash table entries: 65536 (order: 7, 524288 bytes)
    TCP bind hash table entries: 65536 (order: 6, 262144 bytes)
    TCP: Hash tables configured (established 65536 bind 65536)
    TCP reno registered
    UDP hash table entries: 256 (order: 0, 4096 bytes)
    UDP-Lite hash table entries: 256 (order: 0, 4096 bytes)
    NET: Registered protocol family 1
    RPC: Registered udp transport module.
    RPC: Registered tcp transport module.
    RPC: Registered tcp NFSv4.1 backchannel transport module.
    NetWinder Floating Point Emulator V0.97 (double precision)
    PMU: registered new PMU device of type 0
    omap-iommu omap-iommu.0: ducati registered
    omap-iommu omap-iommu.1: sys registered
    highmem bounce pool size: 64 pages
    JFFS2 version 2.2. (NAND) � 2001-2006 Red Hat, Inc.
    msgmni has been set to 705
    io scheduler noop registered
    io scheduler deadline registered
    io scheduler cfq registered (default)
    Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
    omap_uart.0: ttyO0 at MMIO 0x48020000 (irq = 72) is a OMAP UART0
    omap_uart.1: ttyO1 at MMIO 0x48022000 (irq = 73) is a OMAP UART1
    omap_uart.2: ttyO2 at MMIO 0x48024000 (irq = 74) is a OMAP UART2
    console [ttyO2] enabled
    brd: module loaded
    loop: module loaded
    ahci ahci.0: forcing PORTS_IMPL to 0x3
    ahci ahci.0: AHCI 0001.0100 32 slots 2 ports 3 Gbps 0x3 impl platform mode
    ahci ahci.0: flags: ncq sntf pm led clo only pmp pio slum part ccc
    scsi0 : ahci_platform
    scsi1 : ahci_platform
    ata1: SATA max UDMA/133 mmio [mem 0x4a140000-0x4a150fff] port 0x100 irq 16
    ata2: SATA max UDMA/133 mmio [mem 0x4a140000-0x4a150fff] port 0x180 irq 16
    m25p80 spi1.0: found m25p05-nonjedec, expected m25p80
    m25p80 spi1.0: m25p05-nonjedec (64 Kbytes)
    Creating 4 MTD partitions on "spi_flash":
    0x000000000000-0x000000040000 : "U-Boot"
    mtd: partition "U-Boot" extends beyond the end of device "spi_flash" -- size truncated to 0x10000
    0x000000010000-0x000000012000 : "U-Boot Env"
    mtd: partition "U-Boot Env" is out of reach -- disabled
    0x000000000000-0x000000280000 : "Kernel"
    mtd: partition "Kernel" extends beyond the end of device "spi_flash" -- size truncated to 0x10000
    0x000000010000-0x000000010000 : "File System"
    mtd: partition "File System" is out of reach -- disabled
    omap2-nand driver initializing
    NAND device: Manufacturer ID: 0xec, Chip ID: 0xf1 (Samsung )
    Creating 5 MTD partitions on "omap2-nand.0":
    0x000000000000-0x000000260000 : "U-Boot"
    0x000000260000-0x000000280000 : "U-Boot Env"
    0x000000280000-0x0000006c0000 : "Kernel"
    0x0000006c0000-0x00000cee0000 : "File System"
    mtd: partition "File System" extends beyond the end of device "omap2-nand.0" -- size truncated to 0x7940000
    0x000008000000-0x000008000000 : "Reserved"
    mtd: partition "Reserved" is out of reach -- disabled
    davinci_mdio davinci_mdio.0: davinci mdio revision 1.6
    davinci_mdio davinci_mdio.0: no live phy, scanning all
    davinci_mdio: probe of davinci_mdio.0 failed with error -5
    usbcore: registered new interface driver cdc_ether
    usbcore: registered new interface driver dm9601
    Initializing USB Mass Storage driver...
    usbcore: registered new interface driver usb-storage
    USB Mass Storage support registered.
    mice: PS/2 mouse device common for all mice
    omap_rtc omap_rtc: rtc core: registered omap_rtc as rtc0
    i2c /dev entries driver
    Linux video capture interface: v2.00
    usbcore: registered new interface driver uvcvideo
    USB Video Class driver (v1.0.0)
    OMAP Watchdog Timer Rev 0x00: initial timeout 60 sec
    usbcore: registered new interface driver usbhid
    usbhid: USB HID core driver
    

  • Dmitry,

    How much DDR2 you have on your DM816x custom board (256MB, 512MB, 1GB, 2GB)?

    Regards,
    Pavel

  •   Hello, Pavel.

     It has 512MBytes on two EMIFs (Total is 512MBytes).

       Dmitry

  • Dmitry,

    dmitry chernov said:
     It has 512MBytes on two EMIFs (Total is 512MBytes).

    Do you mean you have 256MBytes on EMIF0 and 256MBytes on EMIF1, thus 512MBytes in total?

    Best regards,
    Pavel

  •   Yes, you are right. It's really 256MBytes on EMIF0 and 256MBytes on EMIF1, thus 512MBytes in total

     Does you mean that we are encountered with problem relevant with not corrected size of memory in uImage configuration?

    I'm seeing the string from log file:

    "Memory: 364MB 270MB = 634MB total"

    At which file we need to do changes to correct size?

       Dmitry.

  • Dmitry,

    Make sure you have change the default DDR3 config to DDR2, according to the guidelines in:

    ti-ezsdk_dm816x-evm_5_05_02_00/docs/DM816x_EZ_Software_Developers_Guide.pdf, 6.3 How to setup the EZ SDK for DDR2 EVMs

    http://processors.wiki.ti.com/index.php/TI81XX_PSP_UBOOT_User_Guide#Modifying_U-Boot_for_DDR2

    The default EZSDK memory map is for DDR at 1GByte, for 512MByte EZSDK memory map, see the below wiki:

    http://processors.wiki.ti.com/index.php/EZSDK_Memory_Map#Changing_Memory_Map_For_512MB_DM816x_Board

    You can also check if your DDR is fine with the mtest check:

    http://processors.wiki.ti.com/index.php/DM816x_C6A816x_AM389x_DDR3_Init_Wordwise_SWleveling#Run_mtest

    Regards,
    Pavel

  •   Pavel,

    We have done all of these instructions a long time ago. But your last message open our eyes of mismatching of memory size. We have done changes in files and now all became work correctly. So thank you vary much fo help.

    We have attached new log file - may be you can advise us what we can improve in uImage or route file system settings.

    4846.log_03.txt
    
    U-Boot 2010.06 (Oct 07 2014 - 21:01:02)
    
    DRAM:  2 GiB
    MMC:   OMAP SD/MMC: 0
    Using default environment
    
    Hit any key to stop autoboot:  0
    raise: Signal # 8 caught
    reading u-boot.bin
    
    184588 bytes read
    ## Starting application at 0x80800000 ...
    
    
    U-Boot 2010.06 (Oct 07 2014 - 21:11:38)
    
    TI8168-GP rev 2.1
    
    ARM clk: 987MHz
    DDR clk: 398MHz
    
    I2C:   ready
    DRAM:  2 GiB
    NAND:  HW ECC BCH8 Selected
    128 MiB
    MMC:   OMAP SD/MMC: 0
    raise: Signal # 8 caught
    *** Warning - bad CRC or MMC, using default environment
    
    :,;;:;:;;;;;;;;r;;:,;;:;:;;;;;;;;:,;;:;:;;;;;;;;:,;;:;:;;;;;;;;:;;;;;;;;:,;;:;:
    ;,;:::;;;;r;;;rssiSiS552X5252525259GX2X9hX9X9XX2325S55252i5:,;;:;:;;;;;;;;:,;;:
    ;:;;;;;;;rrssSsS52S22h52299GGAAMHMM#BBH#B#HMM#HMBA&&XX2255S2S5Si:,;;:;:;;;;;;;;
    ;:;;r;;rsrrriiXS5S329&A&MH#BMB#A&9XXA252GXiSXX39AAMMMBB&G22S5i2SSiiiisi:,;;:;:;
    ;;;;;r;rr2iisiih393HB#B#AA99i22irrrX3X52AGsisss2Xii2299HBMA&X2S5S5iSiisSsi:,;;:
    r:r;rrsrsihXSi2&##MHB&Ahh3AGHGA9G9h&#H##@@@##MAMMXXX9SSS29&&HGGX2i5iisiiisisi:,
    ;;rrrrsSiiiA&ABH&A9GAGhAhBAMHA9HM@@@@@@@@@@@@@@@@@@@HHhAh2S2SX9&Gh22SSiisiiisii
    r:rrssisiS2XM##&h3AGAX&3GG3Ssr5H@M#HM2; ;2X&&&MHMB###GBB#B&XXSSs529XX55iSsisisi
    r;rsrisSi2XHAhX99A3XXG&&XS;:,rH#HGhAS   @@@@3rs2XBM@@A552&&AHA2XiisSS252SSsisSs
    r;issi5S22&&3iSSX292&hXsr;;:;h@&G339&S9@@@@2@MA&9&HB##Xris29ABMAAX2ir;rsSi5iss5
    rrsSi2XhG&9GXh399&X99i;;;;;;r#H&293H9X#@@@@@@@B&9GhAH@XrrsrsiXABHB&HG2rr;rrSiSi
    ;:rsisS599&AA9XG&3A35r;:::;,;BMh&&2iX5A@@@@@@@&392X5GB2;;;r;iSX393A##A&Xi:::rsi
    ;:rss552222X553&XHMhir;;::,:,h#HhGSXhG3#@@@@#AXXS2XAHA;::;;;;ss55XShBA3239r:,;;
    r;ii2S5SSi2i53hirsh2srr::,,,,;MMXX359&Ah3h&Si59SX99A#i:,::::;;sri2,.2r;:SGAr;,:
    ;:;rrrrssiriXGSi::shs;;;,,,:,,rBBA9h5s5h5iS5isi2SAHB5:,,,:::;rrs5&SrisSX5Srrr:,
    ;,r;;;;rsriSSrrrr;;5Xrr;;,:,,.,;9AA2SsisS5323XXXG9&i:.,,::;;r;;;srrrrrr;;:;::::
    :,;r;r;rrissrrr;:;::;s;;;;,:,,..,r293h222hXXAAGGGX;:,,,:,:,::;:;::,:,,,,...,,,,
    ;,;;;;rrrrrrrrirr;,.,,:::::::,,,,.,;SX&ABAB2hhXir:,,.,,.,,:,,,,..,,,..,..,,,..:
    :.:;:;;;:;;;;r;rrs;:.. ,,:::::,:,:,,.::rrsrr;;,,.......,..,....,,,,,,,...,.,,:,
    :.:::,::::::;;r;rrr;:.......,.,.,,:::,,...............,,::.,,,,:,::,,:,:,,,:,;:
    ,.::,:,,,,,;;;;;;;;r;;::,..............................;;;:;::::,:::::::,:,:,,,
    : ,,:,,,,,,,,,,,,,:;rrr;;:;,,,,,,,::,.,.:.,.,;s,:;;;;:;:;;;;;::::,:::,:::,:,:,:
    ,.,,,,,,,...,,.,,....................................:,............:,,,:,:,,,,,
    
    Net:   <ethaddr> not set. Reading from E-fuse
    Detected MACID:84:7e:40:f3:55:b8
    No ETH PHY detected!!!
    DaVinci EMAC
    Hit any key to stop autoboot:  0
    raise: Signal # 8 caught
    raise: Signal # 8 caught
    reading boot.scr
    
    354 bytes read
    Running bootscript from MMC/SD to set the ENV...
    ## Executing script at 80900000
    reading ti_logo.bmp
    
    151674 bytes read
    Unknown command 'bmp' - try 'help'
    reading uImage
    
    2566060 bytes read
    ## Booting kernel from Legacy Image at 80009000 ...
       Image Name:   Linux-2.6.37
       Image Type:   ARM Linux Kernel Image (uncompressed)
       Data Size:    2565996 Bytes = 2.4 MiB
       Load Address: 80008000
       Entry Point:  80008000
       Verifying Checksum ... OK
       Loading Kernel Image ... OK
    OK
    
    Starting kernel ...
    
    Uncompressing Linux... done, booting the kernel.
    Linux version 2.6.37 (root@alexeev-desktop) (gcc version 4.3.3 (Sourcery G++ Lite 2009q1-203) ) #1 Mon Oct 6 19:54:08 MSD 2014
    CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c53c7f
    CPU: VIPT nonaliasing data cache, VIPT aliasing instruction cache
    Machine: ti8168evm
    reserved size = 52428800 at 0x0
    FB: Reserving 52428800 bytes SDRAM for VRAM
    Memory policy: ECC disabled, Data cache writeback
    OMAP chip is TI8168 2.0
    Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 160648
    Kernel command line: console=ttyO2,115200n8 rootwait root=/dev/mmcblk0p2 rw mem=364M@0x80000000 mem=320M@0x9FC00000 vmalloc=500M  notifyk.vpssm3_sva=0xBF900000 ip=off noinitrd
    PID hash table entries: 2048 (order: 1, 8192 bytes)
    Dentry cache hash table entries: 65536 (order: 6, 262144 bytes)
    Inode-cache hash table entries: 32768 (order: 5, 131072 bytes)
    Memory: 364MB 270MB = 634MB total
    Memory: 637808k/637808k available, 62608k reserved, 276480K highmem
    Virtual kernel memory layout:
        vector  : 0xffff0000 - 0xffff1000   (   4 kB)
        fixmap  : 0xfff00000 - 0xfffe0000   ( 896 kB)
        DMA     : 0xffc00000 - 0xffe00000   (   2 MB)
        vmalloc : 0xd7000000 - 0xf8000000   ( 528 MB)
        lowmem  : 0xc0000000 - 0xd6c00000   ( 364 MB)
        pkmap   : 0xbfe00000 - 0xc0000000   (   2 MB)
        modules : 0xbf000000 - 0xbfe00000   (  14 MB)
          .init : 0xc0008000 - 0xc003c000   ( 208 kB)
          .text : 0xc003c000 - 0xc04da000   (4728 kB)
          .data : 0xc04da000 - 0xc0522f00   ( 292 kB)
    SLUB: Genslabs=11, HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
    NR_IRQS:407
    IRQ: Found an INTC at 0xfa200000 (revision 5.0) with 128 interrupts
    Total of 128 interrupts on 1 active controller
    GPMC revision 6.0
    Trying to install interrupt handler for IRQ400
    Trying to install interrupt handler for IRQ401
    Trying to install interrupt handler for IRQ402
    Trying to install interrupt handler for IRQ403
    Trying to install interrupt handler for IRQ404
    Trying to install interrupt handler for IRQ405
    Trying to install interrupt handler for IRQ406
    Trying to install type control for IRQ407
    Trying to set irq flags for IRQ407
    OMAP clockevent source: GPTIMER1 at 27000000 Hz
    Console: colour dummy device 80x30
    Calibrating delay loop... 986.31 BogoMIPS (lpj=4931584)
    pid_max: default: 32768 minimum: 301
    Security Framework initialized
    Mount-cache hash table entries: 512
    CPU: Testing write buffer coherency: ok
    devtmpfs: initialized
    omap_voltage_early_init: voltage driver support not added
    regulator: core version 0.5
    regulator: dummy:
    NET: Registered protocol family 16
    omap_voltage_domain_lookup: Voltage driver init not yet happened.Faulting!
    omap_voltage_add_dev: VDD specified does not exist!
    OMAP GPIO hardware version 0.1
    OMAP GPIO hardware version 0.1
    omap_mux_init: Add partition: #1: core, flags: 0
    _omap_mux_get_by_name: Could not find signal i2c2_scl.i2c2_scl
    _omap_mux_get_by_name: Could not find signal i2c2_sda.i2c2_sda
    NOR: Can't request GPMC CS
    registered ti816x_gpio_vr device
    registered ti816x_sr device
    pm_dbg_init: only OMAP3 supported
    registered ti81xx_vpss device
    registered ti81xx_vidout device
    registered ti81xx on-chip HDMI device
    registered ti81xx_fb device
    registered ti81xx_vin device
    ti81xx_pcie: Invoking PCI BIOS...
    ti81xx_pcie: Setting up Host Controller...
    ti81xx_pcie: Register base mapped @0xd7020000
    ti81xx_pcie: Starting PCI scan...
    PCI: bus0: Fast back to back transfers enabled
    bio: create slab <bio-0> at 0
    regulator: VFB: 800 <--> 1025 mV at 860 mV
    vgaarb: loaded
    SCSI subsystem initialized
    usbcore: registered new interface driver usbfs
    usbcore: registered new interface driver hub
    usbcore: registered new device driver usb
    USBSS revision 4ea20809
    registerd cppi-dma Intr @ IRQ 17
    Cppi41 Init Done
    omap_i2c omap_i2c.1: bus 1 rev4.0 at 100 kHz
    omap_i2c omap_i2c.2: bus 2 rev4.0 at 100 kHz
    Advanced Linux Sound Architecture Driver Version 1.0.23.
    Switching to clocksource gp timer
    musb-hdrc: version 6.0, host, debug=0
    musb-hdrc musb-hdrc.0: dma type: dma-cppi41
    MUSB controller-0 revision 4ea20800
    musb-hdrc musb-hdrc.0: MUSB HDRC host driver
    musb-hdrc musb-hdrc.0: new USB bus registered, assigned bus number 1
    usb usb1: New USB device found, idVendor=1d6b, idProduct=0002
    usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1
    usb usb1: Product: MUSB HDRC host driver
    usb usb1: Manufacturer: Linux 2.6.37 musb-hcd
    usb usb1: SerialNumber: musb-hdrc.0
    hub 1-0:1.0: USB hub found
    hub 1-0:1.0: 1 port detected
    musb-hdrc musb-hdrc.0: USB Host mode controller at d701e000 using DMA, IRQ 18
    musb-hdrc musb-hdrc.1: dma type: dma-cppi41
    MUSB controller-1 revision 4ea20800
    musb-hdrc musb-hdrc.1: MUSB HDRC host driver
    musb-hdrc musb-hdrc.1: new USB bus registered, assigned bus number 2
    usb usb2: New USB device found, idVendor=1d6b, idProduct=0002
    usb usb2: New USB device strings: Mfr=3, Product=2, SerialNumber=1
    usb usb2: Product: MUSB HDRC host driver
    usb usb2: Manufacturer: Linux 2.6.37 musb-hcd
    usb usb2: SerialNumber: musb-hdrc.1
    hub 2-0:1.0: USB hub found
    hub 2-0:1.0: 1 port detected
    musb-hdrc musb-hdrc.1: USB Host mode controller at d7026800 using DMA, IRQ 19
    NET: Registered protocol family 2
    IP route cache hash table entries: 16384 (order: 4, 65536 bytes)
    TCP established hash table entries: 65536 (order: 7, 524288 bytes)
    TCP bind hash table entries: 65536 (order: 6, 262144 bytes)
    TCP: Hash tables configured (established 65536 bind 65536)
    TCP reno registered
    UDP hash table entries: 256 (order: 0, 4096 bytes)
    UDP-Lite hash table entries: 256 (order: 0, 4096 bytes)
    NET: Registered protocol family 1
    RPC: Registered udp transport module.
    RPC: Registered tcp transport module.
    RPC: Registered tcp NFSv4.1 backchannel transport module.
    NetWinder Floating Point Emulator V0.97 (double precision)
    PMU: registered new PMU device of type 0
    omap-iommu omap-iommu.0: ducati registered
    omap-iommu omap-iommu.1: sys registered
    highmem bounce pool size: 64 pages
    JFFS2 version 2.2. (NAND) � 2001-2006 Red Hat, Inc.
    msgmni has been set to 705
    io scheduler noop registered
    io scheduler deadline registered
    io scheduler cfq registered (default)
    Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
    omap_uart.0: ttyO0 at MMIO 0x48020000 (irq = 72) is a OMAP UART0
    omap_uart.1: ttyO1 at MMIO 0x48022000 (irq = 73) is a OMAP UART1
    omap_uart.2: ttyO2 at MMIO 0x48024000 (irq = 74) is a OMAP UART2
    console [ttyO2] enabled
    brd: module loaded
    loop: module loaded
    ahci ahci.0: forcing PORTS_IMPL to 0x3
    ahci ahci.0: AHCI 0001.0100 32 slots 2 ports 3 Gbps 0x3 impl platform mode
    ahci ahci.0: flags: ncq sntf pm led clo only pmp pio slum part ccc
    scsi0 : ahci_platform
    scsi1 : ahci_platform
    ata1: SATA max UDMA/133 mmio [mem 0x4a140000-0x4a150fff] port 0x100 irq 16
    ata2: SATA max UDMA/133 mmio [mem 0x4a140000-0x4a150fff] port 0x180 irq 16
    m25p80 spi1.0: found m25p05-nonjedec, expected m25p80
    m25p80 spi1.0: m25p05-nonjedec (64 Kbytes)
    Creating 4 MTD partitions on "spi_flash":
    0x000000000000-0x000000040000 : "U-Boot"
    mtd: partition "U-Boot" extends beyond the end of device "spi_flash" -- size truncated to 0x10000
    0x000000010000-0x000000012000 : "U-Boot Env"
    mtd: partition "U-Boot Env" is out of reach -- disabled
    0x000000000000-0x000000280000 : "Kernel"
    mtd: partition "Kernel" extends beyond the end of device "spi_flash" -- size truncated to 0x10000
    0x000000010000-0x000000010000 : "File System"
    mtd: partition "File System" is out of reach -- disabled
    omap2-nand driver initializing
    NAND device: Manufacturer ID: 0xec, Chip ID: 0xf1 (Samsung )
    Creating 5 MTD partitions on "omap2-nand.0":
    0x000000000000-0x000000260000 : "U-Boot"
    0x000000260000-0x000000280000 : "U-Boot Env"
    0x000000280000-0x0000006c0000 : "Kernel"
    0x0000006c0000-0x00000cee0000 : "File System"
    mtd: partition "File System" extends beyond the end of device "omap2-nand.0" -- size truncated to 0x7940000
    0x000008000000-0x000008000000 : "Reserved"
    mtd: partition "Reserved" is out of reach -- disabled
    davinci_mdio davinci_mdio.0: davinci mdio revision 1.6
    davinci_mdio davinci_mdio.0: no live phy, scanning all
    davinci_mdio: probe of davinci_mdio.0 failed with error -5
    usbcore: registered new interface driver cdc_ether
    usbcore: registered new interface driver dm9601
    Initializing USB Mass Storage driver...
    usbcore: registered new interface driver usb-storage
    USB Mass Storage support registered.
    mice: PS/2 mouse device common for all mice
    omap_rtc omap_rtc: rtc core: registered omap_rtc as rtc0
    i2c /dev entries driver
    Linux video capture interface: v2.00
    usbcore: registered new interface driver uvcvideo
    USB Video Class driver (v1.0.0)
    OMAP Watchdog Timer Rev 0x00: initial timeout 60 sec
    usbcore: registered new interface driver usbhid
    usbhid: USB HID core driver
    notify_init : notify drivercreated  for  remote proc id 2 at physical Address 0xbf900000
    usbcore: registered new interface driver snd-usb-audio
    asoc: tlv320aic3x-hifi <-> davinci-mcasp.2 mapping ok
    ALSA device list:
      #0: TI81XX EVM
    TCP cubic registered
    NET: Registered protocol family 17
    VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
    omap_voltage_late_init: Voltage driver support not added
    Power Management for TI81XX.
    smartreflex smartreflex: Driver initialized
    omap_rtc omap_rtc: setting system clock to 2000-01-01 00:00:00 UTC (946684800)
    ata1: SATA link down (SStatus 0 SControl 300)
    ata2: SATA link down (SStatus 0 SControl 300)
    Waiting for root device /dev/mmcblk0p2...
    mmc0: new high speed SDHC card at address b368
    mmcblk0: mmc0:b368 USD   3.75 GiB
     mmcblk0: p1 p2
    EXT3-fs: barriers not enabled
    kjournald starting.  Commit interval 5 seconds
    EXT3-fs (mmcblk0p2): using internal journal
    EXT3-fs (mmcblk0p2): recovery complete
    EXT3-fs (mmcblk0p2): mounted filesystem with writeback data mode
    VFS: Mounted root (ext3 filesystem) on device 179:2.
    devtmpfs: mounted
    Freeing init memory: 208K
    INIT: version 2.86 booting
    Please wait: booting...
    Error opening /dev/fb0: No such file or directory
    Starting udev
    udevd (74): /proc/74/oom_adj is deprecated, please use /proc/74/oom_score_adj instead.
    Remounting root file system...
    Caching udev devnodes
    NET: Registered protocol family 10
    ALSA: Restoring mixer settings...
    No state is present for card EVM
    Found hardware: "" "" "" "" ""
    Hardware is initialized using a generic method
    Configuring network interfaces... No state is present for card EVM
    PHY 0:07 not found
    net eth0: could not connect to phy 0:07
    ADDRCONF(NETDEV_UP): eth0: link is not ready
    udhcpc (v1.13.2) started
    Sending discover...
    Sending discover...
    Sending discover...
    No lease, forking to background
    done.
    Setting up IP spoofing protection: rp_filter.
    Wed Dec 26 15:58:00 UTC 2012
    INIT: Entering runlevel: 5
    Loading HDVICP2 Firmware
    DM816X prcm_config_app version: 2.0.0.1
    Doing PRCM settings...
            PRCM for IVHD0 is in Progress, Please wait.....
                            BW Phy Addr : 0x48180600 Data : 0x00000002
                            AW Phy Addr : 0x48180600 Data : 0x00000002
                            Phy Addr : 0x48180c04 Data : 0x00000037
                            BW Phy Addr : 0x48180620 Data : 0x00070000
                            AW Phy Addr : 0x48180620 Data : 0x00070002
                            BW Phy Addr : 0x48180624 Data : 0x00030000
                            AW Phy Addr : 0x48180624 Data : 0x00010002
                            Phy Addr : 0x48180600 Data : 0x00000102
                            BW Phy Addr : 0x48180c10 Data : 0x00000007
                            AW Phy Addr : 0x48180c10 Data : 0x00000003
                            Phy Addr : 0x48180c14 Data : 0x00000004
                            BW Phy Addr : 0x58088000 Data : 0x34d44bdd
                            AW Phy Addr : 0x58088000 Data : 0xeafffffe
                            BW Phy Addr : 0x58098000 Data : 0x1fab7e8a
                            AW Phy Addr : 0x58098000 Data : 0xeafffffe
                            BW Phy Addr : 0x48180c10 Data : 0x00000003
                            AW Phy Addr : 0x48180c10 Data : 0x00000000
                            Phy Addr : 0x48180c14 Data : 0x00000007
            PRCM for IVHD0 is Done Successfully
            PRCM for IVHD1 is in Progress, Please wait.....
                            BW Phy Addr : 0x48180700 Data : 0x00000002
                            AW Phy Addr : 0x48180700 Data : 0x00000002
                            Phy Addr : 0x48180d04 Data : 0x00000037
                            BW Phy Addr : 0x48180720 Data : 0x00070000
                            AW Phy Addr : 0x48180720 Data : 0x00050002
                            BW Phy Addr : 0x48180724 Data : 0x00030000
                            AW Phy Addr : 0x48180724 Data : 0x00010002
                            Phy Addr : 0x48180700 Data : 0x00000102
                            BW Phy Addr : 0x48180d10 Data : 0x00000007
                            AW Phy Addr : 0x48180d10 Data : 0x00000003
                            Phy Addr : 0x48180d14 Data : 0x00000004
                            BW Phy Addr : 0x5a088000 Data : 0x75074c4e
                            AW Phy Addr : 0x5a088000 Data : 0xeafffffe
                            BW Phy Addr : 0x5a098000 Data : 0xfb6e26f9
                            AW Phy Addr : 0x5a098000 Data : 0xeafffffe
                            BW Phy Addr : 0x48180d10 Data : 0x00000003
                            AW Phy Addr : 0x48180d10 Data : 0x00000000
                            Phy Addr : 0x48180d14 Data : 0x00000007
            PRCM for IVHD1 is Done Successfully
            PRCM for IVHD2 is in Progress, Please wait.....
                            BW Phy Addr : 0x48180800 Data : 0x00000002
                            AW Phy Addr : 0x48180800 Data : 0x00000002
                            Phy Addr : 0x48180e04 Data : 0x00000037
                            BW Phy Addr : 0x48180820 Data : 0x00070000
                            AW Phy Addr : 0x48180820 Data : 0x00050002
                            BW Phy Addr : 0x48180824 Data : 0x00030000
                            AW Phy Addr : 0x48180824 Data : 0x00010002
                            Phy Addr : 0x48180800 Data : 0x00000102
                            BW Phy Addr : 0x48180e10 Data : 0x00000007
                            AW Phy Addr : 0x48180e10 Data : 0x00000003
                            Phy Addr : 0x48180e14 Data : 0x00000004
                            BW Phy Addr : 0x53088000 Data : 0xef27b9e2
                            AW Phy Addr : 0x53088000 Data : 0xeafffffe
                            BW Phy Addr : 0x53098000 Data : 0xa9739a4c
                            AW Phy Addr : 0x53098000 Data : 0xeafffffe
                            BW Phy Addr : 0x48180e10 Data : 0x00000003
                            AW Phy Addr : 0x48180e10 Data : 0x00000000
                            Phy Addr : 0x48180e14 Data : 0x00000007
            PRCM for IVHD2 is Done Successfully
    PRCM Initialization completed
    SysLink version : 2.20.02.20
    SysLink module created on Date:Dec 26 2012 Time:11:03:34
    FIRMWARE: I2cInit will be done by M3
    FIRMWARE: Memory map bin file not passed
    Usage : firmware_loader <Processor Id> <Location of Firmware> <start|stop> [-mmap <memory_map_file>] [-i2c <0|1>]
    ===Mandatory arguments===
    <Processor Id>         0: DSP, 1: Video-M3, 2: Vpss-M3
    <Location of Firmware> firmware binary file
    <start|stop>           to start/stop the firmware
    ===Optional arguments===
    -mmap                  input memory map bin file name
    -i2c                   0: i2c init not done by M3, 1(default): i2c init done by M3
    FIRMWARE: isI2cInitRequiredOnM3: 1
    FIRMWARE: Default memory configuration is used
    Firmware Loader debugging not configured
    Default FL_DEBUG: warning
    Allowed FL_DEBUG levels: error, warning, info, debug, log
    MemCfg: DCMM (Dynamically Configurable Memory Map) Version :  2.1.2.1
    FIRMWARE: 1 start Successful
    Loading HDVPSS Firmware
    FIRMWARE: I2cInit will be done by M3
    FIRMWARE: Memory map bin file not passed
    Usage : firmware_loader <Processor Id> <Location of Firmware> <start|stop> [-mmap <memory_map_file>] [-i2c <0|1>]
    ===Mandatory arguments===
    <Processor Id>         0: DSP, 1: Video-M3, 2: Vpss-M3
    <Location of Firmware> firmware binary file
    <start|stop>           to start/stop the firmware
    ===Optional arguments===
    -mmap                  input memory map bin file name
    -i2c                   0: i2c init not done by M3, 1(default): i2c init done by M3
    FIRMWARE: isI2cInitRequiredOnM3: 1
    FIRMWARE: Default memory configuration is used
    Firmware Loader debugging not configured
    Default FL_DEBUG: warning
    Allowed FL_DEBUG levels: error, warning, info, debug, log
    MemCfg: DCMM (Dynamically Configurable Memory Map) Version :  2.1.2.1
    FIRMWARE: 2 start Successful
    VPSS_FVID2: M3 firmware version 0x1000145 is newer,driver may not work properly.
    open /dev/fb0: No such file or directory
    HDMI W1 rev 2.0
    HDMI CEC Spec version 1.2
    I2C Bus Low?
    
    Starting system message bus: dbus.
    Starting telnet daemon.
    Starting syslogd/klogd: done
    Starting thttpd.
    Starting PVR
    Starting Matrix GUI application.
    
     _____                    _____           _         _
    |  _  |___ ___ ___ ___   |  _  |___ ___  |_|___ ___| |_
    |     |  _| .'| . | . |  |   __|  _| . | | | -_|  _|  _|
    |__|__|_| |__,|_  |___|  |__|  |_| |___|_| |___|___|_|
                  |___|                    |___|
    
    Arago Project http://arago-project.org dm816x-evm ttyO2
    
    Arago 2011.09 dm816x-evm ttyO2
    
    dm816x-evm login: root
    root@dm816x-evm:~#
    

     Additionally we would like to ask you about error in ti souces files. If you remember our reason by which we was need to create this post was case of absolutely empty console output. We have already desolve the problem by revising source code in evm.c file, because there was error for work with DDR2 when was detection of CPU revision. So it was bug of TI sources in uboot module. After correcting the error all become fine for uboot and we began to see what happens at console output. Are we right about this assumption?

       Dmitry.

  • Dmitry,

    dmitry chernov said:
    We have attached new log file - may be you can advise us what we can improve

    Let us start with u-boot.

    The DM816x u-boot wrongly reports 2GiB DRAM, while DM816x EVM has 1GiB DRAM:

    DRAM:  2 GiB

    This is fixed with the below u-boot patch:

    http://arago-project.org/git/projects/u-boot-omap3.git?p=projects/u-boot-omap3.git;a=commit;h=ef173b974184ed4b83a7ea956bf053ed7e84985a

    And you should modify it for 512 MiB.

    The EZSDK 5.05.02.00 comes with u-boot-2010.06-psp04.04.00.01, while we have some u-boot patches on top of this psp version:

    http://arago-project.org/git/projects/u-boot-omap3.git?p=projects/u-boot-omap3.git;a=shortlog;h=refs/heads/ti81xx-master

    You can apply all generic and ti81xx/ti816x related patches.

    "No ETH PHY detected!!!" - Seems that you have no Ethernet PHY populated on your custom board. So you will not be able to use Ethernet. See the below wiki pages:

    http://processors.wiki.ti.com/index.php/TI81XX_PSP_UBOOT_User_Guide#EMAC_Boot

    http://processors.wiki.ti.com/index.php/TI81XX_PSP_UBOOT_User_Guide#U-Boot_Network_configuration

    http://processors.wiki.ti.com/index.php/TI81xx_PSP_Porting_Guide#Ethernet_Driver_-_Adding_Custom_Ethernet_Phy

    Regards,
    Pavel

  • dmitry chernov said:
    We have attached new log file - may be you can advise us what we can improve in uImage or route file system settings.

    About the linux kernel, you can have a look into the below wiki page:

    http://processors.wiki.ti.com/index.php/TI81XX_PSP_User_Guide - you can remove the Ethernet driver if you are not planning to use it.

    "Kernel command line: console=ttyO2,115200n8 rootwait root=/dev/mmcblk0p2 rw mem=364M@0x80000000 mem=320M@0x9FC00000 vmalloc=500M  notifyk.vpssm3_sva=0xBF900000" - in the 512MB EZSDK memory map, we have mem=176M@0x80000000 (instead of mem=364M@0x80000000 mem=320M@0x9FC00000).

    Also, EZSDK 5.05.02.00 comes with linux-2.6.37-psp04.04.00.01, while we have many patches after this version:

    http://arago-project.org/git/projects/?p=linux-omap3.git;a=shortlog;h=refs/heads/ti81xx-master

    You can apply all generic and ti81xx/ti816x related patches.

    About the root filesystem, you can have a look in:

    DM816x_EZ_Software_Developers_Guide.pdf

    http://processors.wiki.ti.com/index.php/EZSDK_Filesystems

    http://processors.wiki.ti.com/index.php/Category:EZSDK

    Regards,
    Pavel

  •    Hello, Pavel.

    We have already set up the Ethernet - it's not a problem. Thank you for your other help once more.

       Dmitry.

  • Dmitry,

    dmitry chernov said:

    in function

    #ifdef CONFIG_TI816X_EVM_DDR2
    static void ddr_init_settings(int emif)
    {

    in strings as the below

    if(0 == get_cpu_rev())

    So it was incorrectness in identification cpu revision.

    Could you please provide more details on this? What is your part number? I see that get_cpu_rev() is identifying your DM816x part as PG2.1 device:

    TI8168-GP rev 2.1

    Regards,
    Pavel

  •  

       Pavel,

    The function get_cpu_rev() returns value "3". So not one of the branches does not matched with this value and DDR2 is not corrected working.

     We use DM8168 with the next revisions:

    TMS320DM8168CCYG2 and TMS320DM8168BCYG0

       Dmitry.

  • Dmitry,

    CCYG2 is 2.1 device

    BCYG0 is 2.0 device

    dmitry chernov said:
    The function get_cpu_rev() returns value "3". So not one of the branches does not matched with this value and DDR2 is not corrected working.

    The value of 3 is fine for 2.1 device. Looking into the DDR2 related code in evm.c, I am not sure if this is mistake. We have special handling for 1.0 and 1.1 devices:

    #ifdef CONFIG_TI816X_EVM_DDR2
    static void ddr_init_settings(int emif)
    {
        /* DLL Lockdiff */
        if(0 == get_cpu_rev()) - this code is executed only when you have 1.0 device with DDR2
        {
            __raw_writel(0xF, (DDRPHY_CONFIG_BASE + 0x028));
            __raw_writel(0xF, (DDRPHY_CONFIG_BASE + 0x05C));
            __raw_writel(0xF, (DDRPHY_CONFIG_BASE + 0x090));
            __raw_writel(0xF, (DDRPHY_CONFIG_BASE + 0x138));
            __raw_writel(0xF, (DDRPHY_CONFIG_BASE + 0x1DC));
            __raw_writel(0xF, (DDRPHY_CONFIG_BASE + 0x280));
            __raw_writel(0xF, (DDRPHY_CONFIG_BASE + 0x324));
        }

        if(1 == get_cpu_rev()) - this code is executed only when you have 1.1 device with DDR2
        {
            __raw_writel(0x6, (DDRPHY_CONFIG_BASE + 0x358));
        }

        /* setup rank delays */ - this code is executed for all devices (1.0, 1.1, 2.0, 2.1) with DDR2
        __raw_writel(0x1, (DDRPHY_CONFIG_BASE + 0x134));
        __raw_writel(0x1, (DDRPHY_CONFIG_BASE + 0x1D8));
        __raw_writel(0x1, (DDRPHY_CONFIG_BASE + 0x27C));
        __raw_writel(0x1, (DDRPHY_CONFIG_BASE + 0x320));


        __raw_writel(INVERT_CLK_OUT, (DDRPHY_CONFIG_BASE + 0x02C));    /* invert_clk_out cmd0 */
        __raw_writel(INVERT_CLK_OUT, (DDRPHY_CONFIG_BASE + 0x060));    /* invert_clk_out cmd0 */
        __raw_writel(INVERT_CLK_OUT, (DDRPHY_CONFIG_BASE + 0x094));    /* invert_clk_out cmd0 */


        __raw_writel(CMD_SLAVE_RATIO, (DDRPHY_CONFIG_BASE + 0x01C));    /* cmd0 slave ratio */
        __raw_writel(CMD_SLAVE_RATIO, (DDRPHY_CONFIG_BASE + 0x050));    /* cmd0 slave ratio */
        __raw_writel(CMD_SLAVE_RATIO, (DDRPHY_CONFIG_BASE + 0x084));    /* cmd0 slave ratio */

        __raw_writel(DQS_GATE_BYTE_LANE0, (DDRPHY_CONFIG_BASE + 0x108));
        __raw_writel(0x00000000, (DDRPHY_CONFIG_BASE + 0x10C));
        __raw_writel(DQS_GATE_BYTE_LANE1, (DDRPHY_CONFIG_BASE + 0x1AC));
        __raw_writel(0x00000000, (DDRPHY_CONFIG_BASE + 0x1B0));
        __raw_writel(DQS_GATE_BYTE_LANE2, (DDRPHY_CONFIG_BASE + 0x250));
        __raw_writel(0x00000000, (DDRPHY_CONFIG_BASE + 0x254));
        __raw_writel(DQS_GATE_BYTE_LANE3, (DDRPHY_CONFIG_BASE + 0x2F4));
        __raw_writel(0x00000000, (DDRPHY_CONFIG_BASE + 0x2F8));

        __raw_writel(WR_DQS_RATIO_BYTE_LANE0, (DDRPHY_CONFIG_BASE + 0x0DC));
        __raw_writel(0x0, (DDRPHY_CONFIG_BASE + 0x0E0));
        __raw_writel(WR_DQS_RATIO_BYTE_LANE1, (DDRPHY_CONFIG_BASE + 0x180));
        __raw_writel(0x0, (DDRPHY_CONFIG_BASE + 0x184));
        __raw_writel(WR_DQS_RATIO_BYTE_LANE2, (DDRPHY_CONFIG_BASE + 0x224));
        __raw_writel(0x0, (DDRPHY_CONFIG_BASE + 0x228));
        __raw_writel(WR_DQS_RATIO_BYTE_LANE3, (DDRPHY_CONFIG_BASE + 0x2C8));
        __raw_writel(0x0, (DDRPHY_CONFIG_BASE + 0x2CC));

        __raw_writel(WR_DATA_RATIO_BYTE_LANE0, (DDRPHY_CONFIG_BASE + 0x120));
        __raw_writel(0x0, (DDRPHY_CONFIG_BASE + 0x124));
        __raw_writel(WR_DATA_RATIO_BYTE_LANE1, (DDRPHY_CONFIG_BASE + 0x1C4));
        __raw_writel(0x0, (DDRPHY_CONFIG_BASE + 0x1C8));
        __raw_writel(WR_DATA_RATIO_BYTE_LANE2, (DDRPHY_CONFIG_BASE + 0x268));
        __raw_writel(0x0, (DDRPHY_CONFIG_BASE + 0x26C));
        __raw_writel(WR_DATA_RATIO_BYTE_LANE3, (DDRPHY_CONFIG_BASE + 0x30C));
        __raw_writel(0x0, (DDRPHY_CONFIG_BASE + 0x310));

        __raw_writel(RD_DQS_RATIO, (DDRPHY_CONFIG_BASE + 0x0C8));
        __raw_writel(0x0, (DDRPHY_CONFIG_BASE + 0x0CC));
        __raw_writel(RD_DQS_RATIO, (DDRPHY_CONFIG_BASE + 0x16C));
        __raw_writel(0x0, (DDRPHY_CONFIG_BASE + 0x170));
        __raw_writel(RD_DQS_RATIO, (DDRPHY_CONFIG_BASE + 0x210));
        __raw_writel(0x0, (DDRPHY_CONFIG_BASE + 0x214));
        __raw_writel(RD_DQS_RATIO, (DDRPHY_CONFIG_BASE + 0x2B4));
        __raw_writel(0x0, (DDRPHY_CONFIG_BASE + 0x2B8));

        __raw_writel(0x5, (DDRPHY_CONFIG_BASE + 0x00C));
        __raw_writel(0x5, (DDRPHY_CONFIG_BASE + 0x010));
        __raw_writel(0x5, (DDRPHY_CONFIG_BASE + 0x040));
        __raw_writel(0x5, (DDRPHY_CONFIG_BASE + 0x044));
        __raw_writel(0x5, (DDRPHY_CONFIG_BASE + 0x074));
        __raw_writel(0x5, (DDRPHY_CONFIG_BASE + 0x078));

        __raw_writel(0x4, (DDRPHY_CONFIG_BASE + 0x0A8));
        __raw_writel(0x4, (DDRPHY_CONFIG_BASE + 0x0AC));
        __raw_writel(0x4, (DDRPHY_CONFIG_BASE + 0x14C));
        __raw_writel(0x4, (DDRPHY_CONFIG_BASE + 0x150));
        __raw_writel(0x4, (DDRPHY_CONFIG_BASE + 0x1F0));
        __raw_writel(0x4, (DDRPHY_CONFIG_BASE + 0x1F4));
        __raw_writel(0x4, (DDRPHY_CONFIG_BASE + 0x294));
        __raw_writel(0x4, (DDRPHY_CONFIG_BASE + 0x298));

        if(0 == get_cpu_rev()) - this code is executed only when you have 1.0 device with DDR2
        {
            __raw_writel(0x5, (DDRPHY_CONFIG_BASE + 0x338));
            __raw_writel(0x5, (DDRPHY_CONFIG_BASE + 0x340));
            __raw_writel(0x5, (DDRPHY_CONFIG_BASE + 0x348));
            __raw_writel(0x5, (DDRPHY_CONFIG_BASE + 0x350));
        }

    }

    The situation is similar with DDR3:

    #ifdef CONFIG_TI816X_EVM_DDR3
    /*********************************************************************
     * Init DDR3 on TI816X EVM
     *********************************************************************/
    static void ddr_init_settings(int emif)
    {
        /*
         * DLL Lockdiff DLL_Lockdiff determines effectively is the
         * threshold internal to the DLL to indicate that the DLL has
         * lost lock.  When this happens the PHY currently issues an
         * internal reset.  The reset value for this is 0x4, which is
         * insufficient.  Set this to 15 (maximum possible - to
         * prevent this reset.  If the reset happens it would cause
         * the data to be corrupted.
         */
        if(0 == get_cpu_rev())
        {
            __raw_writel(0xF, DDRPHY_CONFIG_BASE + 0x028);
            __raw_writel(0xF, DDRPHY_CONFIG_BASE + 0x05C);
            __raw_writel(0xF, DDRPHY_CONFIG_BASE + 0x090);
            __raw_writel(0xF, DDRPHY_CONFIG_BASE + 0x138);
            __raw_writel(0xF, DDRPHY_CONFIG_BASE + 0x1DC);
            __raw_writel(0xF, DDRPHY_CONFIG_BASE + 0x280);
            __raw_writel(0xF, DDRPHY_CONFIG_BASE + 0x324);
        }

        /*
         * setup use_rank_delays to 1.  This is only necessary when
         * multiple ranks are in use.  Though the EVM does not have
         * multiple ranks, this is a good value to set.
         */
        __raw_writel(1, DDRPHY_CONFIG_BASE + 0x134);
        __raw_writel(1, DDRPHY_CONFIG_BASE + 0x1d8);
        __raw_writel(1, DDRPHY_CONFIG_BASE + 0x27c);
        __raw_writel(1, DDRPHY_CONFIG_BASE + 0x320);

        /* see ddr_defs.h for invert clock setting and details */
        __raw_writel(INVERT_CLOCK, DDRPHY_CONFIG_BASE + 0x02C); /* invert_clk_out cmd0 */
        __raw_writel(INVERT_CLOCK, DDRPHY_CONFIG_BASE + 0x060); /* invert_clk_out cmd0 */
        __raw_writel(INVERT_CLOCK, DDRPHY_CONFIG_BASE + 0x094); /* invert_clk_out cmd0 */

        /* with inv clkout: 0x100. no inv clkout: 0x80.  See ddr_defs.h */
        __raw_writel(CMD_SLAVE_RATIO, DDRPHY_CONFIG_BASE + 0x01C); /* cmd0 slave ratio */
        __raw_writel(CMD_SLAVE_RATIO, DDRPHY_CONFIG_BASE + 0x050); /* cmd1 slave ratio */
        __raw_writel(CMD_SLAVE_RATIO, DDRPHY_CONFIG_BASE + 0x084); /* cmd2 slave ratio */

        /* for ddr3 this needs to be set to 1 */
        __raw_writel(0x1, DDRPHY_CONFIG_BASE + 0x0F8); /* init mode */
        __raw_writel(0x1, DDRPHY_CONFIG_BASE + 0x104);
        __raw_writel(0x1, DDRPHY_CONFIG_BASE + 0x19C);
        __raw_writel(0x1, DDRPHY_CONFIG_BASE + 0x1A8);
        __raw_writel(0x1, DDRPHY_CONFIG_BASE + 0x240);
        __raw_writel(0x1, DDRPHY_CONFIG_BASE + 0x24C);
        __raw_writel(0x1, DDRPHY_CONFIG_BASE + 0x2E4);
        __raw_writel(0x1, DDRPHY_CONFIG_BASE + 0x2F0);

        /****  setup the initial levelinihg ratios ****/
        /* these are derived from board delays and may be different for different boards
         * see ddr_defs.h
         * we are setting the values here for both the ranks, though only one is in use
         */
        __raw_writel((WR_DQS_RATIO_3 << 10) | WR_DQS_RATIO_3, DDRPHY_CONFIG_BASE + 0x0F0); /*  data0 writelvl init ratio */
        __raw_writel(0x00000, DDRPHY_CONFIG_BASE + 0x0F4);   /*   */
        __raw_writel((WR_DQS_RATIO_2 << 10) | WR_DQS_RATIO_2, DDRPHY_CONFIG_BASE + 0x194); /*  data1 writelvl init ratio */
        __raw_writel(0x00000, DDRPHY_CONFIG_BASE + 0x198);   /*   */
        __raw_writel((WR_DQS_RATIO_1 << 10) | WR_DQS_RATIO_1, DDRPHY_CONFIG_BASE + 0x238); /*  data2 writelvl init ratio */
        __raw_writel(0x00000, DDRPHY_CONFIG_BASE + 0x23c);   /*   */
        __raw_writel((WR_DQS_RATIO_0 << 10) | WR_DQS_RATIO_0, DDRPHY_CONFIG_BASE + 0x2dc); /*  data3 writelvl init ratio */
        __raw_writel(0x00000, DDRPHY_CONFIG_BASE + 0x2e0);   /*   */


        __raw_writel((RD_GATE_RATIO_3 << 10) | RD_GATE_RATIO_3, DDRPHY_CONFIG_BASE + 0x0FC); /*  data0 gatelvl init ratio */
        __raw_writel(0x0, DDRPHY_CONFIG_BASE + 0x100);
        __raw_writel((RD_GATE_RATIO_2 << 10) | RD_GATE_RATIO_2, DDRPHY_CONFIG_BASE + 0x1A0); /*  data1 gatelvl init ratio */
        __raw_writel(0x0, DDRPHY_CONFIG_BASE + 0x1A4);
        __raw_writel((RD_GATE_RATIO_1 << 10) | RD_GATE_RATIO_1, DDRPHY_CONFIG_BASE + 0x244); /*  data2 gatelvl init ratio */
        __raw_writel(0x0, DDRPHY_CONFIG_BASE + 0x248);
        __raw_writel((RD_GATE_RATIO_0 << 10) | RD_GATE_RATIO_0, DDRPHY_CONFIG_BASE + 0x2E8); /*  data3 gatelvl init ratio */
        __raw_writel(0x0, DDRPHY_CONFIG_BASE + 0x2EC);

    #ifdef CONFIG_TI816X_DDR3_PG_1_0
        if(HACK_EYE_TRAINING){
            __raw_writel((RD_DQS_FORCE_3 << 9) | RD_DQS_FORCE_3, DDRPHY_CONFIG_BASE + 0x0D4);
            __raw_writel(0x00000001, DDRPHY_CONFIG_BASE + 0x0D0);

            __raw_writel((RD_DQS_FORCE_2 << 9) | RD_DQS_FORCE_2, DDRPHY_CONFIG_BASE + 0x178);
            __raw_writel(0x00000001, DDRPHY_CONFIG_BASE + 0x174);

            __raw_writel((RD_DQS_FORCE_1 << 9) | RD_DQS_FORCE_1, DDRPHY_CONFIG_BASE + 0x21C);
            __raw_writel(0x00000001, DDRPHY_CONFIG_BASE + 0x218);

            /* rd dqs - lane 0 */
            __raw_writel((RD_DQS_FORCE_0 << 9) | RD_DQS_FORCE_0, DDRPHY_CONFIG_BASE + 0x2C0);
            __raw_writel(0x00000001, DDRPHY_CONFIG_BASE + 0x2BC);
        }
        /* DDR3 */
    #endif

        __raw_writel(0x5, DDRPHY_CONFIG_BASE + 0x00C);     /* cmd0 io config - output impedance of pad */
        __raw_writel(0x5, DDRPHY_CONFIG_BASE + 0x010);     /* cmd0 io clk config - output impedance of pad */
        __raw_writel(0x5, DDRPHY_CONFIG_BASE + 0x040);     /* cmd1 io config - output impedance of pad */
        __raw_writel(0x5, DDRPHY_CONFIG_BASE + 0x044);     /* cmd1 io clk config - output impedance of pad */
        __raw_writel(0x5, DDRPHY_CONFIG_BASE + 0x074);     /* cmd2 io config - output impedance of pad */
        __raw_writel(0x5, DDRPHY_CONFIG_BASE + 0x078);     /* cmd2 io clk config - output impedance of pad */
        __raw_writel(0x4, DDRPHY_CONFIG_BASE + 0x0A8);     /* data0 io config - output impedance of pad */
        __raw_writel(0x4, DDRPHY_CONFIG_BASE + 0x0AC);     /* data0 io clk config - output impedance of pad */
        __raw_writel(0x4, DDRPHY_CONFIG_BASE + 0x14C);     /* data1 io config - output impedance of pa     */
        __raw_writel(0x4, DDRPHY_CONFIG_BASE + 0x150);     /* data1 io clk config - output impedance of pad */
        __raw_writel(0x4, DDRPHY_CONFIG_BASE + 0x1F0);     /* data2 io config - output impedance of pa */
        __raw_writel(0x4, DDRPHY_CONFIG_BASE + 0x1F4);     /* data2 io clk config - output impedance of pad */
        __raw_writel(0x4, DDRPHY_CONFIG_BASE + 0x294);     /* data3 io config - output impedance of pa */
        __raw_writel(0x4, DDRPHY_CONFIG_BASE + 0x298);     /* data3 io clk config - output impedance of pad */

        if(0 == get_cpu_rev())
        {
            __raw_writel(0x5, DDRPHY_CONFIG_BASE + 0x338);     /* fifo_we_out0  - output impedance of pad */
            __raw_writel(0x5, DDRPHY_CONFIG_BASE + 0x340);     /* fifo_we_out1 - output impedance of pad */
            __raw_writel(0x5, DDRPHY_CONFIG_BASE + 0x348);     /* fifo_we_in2 - output impedance of pad */
            __raw_writel(0x5, DDRPHY_CONFIG_BASE + 0x350);     /* fifo_we_in3 - output impedance of pad */
        }
    }

  • Hello, Pavel!

    I apologize for the long silence, I was away.

    We'll answer for your question soon.

       Now we are faced with another problem. We have a worked ethernet with ksz9021gn only at 10Mbps. We refer to the manufacturer of the controller-he said that we have a correct scheme. We checked the frequency-all right, except that there are frequency 25MHz instead 125MHz for working with 1000MHz.
     
       Best regards,
         Dmitry.