Hi All,
In DVRRDK, I find the following description in hw board schematic
"Configure McASP such that the Rx section operates off of the Tx section clocks."
1) It means that DVRRDK used TX_SYNC mode(use ACLKX/AFSX), ACLKR/AFSR is useless?
2) If the codec(aic3101) BCLK/WCLK connected to ACLKR/AFSR and configure McASP as TX_ASYNC mode. It only works in i2s record mode and fail in playback mode?(because tx clock is not connected)
3) In TX_SYNC mode, AHCLKR and AHCLKX both could feed to the codec as MCLK?
McASP AHCLKR connect to AIC3101 MCLK
McASP ACLKX connect to AIC3101 BCLK
McASP AFSX connect to AIC3101 WCLK
Is it ok for i2s playback mode and record mode?
Thanks in advance.
BR
Steven
