How can the DM8168 PCIESS initiates a Memory Read / Write request’s TLP ?

       I use DM8168 PCIESS as RC,virtex 5 FPGA  as an  EP, FPGA captures video information and transfer the video to DM1868 by PCIE,the EP Core is a target-only device,so it cannot send TLPs initiatively.

      But I donot kown how can the DM8168 PCIESS initiates a Memory Read / Write request’s TLP.

      Can you help me?thank you very much.