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DM8168: DDR Calibration using CCS

HI,

I am using the latest EZSDK, 5_05_02_00 for DM8168 board. I want to do DDR calibration for my target using CCS.

I am using DDR3 with the capacity of 1GB with Non-interleaved method configuration. How can I do it with the help of Code composer studio.

Thanks in advance.

Regards,

Salih

  • Salih,

    Refer to the below links:

    http://processors.wiki.ti.com/index.php/DM816x_C6A816x_AM389x_DDR3_Init

    http://processors.wiki.ti.com/images/b/b2/DDR3-Bring-up-Overview.pdf

    http://processors.wiki.ti.com/index.php/DDR_Interface_Drive_Strength

    BR
    Pavel

  • Dear Pavel,

    I have successfully launched the CCS studio and I can able to connect the target using JTAG Emulator.

    While running script Script -> DM816x External Memories -> DDR3_796MHZ_doall, I am getting the below messages in CCS log.

    CortxA8: Output:     DM816x DDR PLL Init is in Progress for 796.5 MHz DDR Clock, Please wait .....
    CortxA8: Output:     DM816x DDR PLL Init is Done .....
    CortxA8: Output:     DM816x DDR2/3 PRCM Init is in progress .....
    CortxA8: Output:     DM816x DDR2/3 PRCM Init is Done .....
    CortxA8: Output:     Initializing EMIF1 .....
    CortxA8: Output: DDR3 SWLEVELING DONE FOR EMIF0
    CortxA8: Output: DDR3 SWLEVELING DONE FOR EMIF1
    CortxA8: Output:     DM816x EMIF Init is Done @ 796.5 MHz Clock Rate.....
    CortxA8: Output:     PRCM for OCMCRAM0/1 Initialization in Progress

    After the above print, it is not completing with success for OCMCRAM test and its keep on waiting. Can you please suggest the solution to solve this issue.

    And also is it possible to calibrate our DDR3 using CCS app?.

    Thanks in advance.

    Regards,

    Salih

  • Salih,

    Muhammad Salih said:

    While running script Script -> DM816x External Memories -> DDR3_796MHZ_doall, I am getting the below messages in CCS log.

    CortxA8: Output:     DM816x DDR PLL Init is in Progress for 796.5 MHz DDR Clock, Please wait .....
    CortxA8: Output:     DM816x DDR PLL Init is Done .....
    CortxA8: Output:     DM816x DDR2/3 PRCM Init is in progress .....
    CortxA8: Output:     DM816x DDR2/3 PRCM Init is Done .....
    CortxA8: Output:     Initializing EMIF1 .....
    CortxA8: Output: DDR3 SWLEVELING DONE FOR EMIF0
    CortxA8: Output: DDR3 SWLEVELING DONE FOR EMIF1
    CortxA8: Output:     DM816x EMIF Init is Done @ 796.5 MHz Clock Rate.....
    CortxA8: Output:     PRCM for OCMCRAM0/1 Initialization in Progress

    This is what I have on the DM816x TI EVM:

    CortexA8: Output:     Device type is GP
    CortexA8: Output:     DM816x Main PLL Init is in Progress, Please wait .....
    CortexA8: Output:     DM816x Main PLL Init is Done .....
    CortexA8: Output:     DM816x DDR PLL Init is in Progress for 796.5 MHz DDR Clock, Please wait .....
    CortexA8: Output:     DM816x DDR PLL Init is Done .....
    CortexA8: Output:     DM816x DDR2/3 PRCM Init is in progress .....
    CortexA8: Output:     DM816x DDR2/3 PRCM Init is Done .....
    CortexA8: Output:     Initializing EMIF1 .....
    CortexA8: Output: DDR3 SWLEVELING DONE FOR EMIF0
    CortexA8: Output: DDR3 SWLEVELING DONE FOR EMIF1
    CortexA8: Output:     DM816x EMIF Init is Done @ 796.5 MHz Clock Rate.....
    CortexA8: Output:     PRCM for OCMCRAM0/1 Initialization in Progress
    CortexA8: Output:     OCMCRAM0 & OCMCRAM1 Accesses are PASSED
    CortexA8: Output:     PRCM for OCMCRAM0/1 Initialization in Done

    Do you initialize the MAIN PLL?

    CortexA8: Output:     DM816x Main PLL Init is in Progress, Please wait .....
    CortexA8: Output:     DM816x Main PLL Init is Done .....

    If yes, can you put prints inside the OCMCRAMClkEnable() function and see at which line exactly it hangs? I suspect it is waiting in some of the while loops.

    BR
    Pavel

  • Hi Pavel,

    You are correct. It is exactly hanging in one while loop in the function OCMCRAMClkEnable ();

    while(((RD_MEM_32(CM_ALWON_OCMC_0_CLKSTCTRL) & 0x100)>>8)!=1);

    Its stopping in the above while loop its keep on waiting.

    Please suggest the solution to solve this issue.

    And also is it possible to calibrate our DDR3 using CCS app?.

    Thanks in advance.

    Regards,

    Salih

  • Salih,

    Muhammad Salih said:

    You are correct. It is exactly hanging in one while loop in the function OCMCRAMClkEnable ();

    while(((RD_MEM_32(CM_ALWON_OCMC_0_CLKSTCTRL) & 0x100)>>8)!=1);

    Its stopping in the above while loop its keep on waiting.

    Please suggest the solution to solve this issue.

    Have you enabled the MAIN PLL? I can not see the MAIN PLL init in your CCS console output.

    Muhammad Salih said:
    And also is it possible to calibrate our DDR3 using CCS app?.

    http://processors.wiki.ti.com/index.php/Sitara_Linux_Training:_Tuning_the_DDR3_Timings_on_BeagleBoneBlack#Description_2

    This section will take you through the steps involved in setting up CCS to communicate with the board as well as running the calibration software.

    7. The software will begin calibrating

    The above is for AM335x, for DM816x should be similar.

    See also:

    http://processors.wiki.ti.com/index.php/Setting_up_AM35x_SDRC_registers

    http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/717/p/218073/768463.aspx#768463

    http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/717/t/290832.aspx

    Regards,
    Pavel

  • Hi,

    I have enabled the Main PLL. I missed to copy the above logs. Please give the solution to solve this issue.

    Thanks in advance.

    Regards,

    Salih

  • Salih,

    Muhammad Salih said:
    Please give the solution to solve this issue.

    As this OCMCRAMClkEnable() function runs fine on the DM816x TI EVM and failed on your DM816x custom board, this is indication for a HW malfunction of your custom board.

    This while loop is expecting the OCMC RAM0 clock to become active, it is waiting till the read only bit CM_ALWON_OCMC_0_CLKSTCTRL[8] CLKACTIVITY_OCMC_0_GCLK transition from 0 (gated) to 1 (active). In your custom board, by some reason this clock can never go active. Your clock system is not stable.

    Refer to the DM816x EVM reference design schematics and DM816x datasheet. You should have 27MHz crystal oscillator supplying the MAIN PLL. The output clock of the MAIN PLL is sysclk5 (with frequency of 250MHz), and this sysclk5 is input clock (interface and functional clock) to the OCMC RAM.

    BR
    Pavel

  • Hi,

    Thank you very much for your input. I have changed my customized SOM which Silicon Rev2.0. In that, I can able to run the testing successfully. But once I loaded the program file DDR3_SlaveRatio_ByteWiseSearch_TI816x.out, I am getting the below error message and I am not seeing the "Running the Slave Ratio Search Program" application.

    Can't find a source file at "C:\Documents and Settings\x0157560\Desktop\DDR3_slave_ratio_search_byte_wise\Debug/../arm_boot.asm

    So, please can you suggest me to fix this issue.

    Thanks in advance.

    Regards,

    Salih

  • Salih,

    Muhammad Salih said:

    But once I loaded the program file DDR3_SlaveRatio_ByteWiseSearch_TI816x.out, I am getting the below error message and I am not seeing the "Running the Slave Ratio Search Program" application.

    Can't find a source file at "C:\Documents and Settings\x0157560\Desktop\DDR3_slave_ratio_search_byte_wise\Debug/../arm_boot.asm

    This message is normal, as you do not have the source code for the .out file, thus CCS can not locate it. You can ignore this message and continue according to the instructions.

    See also the below e2e threads:

    http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/717/t/170053.aspx

    http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/717/t/245918.aspx

    BR
    Pavel

  • Hi Pavel,

    Thank you very much for your inputs. I have followed the procedure as per the steps in the TI Wiki. The Link is below:

    http://processors.wiki.ti.com/index.php/DM816x_C6A816x_AM389x_DDR3_Init

    But, after loaded the program, DDR3_SlaveRatio_ByteWiseSearch_TI816x.out I am not seeing any running application in my CCS console. The step is below:

    • Select Run -> Load -> Load Program. Select the CCS program DDR3_SlaveRatio_ByteWiseSearch_TI816x.out for loading.

    What might be the reason for this application not running in my target and CCS.

    Please provide any solution/suggestion to solve this issue.

    Thanks in advance.

    Regards,
    Salih

  • Muhammad Salih said:

    But, after loaded the program, DDR3_SlaveRatio_ByteWiseSearch_TI816x.out I am not seeing any running application in my CCS console. The step is below:

    • Select Run -> Load -> Load Program. Select the CCS program DDR3_SlaveRatio_ByteWiseSearch_TI816x.out for loading.

    What might be the reason for this application not running in my target and CCS.

    See the below e2e threads:

    http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/717/t/170053.aspx

    http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/717/t/245918.aspx

  • Hi Pavel,

    Thanks for your input. But I want to know how may I calculate/get the proper values for CLK trace and DQS trace for my target.

    Thanks in advance.

    Regards,

    Salih

  • Muhammad Salih said:
    But I want to know how may I calculate/get the proper values for CLK trace and DQS trace for my target

    These are the PCB trace length (in inches) for the byte lanes. These are calculated based on the board topology. CK (CLK) and DQS trace length is the sum of traces before and after the termination resistors.

    RD DQS is board independent and hence is a constant value.

    Please note that all inputs need to be approximate and not necessarily exact. The software leveling program uses the seed values (from the xls), does a search around these values and comes up with the true optimum values.

    See also the below e2e thread:

    BR
    Pavel

  • Hi Pavel,

    Actually, what this clock (CM_ALWON_OCMC_0_CLKSTCTRL)  will do?. Is this clock is mandatory to boot the DDR3 at 796Mhz?.

    Currently, this clock is becoming active with Rev2.0 DM8168 processor and its not happening with Rev2.1 processor.

    Is there any changes needs to be done in the GEL file particularly for Rev2.1 in order to make execute it successfully?.

    Here in my case, I can't able to boot my target with DDR3@796MHz. But I can able to boot it @675MHz.

    And also currently, with Rev2.0, I couldn't launch the (Running the Slave Ratio Search Program) application in the CCS

    Please suggest any idea to solve this issue?.

    Thanks in advance,

    Regards,
    Salih

  • Salih,

    Muhammad Salih said:
    Actually, what this clock (CM_ALWON_OCMC_0_CLKSTCTRL)  will do?

    This clock will enable the OCMC0 RAM. OCMC0 RAM is used by ROM Code and NOR u-boot:

    Muhammad Salih said:
    Here in my case, I can't able to boot my target with DDR3@796MHz. But I can able to boot it @675MHz.

    This should be issue with the software leveling. Revise your SW leveling procedure.

    BR
    Pavel

  • Hi Pavel,

    Thanks for your inputs. You meant like, should I to do source code changes in U-boot. If so, where I supposed to change this SW leveling?

    Thanks in advance.

    Regards,
    Salih
  • Hi,

    I am facing this issue only in the DM8168 with Silicon Rev2.1 and I can able to boot it with Silicon Rev2.0. Is there any changes needs to be done with Rev2.1 SOM from Rev2.1. Any revision history related documents are available. If so, please provide the same for this.

    Thanks in advance.

    Regards,
    Salih
  • Salih,

     

    Muhammad Salih said:
    You meant like, should I to do source code changes in U-boot. If so, where I supposed to change this SW leveling?

    Refer to the below wiki page:

    See also the below e2e thread:

    BR
    Pavel

  • Salih,

    Muhammad Salih said:
    I am facing this issue only in the DM8168 with Silicon Rev2.1 and I can able to boot it with Silicon Rev2.0. Is there any changes needs to be done with Rev2.1 SOM from Rev2.1. Any revision history related documents are available. If so, please provide the same for this.

    The differences between DM816x 2.0 and 2.1 silicon revisions are documented in the DM816x Silicon Errata.

    BR
    Pavel

  • Hi,

    I have gone through those links. I think you are repeating the same. As for me, the GEL file is not executing completely.
    As you told in the previous post to revise the SW leveling procedure. How can I revise my software procedure.?.
    Sorry, I am not getting clearly. I have followed those steps in the CCS. Since OCMC clock is not active in my target.

    If it is the case, is the DDR3 will not boot @796MHz ?. Even its working @675Mhz?.

    Thanks in advance.

    Regards,
    Salih
  • Hi,

    Muhammad Salih said:
    I think you are repeating the same.

    Yes, because you are asking the same.

    Muhammad Salih said:
    As for me, the GEL file is not executing completely.

    Can you provide console output?

    Muhammad Salih said:
    As you told in the previous post to revise the SW leveling procedure. How can I revise my software procedure.?.
    Sorry, I am not getting clearly. I have followed those steps in the CCS. Since OCMC clock is not active in my target.

    If it is the case, is the DDR3 will not boot @796MHz ?. Even its working @675Mhz?.

    This is indication that your DDR3 timings are not set to optimal values and DDR3 is not stable at highest frequency. The DDR3 timing values can be set through software leveling. If you are not able to work with 796MHz, but able to work with 675Mhz, then most probably your DDR3 timing settings are not set to optimal values.

    Make sure also your chip is DDR3-1600

    Software leveling/calibration is a procedure by which the time delays between DDR3 signals can be compensated by appropriate values programmed in the
    corresponding slave ratio registers of the DDR PHY.

    On all silicon revisions (except silicon revision 1.0), DDR2 and DDR3 require software leveling to tune the device IOs to the timing characteristics of a particular board design.


    See also the below e2e threads:

    http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/717/t/334550

    Regards,
    Pavel