Hi All,
As per Rev F datasheet of DM816x, the PLL min cycles mentioned in Table 8-13 and the maximum SYSCLK frequencies mentioned in Table 8-15 don’t match. These were matching in the earlier Rev E datasheet.
Example: (based on Rev F datasheet) For SYSCLK2 speed grade 4, 1200MHz is max frequency as per Table 8-15 whereas from Table 8-13, it is 1350MHz (1/741ps) for Clock2.
Can anyone from TI please give the reasoning for it?
Regards,
Shareef