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DM8168 DDR3 init problem in u-boot

Dear TI,


I have 2 custom boards working on dm816x. Both have same DDR layout based on dm816x evm from Spectrum Digital.

DDR configuration is 8 chips in total, 4 chips per EMIF.

Board #1 DDR3: MT41J128M8JP-15E (1Gb 128 x8 @667MHz). This one is working fine.

Board #2 DDR3: MT41J256M8DA-093 (2Gb 256 x8 @1066MHz). This one hangs at this line during EMIF0 init

       

__raw_writel((0x10000000|EMIF_SDREF), EMIF4_0_SDRAM_REF_CTRL);

I use evm DDR timings for 796MHz.

 

What I've done so far after reading about this issue:

1. Applied u-boot patches http://arago-project.org/git/projects/u-boot-omap3.git?p=projects/u-boot-omap3.git;a=shortlog;h=refs/heads/ti81xx-master

#define EMIF_TIM1   0x1557DA3D
#define EMIF_TIM2   0x50877FEC
#define EMIF_TIM3   0x001F87FF
#define EMIF_SDREF  0x10001840 
#define EMIF_SDCFG  0x7AA73B32
#define EMIF_PHYCFG 0x00000110

  • Applied those in ddr_defs_ti816x.h

3. Tried modifying LISA registers to disable interleaving

Nothing worked so far, although Board #1 boots with this settings.

I don't exclude hardware problem, however we have manufactured a few in one batch and the only differences are those memory chips.

Are the timings wrong? What else can I do?

Please advice. Thanks,

Michal

  • Sth went missing:

    2. Followed steps from this doc: http://processors.wiki.ti.com/index.php/DM816x_C6A816x_AM389x_DDR3_Init

  • Thanks for answer.

    I've checked voltages - seems OK.
    In some threads there are mentioned terminating resistors, I've also checked those - seems OK.
    We've got 2 boards #1 that work, and 4 #2 that not work, so it's hard to believe that all four have 32 bad DDR chips.

    I'm more likely to consider timing issue. However, I don't know why board #1 works with timing parameters calculated for board #2. It suggests that for initializing DDR they are not crucial.

    What am I doing wrong for calculating above timings?

    Michal
  • There is CCS based DDR test program which can be downloaded here
    support.spectrumdigital.com/.../evm816x_BSL.zip

    When you do DDR SW leveling, have you also modify the DDR timing parameter in the gel file?
  • The problem is I don't have JTAG interface, so I cannot use CSS.

    I used File:RatioSeed.zip to obtain seed values. I understand that these values are initial ones and they have to be tuned with CSS script.
    However, I used them in ddr_defs_ti816x.h

    #define RD_DQS_GATE_LANE3      ((emif == 0) ? 0x191 : 0x191) 
    #define RD_DQS_GATE_LANE2      ((emif == 0) ? 0x1BC : 0x1BC) 
    #define RD_DQS_GATE_LANE1      ((emif == 0) ? 0x1F4 : 0x1F4) 
    #define RD_DQS_GATE_LANE0      ((emif == 0) ? 0x21E : 0x21E) 
    
    #define RD_DQS_LANE3           ((emif == 0) ? 0x40 : 0x40) 
    #define RD_DQS_LANE2           ((emif == 0) ? 0x40 : 0x40) 
    #define RD_DQS_LANE1           ((emif == 0) ? 0x40 : 0x40) 
    #define RD_DQS_LANE0           ((emif == 0) ? 0x40 : 0x40) 
    
    #define WR_DQS_LANE3           ((emif == 0) ? 0x96 : 0x96)
    #define WR_DQS_LANE2           ((emif == 0) ? 0x9E : 0x9E) 
    #define WR_DQS_LANE1           ((emif == 0) ? 0xA1 : 0xA1) 
    #define WR_DQS_LANE0           ((emif == 0) ? 0xAA : 0xAA) 

    Those work for Board #1 not for Board #2.

  • JTAG connectivity is required for board commissioning.  You will need to modify a board to add it so that CCS can be used.

    Tom

  • It's clear that JTAG and CSS are required for custom design. But I have DM8168 evm based layout.

    What I don't understand why Board #1 with DDR3 @796MHz clock and timings calculated for Board #2 works, Board #2 with the same DDR3 timings and clock and with memories that (according to Micron spec) are fully back compatible to DDR3-1600 does not.

    Has someone used 2Gb density chips successfully in DM8168? Are there any modifications needed for DDR3 memory controller registers?

    Default u-boot configuration sets address space of 2GB (LISA registers). As I understand, if I put 8x2Gb DDR3 chips into DM8168 evm default u-boot configuration should work for this board?

    Thanks,

    Michal