Dear TI,
I have 2 custom boards working on dm816x. Both have same DDR layout based on dm816x evm from Spectrum Digital.
DDR configuration is 8 chips in total, 4 chips per EMIF.
Board #1 DDR3: MT41J128M8JP-15E (1Gb 128 x8 @667MHz). This one is working fine.
Board #2 DDR3: MT41J256M8DA-093 (2Gb 256 x8 @1066MHz). This one hangs at this line during EMIF0 init
__raw_writel((0x10000000|EMIF_SDREF), EMIF4_0_SDRAM_REF_CTRL);
I use evm DDR timings for 796MHz.
What I've done so far after reading about this issue:
1. Applied u-boot patches http://arago-project.org/git/projects/u-boot-omap3.git?p=projects/u-boot-omap3.git;a=shortlog;h=refs/heads/ti81xx-master
- Used File:DM816x C6A816x AM389x EMIF4 Register Settings.zip with MT41J256M8DA-093 spreadsheet to obtain timing parameters:
#define EMIF_TIM1 0x1557DA3D #define EMIF_TIM2 0x50877FEC #define EMIF_TIM3 0x001F87FF #define EMIF_SDREF 0x10001840 #define EMIF_SDCFG 0x7AA73B32 #define EMIF_PHYCFG 0x00000110
- Applied those in ddr_defs_ti816x.h
3. Tried modifying LISA registers to disable interleaving
Nothing worked so far, although Board #1 boots with this settings.
I don't exclude hardware problem, however we have manufactured a few in one batch and the only differences are those memory chips.
Are the timings wrong? What else can I do?
Please advice. Thanks,
Michal